CN102479132A - Multi-chip test system and its test method - Google Patents

Abstract

A multi-chip test system and a test method thereof are provided, which utilize a programmable controller to connect in series a plurality of chips with joint test task group JTAG interfaces to carry out function detection. The test system comprises a device to be tested and a control device. The device to be tested comprises a plurality of chips, a programmable controller and second JTAG interfaces, wherein each chip is provided with a first JTAG interface, the programmable controller is coupled to each chip through the first JTAG interface, the second JTAG interfaces are connected to the programmable controller, and the control device is connected to the second JTAG interfaces and used for sending a switching instruction to the programmable controller. The testing method comprises the steps of firstly receiving a switching instruction to select a chip to be tested, then sending a testing signal to the chip to be tested according to the chip to be tested, and returning a testing result to the programmable controller by the chip to be tested according to the testing signal.

Description

Multi-chip test system and its test method

technical field

The present invention relates to a multi-chip testing system and its method, in particular to a multi-chip testing system which utilizes a programmable controller (Complex Programmable Logic Device, CPLD) to connect multiple A chip, a test system and method for performing chip function detection.

Background technique

Generally speaking, after the circuit board is manufactured, some flying probe tests are often carried out to ensure that there is no open circuit or short circuit (Open/Short) on the integrated circuits set on the circuit board. To test the operation of integrated circuits, it is often necessary to go through multiple tedious simulations and tests in order to test the operation of each integrated circuit.

However, the development of integrated circuit testing is to use a Joint Test Action Group (JTAG) interface for internal testing. The common testing method of JTAG is to access the integrated circuit interface and use the boundary scan method. Testing, in simple terms, is to input a test signal to the integrated circuit. If the signal output by the integrated circuit is a wrong signal, it can be known that an error occurs in the internal circuit of the integrated circuit. JTAG is also known as the Standard Test Access Port and Boundary Scan Architecture Protocol, and this protocol has been certified by the Institute of Electrical and Electronics Engineers (IEEE), which is the IEEE 1149.1 standard.

At present, the design of computer motherboards is to reserve test points for detection. Needle bed equipment is needed to handle the testing process. However, there are many chips on the motherboard and the test specifications of each chip are not uniform. In addition to the tedious and complicated process, it is also necessary to design suitable needle bed testing equipment, which in turn increases the production cost a lot.

Therefore, how to propose a method or means that can reduce the cost of production, reduce the complexity of the testing process, and improve the efficiency and speed of testing is the goal that people in the relevant professional fields strive to improve.

Contents of the invention

The purpose of the present invention is to provide a multi-chip testing system and method thereof, which utilizes a programmable controller to connect a plurality of chips with a joint test working group (Joint Test Action Group, JTAG) interface in series to carry out chip function detection, therefore , through a single window to detect multiple chips, to reduce the design of the JTAG interface detection points of each chip, to simplify the difficulty and complexity of the test process, and to improve the efficiency and speed of detection.

According to the multi-chip testing system disclosed in the present invention, it includes a device under test and a control device. The device to be tested includes a plurality of chips, a programmable controller, and a second JTAG interface, each of which has a first JTAG interface, the programmable controller is coupled to the corresponding chip through the first JTAG interface, and the second JTAG The interface is connected to the programmable controller, and the control device is connected to the second JTAG interface for sending a switching command to the programmable controller.

The switching command is sent to the programmable controller through the second JTAG interface. The programmable controller selects the corresponding chip according to the switching command, and sends a test command to detect the chip, and the programmable controller returns a test result to the control panel. device.

According to the multi-chip testing method disclosed in the present invention, which is applied to the above-mentioned multi-chip testing system, the testing method first receives a switching instruction from a programmable controller to select at least one chip to be tested, and then sends a test signal to the selected chip to be tested, and make the chip to be tested generate a test result, and finally return the test result to the programmable controller.

Therefore, through the above-mentioned test system and test method, the present invention connects a programmable controller to a plurality of chips with JTAG interfaces, and the user can send a switching command through the control device to select the chip to be tested. The programming controller then selects the chip according to the switching instruction, and sends a test signal conforming to the test specification of the corresponding chip. In this way, the design of the JTAG interface detection points of each chip is reduced to simplify the difficulty and complexity of the test process, thereby improving the efficiency and speed of detection.

The present invention will be described in detail below in conjunction with the accompanying drawings and specific embodiments, but not as a limitation of the present invention.

Description of drawings

The schematic diagram of Fig. 1 multi-chip testing system of the present invention;

Fig. 2 is the internal functional block diagram of the programmable controller in Fig. 1;

Fig. 3 is a flow chart of the multi-chip detection method of the present invention.

Among them, reference signs

1 device under test

10 chips

101 First Joint Testing Working Group

2 Second Joint Testing Working Group

3 programmable controller

30 multitasking units

31 logical units

4 control device

40 Third Joint Testing Working Group

41 microprocessor

42 Universal Serial Bus interface

43 operating device

Detailed ways

Below in conjunction with accompanying drawing, structural principle and working principle of the present invention are specifically described:

Please refer to FIG. 1 and FIG. 2 . FIG. 1 is a schematic diagram of the multi-chip testing system of the present invention, and FIG. 2 is a diagram of internal functional blocks of the programmable controller in FIG. 1 .

The multi-chip testing system of the present invention includes a device under test 1 and a control device 4 . The device under test 1 comprises a plurality of chips 10, a programmable controller 3, and a second Joint Test Action Group (JTAG) interface 2, and each chip 10 has a first JTAG interface 101 respectively, and the programmable controller 3 The first JTAG interface 101 is coupled to the corresponding chip 10, the second JTAG interface 2 is connected to the programmable controller 3, the control device 4 has a third JTAG interface 40, and the third JTAG interface 40 is connected to the second JTAG The interface 2 , the control device 4 sends a switching instruction to the programmable controller 3 .

The switching instruction is sent to the programmable controller 3 through the second JTAG interface 2, and the programmable controller 3 selects the corresponding chip 10 according to the switching instruction, and sends at least one test signal to the corresponding at least one chip 10, and the corresponding chip 10 generates Once the test result is obtained, the programmable controller 3 sends back the test result to the control device 4 .

In this embodiment, the device under test 1 can be a computer motherboard, and each chip 10 can be a central processing unit, a south bridge chip or a north bridge chip, but it is not limited thereto. The programmable controller 3 includes a logic unit 31 and a multitasking unit 30. The logic unit 31 is connected to the control device 4 for receiving the switching command and sending a corresponding test signal according to the switching command. The multitasking unit 30 has a first interface and a plurality of second interfaces, the first interface is connected to the logic unit 31, each second interface is connected to the corresponding first JTAG interface 101, and the multitasking unit 30 is based on the test signal and the corresponding The chip 10 establishes a transmission channel for the test signal to detect the chip 10 .

Wherein, the logic unit 31 has a function test application software and a plurality of logic units 31, and the function test application software is stored in the logic unit 31 in the form of firmware in an embedded system (Embedded System) framework, and the function test application software According to the pre-tested chip 10 specified by the switching command, the logic components are controlled to generate test signals.

The control device 4 also includes a Universal Serial Bus interface 42 and a microprocessor 41, the third JTAG interface 40 is connected to the second JTAG interface 2, and the Universal Serial Bus interface 42 is connected to an operating device 43 for a user to pass The USB interface 42 sets switching instructions and receives test results of the chip 10 after testing. The microprocessor 41 connects the third JTAG interface 40 and the USB interface 42 to communicate with the programmable controller 3 .

It is worth noting that another feature of the present invention is that, since the detection specifications of each chip 10 may vary according to different chip manufacturers, using the firmware architecture of the present invention, users can easily and without spending extra money. To construct different test environments at a low cost, it is only necessary to update the functional test application software stored in the programmable controller 3 through the communication between the second JTAG interface 2 and the third JTAG interface 40 .

Please refer to FIG. 3 , which is a flow chart of the multi-chip detection method of the present invention. Detection methods include at least:

Step S31: receiving a switching instruction from a programmable controller to select at least one chip to be tested;

Step S32: sending a test signal to the selected chip under test, and making the chip under test generate a test result; and

Step S33: Return the test result to the programmable controller.

Wherein, before the step S31, a step S30 is also included, and the step S30 is that a control device sends a switching instruction according to a test requirement.

In summary, through the above test system and test method, by connecting a programmable controller to multiple chips with JTAG interfaces, a user can send a switching command through the control device to select the chip to be tested , the programmable controller selects the chip according to the switching instruction, and sends a test signal conforming to the corresponding chip test specification. In this way, the design of the JTAG interface detection points of each chip is reduced to simplify the difficulty and complexity of the test process, thereby improving the efficiency and speed of detection.

Certainly, the present invention also can have other multiple embodiments, without departing from the spirit and essence of the present invention, those skilled in the art can make various corresponding changes and deformations according to the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (9)

1. A multi-chip test system, characterized in that, comprising: A device under test, comprising: A plurality of chips, each of which has a first joint test working group interface; a programmable controller, coupled to the chips through the first JTAG interfaces; and a second joint test working group interface connected to the programmable controller; and A control device with a third joint test working group interface connected to the second joint test working group interface, the control device sends a switching command to the programmable controller, wherein the switching command is passed through the second joint testing working group interface The test working group interface is sent to the programmable controller, and the programmable controller sends at least one test signal to the corresponding at least one chip according to the switching instruction, and the corresponding chip generates a test result and sends it back to the control device . 2. The multi-chip testing system according to claim 1, wherein the programmable controller comprises: a logic unit, connected to the second joint test working group interface, for receiving the switching instruction, and sending the corresponding test signal according to the switching instruction; and A multitasking unit has a first interface and a plurality of second interfaces, the first interface is connected to the logic unit, each of the second interfaces is connected to the corresponding first joint test working group interface, and the multitasking unit is based on A transmission channel is established between the test signal and the corresponding chips for the test signal to detect the chips. 3. The multi-chip test system according to claim 2, wherein the logic unit has a functional test application software and a plurality of logic components, and the functional test application software controls the logic components according to the switch command to generate the test signal. 4. The multi-chip testing system according to claim 1, wherein the control device comprises: an operating device; a universal serial bus interface connected to the operating device, the operating device sets the switching command and receives the test result through the universal serial bus interface; and A microprocessor is connected to the interface of the third joint test working group and the interface of the universal serial bus. 5. A multi-chip testing method is characterized in that, comprising the following steps: receiving a switching instruction from a programmable controller to select at least one chip to be tested; sending a test signal to the selected chip under test, and making the chip under test generate a test result; and Return the test result to the programmable controller. 6. The multi-chip testing method according to claim 5, characterized in that, before the step of receiving the switch command sent by the programmable controller, it also includes: According to a test requirement, a control device is instructed to send the switching instruction. 7. The multi-chip testing method according to claim 5, wherein the switch command is sent to the programmable controller through a joint test working group interface. 8. The multi-chip testing method according to claim 5, wherein the test signal is sent to the chip under test through a joint test working group interface. 9. The multi-chip testing method according to claim 5, wherein the test result is sent back to the programmable controller through a joint test working group interface.