CN102487056A - Dummy metal in integrated circuit and method for manufacturing integrated circuit plate - Google Patents
Dummy metal in integrated circuit and method for manufacturing integrated circuit plate Download PDFInfo
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- CN102487056A CN102487056A CN2010105682564A CN201010568256A CN102487056A CN 102487056 A CN102487056 A CN 102487056A CN 2010105682564 A CN2010105682564 A CN 2010105682564A CN 201010568256 A CN201010568256 A CN 201010568256A CN 102487056 A CN102487056 A CN 102487056A
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- 239000002184 metal Substances 0.000 title claims abstract description 115
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 115
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 title abstract description 6
- 238000005516 engineering process Methods 0.000 claims abstract description 7
- 238000000465 moulding Methods 0.000 claims description 7
- 230000009467 reduction Effects 0.000 abstract description 5
- 150000002739 metals Chemical class 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 30
- 239000004020 conductor Substances 0.000 description 8
- 238000005530 etching Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000000739 chaotic effect Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000005674 electromagnetic induction Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
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Abstract
The invention provides a dummy metal in an integrated circuit. The dummy metal can be applied to each layer of integrated circuit plate; the overall dimension of the dummy metals is a minimum one in the processing technology; and the dummy metal is in a cross shape. Besides, the invention also provides a method for manufacturing an integrated circuit plate containing the dummy metal. The method comprises the following steps that: a dummy metal is moulded in a layer of integrated circuit plate; and in a next layer of integrated circuit plate, a dummy metal is moulded at a position that is staggered with a position of projection at a direction where the dummy metal of the previous integrated circuit plate is perpendicular to the integrated circuit plate. According to the dummy metal in an integrated circuit in the invention, generation of eddy currents can be reduced and a reduction amplitude of a Q value can be reduced; that is, Q value reduction amplitudes of inductance devices provided with integrated circuits obtained by carrying out processing on the dummy metals provided in the invention can be reduced, wherein the inductance devices include an RFIC, a voltage controloscillator (VCO), and a low noise amplifier (LNA) and the like; and magnetic losses can also be reduced.
Description
Technical field
The present invention relates to technical field of integrated circuits, be specifically related to the dummy metal (Dummy Metal) in a kind of integrated circuit, and a kind of manufacturing approach that contains this surface-mounted integrated circuit of dummy metal.
Background technology
In the processing technology of integrated circuit, dummy metal (Dummy Metal) is to be added in the wafer for the requirement of wafer processing.The effect of dummy metal is exactly in order to satisfy minimum density metal requirement.Angle from wafer processing if density metal is widely different on the mould, when cmp (CMP), oxide (silicon dioxide) groove can occur in the high zone of density metal, and it is that oxide and metal are ground sunk result together.So need will add the dummy metal that some and circuitous pattern have nothing to do in the low place of density metal, this oxide groove to prevent that the high zone of density metal from occurring reduces the deviation in the pilot process.In addition, in processing step (process) lining of etching (etch), (etch rate) is different for the etch rate in the zone that zone that density metal is high and density metal are low.So need be through adding dummy metal, it is excessive to occur etching deficiency or etching when preventing etching, improves etching effect.Integrated circuit comprises the circuitous pattern of multilayer, realizes and the processing of every layer of circuitous pattern all need add dummy metal.The shape in the individual layer circuit of existing dummy metal is respectively square and octagon like Fig. 1, shown in 2.
The making of integrated circuit is made up of multilayer circuit board, like Fig. 4, shown in 5.Dummy metal is respectively arranged with the dummy metal of some on the circuit board of multilayer.Wherein the arranged evenly mode of the dummy metal among Fig. 4 301 among the circuit board of different layers is to be arranged in parallel; Be that dummy metal 301 between the different layers is taking place overlappedly completely perpendicular to the projection meeting on each layer circuit board direction, i.e. projection is the same with the arranged distribution of the dummy metal of individual layer; The arranged evenly mode of dummy metal 302 among Fig. 5 among the circuit board of different layers is that entanglement is arranged; Be between the different layers dummy metal 302 take place perpendicular to the projection on each layer circuit board direction overlapped, overlap; And the multiple situation that staggers each other, distributing relatively, confusion does not have certain rules to say.
The Q value is to weigh the major parameter of inductance component, is meant when inductor is worked under the alternating voltage of a certain frequency the ratio of the induction reactance that is appeared loss resistance equivalent with it.The Q value of inductor is high more, and its loss is more little, and efficient is high more.At RF IC (RFIC), voltage controlled oscillator (VCO; Voltage controloscillator) and low noise amplifier (LNA; Low noise amplifier) in the integrated circuit of the device processing such as; Owing to can produce eddy current in the dummy metal, when in integrated circuit, introducing dummy metal, can bring Q value to reduce above 15%.And the magnetic loss that reduces will to increase the above-mentioned type device of above-mentioned Q value.
Summary of the invention
In view of this, main purpose of the present invention is the technical problem that the introducing to dummy metal of the prior art will bring Q value to reduce significantly, and the dummy metal a kind of Q of minimizing value reduction amplitude and then minimizing magnetic loss, in the integrated circuit is provided.
And, a kind of manufacturing approach that contains the surface-mounted integrated circuit of dummy metal is proposed.
For achieving the above object, technical scheme provided by the invention is following:
Dummy metal in a kind of integrated circuit is applied in each layer surface-mounted integrated circuit, and its geomery is the processing technology smallest dimension, and said dummy metal is " ten " font.
Preferably, said dummy metal mode arranged evenly between the different layers surface-mounted integrated circuit is that the said dummy metal of adjacent two layers is staggering perpendicular to the projection on the surface-mounted integrated circuit direction each other.
A kind of manufacturing approach that contains the surface-mounted integrated circuit of above-mentioned dummy metal may further comprise the steps:
The said dummy metal of moulding in one deck surface-mounted integrated circuit;
In one deck surface-mounted integrated circuit next, at the position of staggering each other perpendicular to the projection on the surface-mounted integrated circuit direction with the said dummy metal of preceding one deck, the said dummy metal of moulding.
Dummy metal in the integrated circuit of the present invention, it has following beneficial effect:
Dummy metal in the integrated circuit of the present invention; It is " ten " word shape; Compare with the square and octagon of prior art, it can avoid producing a large amount of eddy current, so can reduce the consumption of eddy current to energy; And then can make by be provided with integrated circuit that dummy metal of the present invention processing obtains for example the Q value of inductance components such as RF IC, voltage controlled oscillator and low noise amplifier reduce amplitude and decrease, promptly reduce magnetic loss.
Dummy metal in the integrated circuit of the present invention; Arranged evenly between the different layers surface-mounted integrated circuit; The projection on the direction between perpendicular to surface-mounted integrated circuit of the said dummy metal of adjacent two layers is staggered each other, and experimental data shows, this mode arranged evenly between different layers of dummy metal; Can reduce the amplitude that the Q value of inductance component reduces, promptly reduce magnetic loss.
Description of drawings
Fig. 1 and Fig. 2 are respectively the plan structure sketch mapes of the dummy metal in the integrated circuit in the prior art;
Fig. 3 is the plan structure sketch map of a kind of embodiment of the dummy metal in the integrated circuit of the present invention;
Fig. 4 and Fig. 5 be respectively in the prior art dummy metal in the integrated circuit at the structural representation arranged evenly of each interlayer;
Fig. 6 is dummy metal in the integrated circuit of the present invention a kind of embodiment surface-mounted integrated circuit vertical section structure sketch map arranged evenly between the different layers surface-mounted integrated circuit.
Reference numeral is expressed as among the figure: 301,302, and the 401-dummy metal.
Embodiment
Eddy current (eddy current) coils a conductor outside, and lets coil feed alternating current, and coil just produces alternating magnetic field so.Because the conductor in the middle of the coil is the closed circuit that can equivalence becomes a circle circle at circumferencial direction; Magnetic flux in the closed circuit is constantly changing; So the circumferencial direction at conductor can produce induced electromotive force and induced current; Sense of current is turn-taked along the circumferencial direction of conductor, just as the whirlpool of a circle circle, so thisly electromagnetic induction takes place and produce faradic phenomenon and be called vortex phenomenon in that the monoblock conductor is inner.The outer perimeter of conductor is long more, and the frequency of alternating magnetic field is high more, and eddy current is just big more.The inner eddy current of conductor also can produce heat, if the resistivity of conductor is little, then eddy current is very strong, and the heat of generation is just very big.
The present invention provides dummy metal and the arranged evenly mode of this dummy metal between different layers in a kind of integrated circuit through generation that reduces eddy current and then the effect that plays minimizing inductance component magnetic loss.
For make the object of the invention, technical scheme, and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.
Embodiment 1
As shown in Figure 3, the dummy metal in a kind of integrated circuit is applied in each layer surface-mounted integrated circuit; Its geomery is the processing technology smallest dimension; Be 45 nanometers like current minimum process yardstick promptly, then the minimum length of side of this dummy metal is 45 nanometers, and the technology of integrated circuit is improved like future; Can carry out more precise and tiny processing, then the yardstick of the above-mentioned minimum length of side also can reduce thereupon.
Said dummy metal is " ten " font.Owing to can produce eddy current in the dummy metal, when in integrated circuit, introducing dummy metal, can bring the Q value to reduce." ten " font dummy metal among Fig. 3 and square dummy metal among Fig. 1 and the octagon dummy metal among Fig. 2, under the situation of identical dummy metal distribution density, the corresponding relation such as the following table of frequency and Q value:
6.00E+08 in the last table is meant 6.00*10
8, the expression mode of its remainder values is similar with it.
Data through last table are visible, and " ten " of the present invention font dummy metal is compared with the dummy metal of two kinds of shapes of prior art, with first group of data instance: under 6.00E+08Hz; The Q value of " ten " of the present invention font dummy metal is 3.83E+00; And the Q value of square dummy metal of the prior art is 3.64E+00, and the Q value of octagon dummy metal of the prior art is 3.47E+00, wherein; The Q value of " ten " of the present invention font dummy metal is the highest; That is to say that the Q value that is introduced in the surface-mounted integrated circuit to be brought reduces minimum, thereby dummy metal of the present invention can effectively reduce the Q value reduction amplitude of inductance component.
And then because the making of integrated circuit is made up of multilayer circuit board, like Fig. 4,5 and shown in Figure 6, dummy metal is respectively arranged with the dummy metal of some on the circuit board of multilayer.Wherein the arranged evenly mode of the dummy metal among Fig. 4 301 among the circuit board of different layers is to be arranged in parallel; Be that dummy metal 301 between the different layers is taking place overlappedly completely perpendicular to the projection meeting on each layer circuit board direction, i.e. projection is the same with the arranged distribution of the dummy metal of individual layer; The arranged evenly mode of dummy metal 302 among Fig. 5 among the surface-mounted integrated circuit of different layers is that entanglement is arranged; Be between the different layers dummy metal 302 take place perpendicular to the projection meeting on each layer surface-mounted integrated circuit direction overlapped completely; Overlap; And situation about staggering each other, the distribution of dummy metal is chaotic.
As shown in Figure 6; Dummy metal 401 in the integrated circuit is arranged evenly between the different layers surface-mounted integrated circuit; The projection on the direction between perpendicular to surface-mounted integrated circuit of the said dummy metal 401 of adjacent two layers is staggered each other, and the arrangement mode of this dummy metal is staggered pattern (Cross Over mode).
Under the situation of same dummy metal distribution density; Dummy metal among Fig. 6 is staggered mode arranged evenly and the dummy metal contrast arranged evenly of the entanglement arrangement mode in the parallel arrangement mode among Fig. 4 and 5 between different layers, the corresponding relation such as the following table of its frequency and Q value:
1.15E+09 in the last table is meant 1.15*10
9, the expression mode of its remainder values is similar with it.
Data through last table are visible; With first group of data instance: under 1.15E+09Hz; The Q value of the dummy metal of staggered pattern of the present invention is 6.88E+00, and the Q value of the dummy metal of parallel arrangement mode of the prior art is 6.27E+00, and the Q value of the dummy metal of entanglement arrangement mode of the prior art is 5.98E+00; Wherein, the Q value of the dummy metal of staggered pattern of the present invention is the highest.That is to say; Under the situation of same dummy metal distribution density; The dummy metal of staggered pattern of the present invention is incorporated in the surface-mounted integrated circuit; Q value that it brought reduces minimum, and the distribution thereby dummy metal of the present invention is staggered between different layers can effectively reduce the Q value reduction amplitude of inductance component.
The manufacturing approach that contains dummy metal shown in Figure 6 401 surface-mounted integrated circuits is: at first, and the said dummy metal 401 of moulding in one deck surface-mounted integrated circuit; Then, in one deck surface-mounted integrated circuit next, at the position of staggering each other perpendicular to the projection on the surface-mounted integrated circuit direction with the said dummy metal 401 of preceding one deck, the said dummy metal 401 of moulding.By that analogy, the whole dummy metal 401 in the intact multilevel integration plate of moulding.So just obtained the vertical section of different layers surface-mounted integrated circuit shown in Figure 6, presented the dummy metal 401 of staggered pattern.
The above is merely preferred embodiment of the present invention, and is in order to restriction the present invention, not all within spirit of the present invention and principle, any modification of being made, is equal to replacement, improvement etc., all should be included within the scope that the present invention protects.
Claims (3)
1. the dummy metal in the integrated circuit is applied in each layer surface-mounted integrated circuit, and its geomery is the processing technology smallest dimension, it is characterized in that, said dummy metal is " ten " font.
2. dummy metal according to claim 1 is characterized in that, said dummy metal mode arranged evenly between the different layers surface-mounted integrated circuit is that the said dummy metal of adjacent two layers is staggering perpendicular to the projection on the surface-mounted integrated circuit direction each other.
3. a manufacturing approach that contains the surface-mounted integrated circuit of the described dummy metal of claim 1 is characterized in that, may further comprise the steps:
The said dummy metal of moulding in one deck surface-mounted integrated circuit;
In one deck surface-mounted integrated circuit next, at the position of staggering each other perpendicular to the projection on the surface-mounted integrated circuit direction with the said dummy metal of preceding one deck, the said dummy metal of moulding.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105682564A CN102487056A (en) | 2010-12-01 | 2010-12-01 | Dummy metal in integrated circuit and method for manufacturing integrated circuit plate |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010105682564A CN102487056A (en) | 2010-12-01 | 2010-12-01 | Dummy metal in integrated circuit and method for manufacturing integrated circuit plate |
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| CN102487056A true CN102487056A (en) | 2012-06-06 |
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| CN2010105682564A Pending CN102487056A (en) | 2010-12-01 | 2010-12-01 | Dummy metal in integrated circuit and method for manufacturing integrated circuit plate |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020199036A1 (en) * | 2019-03-29 | 2020-10-08 | 华为技术有限公司 | Inductive wiring architecture, integrated circuit, and communication device |
| WO2022241999A1 (en) * | 2021-05-19 | 2022-11-24 | 长鑫存储技术有限公司 | Semiconductor structure |
| US12261109B2 (en) | 2021-05-19 | 2025-03-25 | Changxin Memory Technologies, Inc. | Semiconductor structure |
| US12341094B2 (en) | 2021-05-19 | 2025-06-24 | Changxin Memory Technologies, Inc. | Semiconductor structure |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0661230A (en) * | 1992-05-28 | 1994-03-04 | Nec Corp | Semiconductor integrated circuit device |
| US20020190382A1 (en) * | 2001-06-15 | 2002-12-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having dummy patterns for metal cmp |
| KR20050104959A (en) * | 2004-04-30 | 2005-11-03 | 매그나칩 반도체 유한회사 | Method for chemical mechanical polishing using cross-shaped dummy pattern |
| CN101459178A (en) * | 2007-12-14 | 2009-06-17 | 恩益禧电子股份有限公司 | Semiconductor device |
-
2010
- 2010-12-01 CN CN2010105682564A patent/CN102487056A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0661230A (en) * | 1992-05-28 | 1994-03-04 | Nec Corp | Semiconductor integrated circuit device |
| US20020190382A1 (en) * | 2001-06-15 | 2002-12-19 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device having dummy patterns for metal cmp |
| KR20050104959A (en) * | 2004-04-30 | 2005-11-03 | 매그나칩 반도체 유한회사 | Method for chemical mechanical polishing using cross-shaped dummy pattern |
| CN101459178A (en) * | 2007-12-14 | 2009-06-17 | 恩益禧电子股份有限公司 | Semiconductor device |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2020199036A1 (en) * | 2019-03-29 | 2020-10-08 | 华为技术有限公司 | Inductive wiring architecture, integrated circuit, and communication device |
| CN113614915A (en) * | 2019-03-29 | 2021-11-05 | 华为技术有限公司 | Inductance device wiring architecture, integrated circuit and communication equipment |
| US12354954B2 (en) | 2019-03-29 | 2025-07-08 | Huawei Technologies Co., Ltd. | Inductor device wiring architecture, integrated circuit, and communications device |
| WO2022241999A1 (en) * | 2021-05-19 | 2022-11-24 | 长鑫存储技术有限公司 | Semiconductor structure |
| US12261109B2 (en) | 2021-05-19 | 2025-03-25 | Changxin Memory Technologies, Inc. | Semiconductor structure |
| US12341094B2 (en) | 2021-05-19 | 2025-06-24 | Changxin Memory Technologies, Inc. | Semiconductor structure |
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| ASS | Succession or assignment of patent right |
Owner name: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING Effective date: 20121119 |
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Effective date of registration: 20121119 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant after: Semiconductor Manufacturing International (Shanghai) Corporation Applicant after: Semiconductor Manufacturing International (Beijing) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Applicant before: Semiconductor Manufacturing International (Shanghai) Corporation |
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Application publication date: 20120606 |