CN102508262B - Double-channel radiofrequency receiver capable of realizing multiplex analog-to-digital conversion output and data processing method of double-channel radiofrequency receiver - Google Patents
Double-channel radiofrequency receiver capable of realizing multiplex analog-to-digital conversion output and data processing method of double-channel radiofrequency receiver Download PDFInfo
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Abstract
The invention relates to a double-channel radiofrequency receiver capable of realizing complex analog-to-digital conversion output and a data processing method of the double-channel radiofrequency receiver. Double channels receive two GNSS (global navigation satellite system) radiofrequency signals to realize precise positioning, after analog-to-digital conversion processing is respectively carried out by the aid of identical sampling clocks in the two channels, analog-to-digital conversion data of the double channels are in multiplex conversion processing by a shared multiplex switching module, multiplex polar and amplitude signals are outputted by a group of IO (input and output) output pins which are completely consistent with a single-channel navigation radiofrequency receiver, packaging cost of a chip is saved, and the double-channel radiofrequency receiver is compatible with the single-channel receiver. The multiplex switching module further outputs a sampling output clock used for restoring data of the two channels from multiplex outputted data in a follow-up procedure.
Description
Technical field
The present invention relates to a kind of radio frequency chip of field of wireless communication, particularly a kind of binary channels radio-frequency transmitter and data processing method thereof of multiplexing analog to digital conversion output.
Background technology
The worldwide navigation Positioning System (GPS) has been widely used in vehicle mounted guidance, vehicle tracking, time synchronized, measurement mapping, ship or vehicle monitoring, geodata collection, space industry or the like.Up to the present, navigation positioning system maximum and maximum users are vehicle-mounted and hand-held navigation.At hand-held navigating instrument (PND, Portable Navigation Device) or similarly in using, because whole navigating instrument is by powered battery, so at this application, the chip power-consumption of navigational system has special meaning: power consumption is low more, and the time of use is just long more.On market, as the SiRF company of the U.S., all there has been very ripe navigation radio frequency chip in the MAXIM company of the Canadian SiGe company and the U.S. at present, and its product is most to be designed and make with SiGe technology, to reach low-power consumption, high performance purpose.
As shown in Figure 1, these products all are to adopt in the system architecture of traditional Low Medium Frequency navigation radio-frequency transmitter, 1575.42MHz navigation GPS rf modulated signal, be received by the antenna (not shown) in the signalling channel of radio frequency, by the low noise amplifier 10(LNA of front end) amplify.In order to filter out contiguous mobile phone or other communication undesired signal, the radio frequency rf signal through amplifying need output to outside the chip, by the outer acoustic filter 20(SAW FILTER of sheet) carry out Filtering Processing; Take back the radio frequency prime amplifier 30(RFA in the sheet again) do further to amplify after, output to quadrature down converter 40 and 50(MixerI, MixerQ) carry out the frequency down-converts of radio frequency to medium-frequency IF.For convenience of explanation, we are with cell frequency f
0=1.023MHz calculates radio frequency (1540f
0) and IF-FRE.In the navigation radio frequency chip, the IF-FRE of main flow is 4f
0Intermediate-frequency filter 60(IF Filter) intermediate-freuqncy signal is carried out channel and select, filter out the intermediate-freuqncy signal that needs by demodulation in bandwidth, outer any signal or the noise of bandwidth can be filtered fully.The bandwidth of navigation GPS is 2f
0, the bandwidth ratio 2f of general intermediate-frequency filter
0High slightly.This intermediate-freuqncy signal is through variable gain amplifier 70(VGA) amplify after, the signal intensity that appropriateness is provided is to analog to digital converter 80(ADC), thereby analog intermediate frequency signal is converted to the two digits signal that comprises polarity S IGN and amplitude MAG, and these digital signals are output to the digital baseband (not shown) and do follow-up signal Processing at last.In Low Medium Frequency navigation radio-frequency transmitter system architecture, because radio frequency chip needs independently to become a single-chip, so the amplitude MAG signal of analog to digital converter 80 output is also by variable gain amplifier control circuit 90(VGA Controller) feed back to variable gain amplifier 70, as the detection of its signal intensity, so that this variable gain amplifier 70 can provide constant signal output for analog to digital converter 80.
Wherein, carry out the quadrature down converter 40 and 50 of radio frequency to the medium-frequency IF down coversion, its local oscillator is provided by frequency synthesizer.No matter be integral frequency divisioil frequency synthesizer (Integer-N RFPLL) or fractional frequency division frequency synthesizer (Fractional-N RFPLL), frequency synthesizer phaselocked loop (RFPLL) generally comprises by phase frequency detector 120(PFD), charge pump 130(CP), loop filter 140(LPF), voltage controlled oscillator 150(VCO), the backfeed loop that is connected to form of a set of division module.Wherein, phase frequency detector 120, (the navigation radio frequency chip is generally used 16f with feedback signal and canonical reference clock
0) compare; By the control of this comparative result, 130 pairs of loop filters of described charge pump 140 carry out charge or discharge, make the DC voltage after loop filter 140 output filterings, and the frequency of voltage controlled oscillator 150 is controlled.The local oscillation signal that voltage controlled oscillator 150 produces is via two-divider 160(DIV2), pre-divider 170(Prescaler), feedback divider 180(Feedback Divider) frequency division handle after, feedback outputs to phase frequency detector 120; When the standard frequency of frequency of feeding back and reference equates, phase frequency detector 120 these frequency synthesizer pll locks of control, the local frequency that this moment, voltage controlled oscillator 150 was exported are exactly N times (multiple N cooperates decision by described some frequency division modules 160,170,180) of reference clock.Because the system architecture of navigation radio frequency chip main flow is all selected the pressuring controlling oscillator frequency of two frequencys multiplication, i.e. 2 * 1536f
0, so the output of voltage controlled oscillator 150 exports described quadrature down converter 40 and 50 respectively to via two-divider 160 frequency divisions acquisition orthogonal local oscillation LOI and LOQ.
In general, in order to satisfy the high-precision requirement of navigation radio frequency chip to frequency, crystal oscillator (TCXO by the outer temperature compensation of sheet, do not draw) clock signal (TCXO_IN) that provides, process clock isolation amplifier 100(CLK BUF) after the shaping, is input into frequency synthesizer phaselocked loop (RFPLL) as the canonical reference clock.Meanwhile, this clock of clock isolation amplifier 100 outputs also offers analog to digital converter 80 as its sampling clock.This sampling clock finally also passes through another one clock isolation amplifier 110(CLK BUF) shaping, output to the outer navigation baseband chip of sheet do the data sampling synchronously.
Four Global Navigation System Global Navigation Satellite System(GNSS are arranged at present in the world): the firstth, the GPS of USA navigational system, its rf frequency is 1575.42MHz, bandwidth is 2.046MHz, is containing the C/A sign indicating number of time and positional information in the bandwidth.The secondth, the GLONASS navigational system of Russia, its rf frequency is 1598.0625MHz to 1605.375MHz, bandwidth is 8MHz, is divided into 14 channels; Channel and channel be 0.5625MHz at interval, the bandwidth of each channel is 0.5625MHz; The 3rd is the Chinese Big Dipper COMPASS navigational system in two generations, and its rf frequency is 1561.098MHz, and bandwidth is 4.092MHz.The 4th is Galileo (Galileo) navigational system of European Union, and its rf frequency is 1575.42MHz, and bandwidth is 4.092MHz.
At present most widely used general, the navigational system of main flow is exactly the GPS of USA navigational system.By in February, 2011, there have been 22 GLONASS of the Russia Navsats that can run the sky.The COMPASS navigational system in two generations of the Big Dipper of China is more and more ripe, and there have been 9 Navsats the sky at present.The Big Dipper two generations expectation can cover the Asian-Pacific area and enter substantive operation in 2012.The Galileo of European Union (Galileo) navigational system speed of development is the most slowly.
Yet, no matter be government of Russia now, Chinese Government or European Union, it is unpractical that requirement and encourage consumer only use the navigational system of oneself.The first, number of satellite is insufficient, and the Glonass Navsat that just is Russia also is less than 24; The second, the ripe operation of Global Navigation System separately (GNSS) also needs more time.Referring to table 1, therefore, if a twin-channel navigation radio-frequency transmitter is arranged on market, can receive simultaneously the Glonass Navsat of GPS of America Navsat and Russia, or the while can receive the Big Dipper Compass Navsat of GPS of America Navsat and China, or can receive simultaneously Galileo (Galileo) Navsat of GPS of America Navsat and European Union, its comprehensive location will be more accurate, will have very high using value.
Table 1 is twin-channel may practical combination
As shown in Figure 2, in general, twin-channel GNSS radio-frequency transmitter is provided with two independently next corresponding two-way GNSS radiofrequency signals that receive of signalling channel, the radio-frequency (RF) front-end circuit during down-converted that these two signalling channels are shared up to the first time, for the first time down coversion frequency synthesizer phaselocked loop of local frequency is provided, and reference clock is provided and corresponds to the correlation module that analog-to-digital conversion process provides sampling clock to the frequency synthesizer phaselocked loop.
Will be in the first passage through the intermediate-freuqncy signal of the down-converted first time, after converting the first intermediate frequency switching signal CH1_IF corresponding to first via radiofrequency signal, be sent to variable gain amplifier 71 and amplify, outwards export the two digits signal that comprises polarity S IGN1, amplitude MAG1 by analog to digital converter 81 again; Variable gain amplifier control circuit 91 feeds back to the detection that variable gain amplifier 71 is used for signal intensity with amplitude MAG1 signal.
Will be in the second channel through for the first time, the intermediate-freuqncy signal of down-converted for the second time, after converting the second intermediate frequency switching signal CH2_IF corresponding to the second tunnel radiofrequency signal, handle by the variable gain amplifier 72, the analog to digital converter 82 that are provided with in addition in the second channel, obtain the digital signal of polarity S IGN2 and amplitude MAG2; Variable gain amplifier control circuit 92 feeds back to variable gain amplifier 72 with amplitude MAG2 signal.
Though the binary channels GNSS receiver of this framework, can independent processing two-way radiofrequency signal, but, follow-up digital signal through analog to digital conversion output also can be two covers independently, comprise polar signal SIGN1 and SIGN2, range signal MAG1 and MAG2, and handle after two sampling clock CLK_OUT1 and CLK_OUT2 that clock isolation amplifier 101,102 is exported respectively by shared sampling clock module 11.Compare single pass framework, this binary channels GNSS radio-frequency transmitter can take the IO output pin of twice, needs bigger cost of manufacture, and also is difficult to compatibility with the single channel radio-frequency transmitter.
Summary of the invention
The binary channels radio-frequency transmitter and the data processing method thereof that the purpose of this invention is to provide a kind of multiplexing analog to digital conversion output, this receiver can receive two-way GNSS radio frequency navigation signal simultaneously, after in signalling channel separately, carrying out data processing, export polarity, the range signal that analog to digital conversion obtains in these two passages by same set of IO pin, and analog-to-digital sample frequency, thereby it is the saving packaging cost, and compatible mutually with the output pin of single channel radio-frequency transmitter.
Technical scheme of the present invention provides a kind of binary channels radio-frequency transmitter and data processing method thereof of multiplexing analog to digital conversion output.
The binary channels radio-frequency transmitter of described multiplexing analog to digital conversion output, be provided with first, second passage and come corresponding two-way radiofrequency signal RF1, the RF2 of receiving, radiofrequency signal is converted to separately after first, second intermediate frequency switching signal CH1_IF, the CH2_IF of correspondence, the subsequent conditioning circuit in described two passages sends respectively;
In first, second passage, be provided with variable gain amplifier and analog to digital converter separately, in these two passages, respectively first, second intermediate frequency switching signal CH1_IF, CH2_IF after amplifying are carried out analog to digital conversion, obtain the polar signal SIGN1 and the range signal MAG1 of first passage, and the polar signal SIGN2 of second channel and range signal MAG2; Also be provided with the variable gain amplifier control circuit in first, second passage separately, range signal MAG1, MAG2 wherein fed back to the variable gain amplifier of correspondence;
Described two passages are also shared multiplexing handover module, come the analog-digital conversion data of first, second passage is carried out multiplexing process, obtain changing the polarity composite signal SIGN that forms, and change the amplitude composite signal MAG that forms by described two range signal MAG1, MAG2 by described two polar signal SIGN1, SIGN2;
When described two analog to digital converters carry out analog to digital conversion, use identical sampling clock CLK; Described multiplexing handover module also receives described sampling clock CLK, and is translated into the sampling output clock CLK_OUT that is used for data sync;
Described multiplexing handover module is provided with some IO output pins, comprises respectively that the digital baseband outside sheet sends described polarity composite signal SIGN, described amplitude composite signal MAG, and one group of port of described sampling output clock CLK_OUT.
Radio-frequency (RF) front-end circuit that described two passages are shared is carried out the down-converted first time to described two-way radiofrequency signal RF1, the RF2 that receives; Required local frequency LOI, the LOQ of down coversion provided by two shared frequency synthesizer phaselocked loops of passage for the first time;
In the described radio-frequency (RF) front-end circuit, comprise the outer acoustic filter of low noise amplifier, sheet, radio frequency prime amplifier and the quadrature down converter that connect successively;
In the described frequency synthesizer phaselocked loop, comprise the backfeed loop that connects and composes by phase frequency detector, charge pump, loop filter, voltage controlled oscillator, two-divider, pre-divider and feedback divider.
In described first passage, also be included in the intermediate-frequency filter that is provided with after the described quadrature down converter, it carries out Filtering Processing to down coversion first time intermediate-freuqncy signal afterwards, obtains the corresponding first intermediate frequency switching signal CH1_IF with first via radiofrequency signal RF1;
In described second channel, also be included in the double down converter and the intermediate-frequency filter that are provided with after the described quadrature down converter, to the intermediate-freuqncy signal after the first time down coversion carry out the second time down coversion and Filtering Processing after, obtain the second intermediate frequency switching signal CH2_IF corresponding with the second tunnel radiofrequency signal RF2.
Described two passages are also shared connect successively with lower module:
A clock isolation amplifier after its clock signal to the outside input is carried out shaping, is sent to described frequency synthesizer phaselocked loop with the reference clock Ref CLK that obtains;
A sampling clock module, it is according to the described reference clock Ref CLK that receives, and local frequency LOI, LOQ that described frequency synthesizer phaselocked loop is sent carry out the frequency division processing, obtain sample frequency;
A clock isolation amplifier, its with the sample frequency shaping after, send identical sampling clock CLK to described two analog to digital converters and described multiplexing handover module.
Sampling clock CLK with input in described multiplexing handover module obtains delayed clock CLK_SEL after carrying out certain time-delay, setting and retention time when carry out multiplexing output and handle as described multiplexing handover module this time delay;
The multiplexing output information OUTPUT of described multiplexing handover module output comprises the analog-digital conversion data of first passage and second channel simultaneously;
And when described delayed clock CLK_SEL was high level, described multiplexing output information OUTPUT was the analog-digital conversion data of a passage in first passage or the second channel; When described delayed clock CLK_SEL was low level, described multiplexing output information OUTPUT was the analog-digital conversion data of another passage wherein.
The sampling output clock CLK_OUT of described multiplexing handover module output carries out obtaining after the certain time-delay to delayed clock CLK_SEL;
When sampling output clock CLK_OUT rising edge triggered, the sheet external circuit restored the analog-digital conversion data of a passage in first passage or the second channel from described multiplexing output information OUTPUT; When sampling output clock CLK_OUT negative edge triggers, restore the wherein analog-digital conversion data of another passage.
Described delayed clock CLK_SEL forms 1/4 all after date of sampling clock CLK time-delay; When delayed clock CLK_SEL was high level, described multiplexing output information OUTPUT was the analog-digital conversion data of first passage; When delayed clock CLK_SEL was low level, described multiplexing output information OUTPUT was the analog-digital conversion data of second channel;
Described sampling output clock CLK_OUT formed described 1/4 cycle of delayed clock CLK_SEL time-delay, and described sampling output clock CLK_OUT is described sampling clock CLK through 1 grade of clock after oppositely;
When described sampling output clock CLK_OUT rising edge triggered, from described multiplexing output information OUTPUT, reduction obtained the data after the analog-digital conversion data time-delay half period of first passage; When sampling output clock CLK_OUT is a negative edge when triggering, reduction obtains the data after the analog-digital conversion data time-delay half period of second channel.
In the data processing method to multiplexing analog to digital conversion output in the described binary channels radio-frequency transmitter, at first in described binary channels radio-frequency transmitter, be provided with first, second passage and come corresponding two-way radiofrequency signal RF1, the RF2 of receiving; In first passage, carry out the first time down coversion and Filtering Processing after, obtain the corresponding first intermediate frequency switching signal CH1_IF with first via radiofrequency signal RF1; In second channel, carry out for the first time, for the second time after down coversion and the Filtering Processing, obtain the second intermediate frequency switching signal CH2_IF corresponding with the second tunnel radiofrequency signal RF2; Afterwards, in first, second passage, carry out analog-to-digital conversion process separately to described first, second intermediate frequency switching signal CH1_IF, CH2_IF;
Also be provided with a multiplexing handover module in the described binary channels radio-frequency transmitter, it is shared by first, second passage; Described multiplexing handover module carries out multiplexing process after by the outside method that sends of same group of IO output pin, specifically comprise following steps with the analog-digital conversion data of first, second passage:
In first passage, when sampling clock CLK is high level, export polar signal SIGN1 and the range signal MAG1 of the corresponding first intermediate frequency switching signal CH1_IF, as the analog-digital conversion data of this passage; When sampling clock CLK is low level, carries out data and keep;
In second channel, when sampling clock CLK is low level, export polar signal SIGN2 and the range signal MAG2 of the corresponding second intermediate frequency switching signal CH2_IF, as the analog-digital conversion data of this passage; When sampling clock CLK is high level, carries out data and keep;
In the time of the described multiplexing output information OUTPUT of step 3, output, obtain a sampling output clock CLK_OUT after also delayed clock CLK_SEL being postponed for second time by multiplexing handover module; According to this sampling output clock CLK_OUT, by the sheet external circuit described multiplexing output information OUTPUT is reduced processings, the data of analog-digital conversion data after the very first time of having delayed time added for second time of the data that obtain and described two passages of reducing are corresponding.
In the preferred embodiment, the CLK_SEL of delayed clock described in the step 2 obtained sampling clock CLK a+1/4 cycle of delay, and wherein a is the integer more than or equal to 0;
When delayed clock CLK_SEL is high level, described multiplexing output information OUTPUT be first passage analog-digital conversion data; When delayed clock CLK_SEL was low level, described multiplexing output information OUTPUT was the analog-digital conversion data of second channel.
In the preferred embodiment, the output of sampling described in the step 3 clock CLK_OUT postpones b+1/4 cycle formation to delayed clock CLK_SEL, and wherein b is the integer more than or equal to 0; And described sampling output clock CLK_OUT is the clock after described sampling clock CLK process oppositely reaches corresponding delay;
When described sampling output clock CLK_OUT rising edge triggered, what restore was the analog-digital conversion data of first passage after the corresponding delay; And when sampling output clock CLK_OUT was the negative edge triggering, what restore was the analog-digital conversion data of second channel after the corresponding delay.
Compared with prior art, the binary channels radio-frequency transmitter and the data processing method thereof of multiplexing analog to digital conversion output of the present invention, its advantage is:
Parameters such as the bandwidth that the present invention selects by reference clock, local frequency, sampling clock, the channel of controlling first passage and second channel respectively, intermediate-freuqncy signal, make first passage carry out the down coversion first time, second channel carries out for the first time, for the second time after the down-converted, can correspondingly receive two-way GNSS radio frequency navigation signal, thereby improve the accuracy of navigator fix.Simultaneously, owing to shared RF front-end module and frequency synthesizer phaselocked loop etc., this binary channels navigation radio-frequency transmitter system architecture can be saved power consumption, reduces cost, and has good application value.
After using identical sampling clock to carry out analog-to-digital conversion process separately in two passages of the present invention, by shared multiplexing handover module the double-channel analog/digital translation data is carried out multiplexing conversion process, and with multiplexing polar signal, range signal, and the sampling output clock that is used for data sync, by outwards exporting with the on all four one group of IO output pin of single channel navigation radio-frequency transmitter, saved the Chip Packaging cost, can also with the single-channel receiver compatibility.
The present invention is based on first, second passage to analog-to-digital output timing requirement, 1/4 cycle formed delayed clock CLK_SEL by delaying time, according to the difference of this delayed clock CLK_SEL high-low level, the multiplexing output information OUTPUT that multiplexing handover module is exported corresponds to the analog-digital conversion data of first passage or second channel.Form sampling output clock CLK_OUT by 1/4 cycle of time-delay again,, from multiplexing output information OUTPUT, restore the analog-digital conversion data of these two passages by the sheet external circuit according to this sampling output clock CLK_OUT.Data processing method of the present invention is easy to realize the reliability height.
Description of drawings
Fig. 1 is the synoptic diagram of existing a kind of single pass navigation radio-frequency transmitter chip architecture;
Fig. 2 is the synoptic diagram of existing a kind of twin-channel navigation radio-frequency transmitter chip architecture;
Fig. 3 is the chip architecture synoptic diagram of the binary channels navigation radio-frequency transmitter of multiplexing analog to digital conversion output of the present invention;
Fig. 4 is the sequential synoptic diagram of navigation radio-frequency transmitter of the present invention multiplexing analog-digital conversion data in GPS and the twin-channel embodiment of GLN;
Fig. 5 is the signal Processing synoptic diagram of navigation radio-frequency transmitter of the present invention handover module in GPS and the twin-channel embodiment of GLN;
Fig. 6 be navigation radio-frequency transmitter of the present invention in GPS and the twin-channel embodiment of GLN from the output signal of handover module the reduction double-channel signal synoptic diagram.
Embodiment
Below in conjunction with description of drawings the specific embodiment of the present invention.
As shown in Figure 3, the binary channels navigation radio-frequency transmitter of multiplexing analog to digital conversion output of the present invention is provided with first, second passage and comes the corresponding two-way GNSS radiofrequency signal that receives.Described two-way GNSS radiofrequency signal can be the combination of any one double-channel signal in the table 1.
At first, receive the GNSS rf modulated signal, and finish the down-converted first time this signal by the shared radio-frequency (RF) front-end circuit of first, second passage; Carry out required local frequency LOI, the LOQ of down coversion for the first time, a frequency synthesizer phaselocked loop (RFPLL) shared by first, second passage provides.In the described radio-frequency (RF) front-end circuit, comprise successively the low noise amplifier 1(LNA that connects), the outer acoustic filter 2(SAW FILTER of sheet), radio frequency prime amplifier 3(RFA) and quadrature down converter 4 and 5(MixerI, MixerQ).In the described frequency synthesizer phaselocked loop, comprise by phase frequency detector 12(PFD), charge pump 13(CP), loop filter 14(LPF), voltage controlled oscillator 15(VCO), two-divider 16(DIV2), pre-divider 17(Prescaler), feedback divider 18(Feedback Divider) backfeed loop that connects and composes.Respective modules basically identical in the circuit framework of these modules and signal processing and existing single channel or the binary channels radio-frequency transmitter.
In addition, with basically identical in the existing binary channels radio-frequency transmitter, the intermediate-freuqncy signal that the first time, down-converted obtained among the present invention is handled by intermediate-frequency filter 61 in first passage, obtains the first intermediate frequency switching signal CH1_IF corresponding with first via radiofrequency signal.The intermediate-freuqncy signal of down-converted via after double down converter 52 and intermediate-frequency filter 62 processing, obtains the second intermediate frequency switching signal CH2_IF corresponding with the second tunnel radiofrequency signal in second channel for the first time.Described intermediate frequency switching signal CH1_IF and CH2_IF are respectively in first, second passage, after variable gain amplifier 71,72 amplifications that are provided with respectively, each free analog to digital converter 81,82 is handled and is obtained the two digits signal again, promptly, the polar signal SIGN1 of first passage and range signal MAG1, the polar signal SIGN2 of second channel and range signal MAG2.Variable gain amplifier control circuit 91,92 is again with range signal MAG1, the MAG2 of correspondence, and the variable gain amplifier 71,72 of passage is used for the detection of signal intensity under feeding back to respectively.
As shown in table 2 is more common several double-channel signals combination, for example be GPS of America respectively with Russian Glonass, the Chinese Big Dipper or European Union's Galileo in a kind of composition binary channels.The intermediate frequency planning that provides for each passage and the frequency scheme of analog to digital conversion sample frequency have been provided in the table 2 according to different reference clocks.
The twin-channel reference clock of table 2, intermediate frequency, bandwidth and ADC clock
As seen from the above table, in each binary channels combination, the sampling clock CLK that described two analog to digital converters 81,82 use is identical.This sampling clock CLK is by a shared sampling clock module 11(ADC CLK GEN of first, second passage) and a clock isolation amplifier 101(CLK BUF) provide after the processing successively.After local frequency LOI, the LOQ that described sampling clock module 11 is exported according to the frequency synthesizer phaselocked loop carries out frequency division to reference clock Ref CLK, carry out shaping by clock isolation amplifier 101 again and handle, the sampling clock CLK that obtains thus is sent to 81,82 and multiplexing handover module 103(ADC MUX of described two analog to digital converters simultaneously).Described reference clock Ref CLK is the clock signal (TCXO_IN) of the outer input of sheet, via what obtain after another clock isolation amplifier 10 shapings.
Described multiplexing handover module 103 is also shared by first, second passage, it is to two the polar signal SIGN1 and the SIGN2 of 81,82 outputs of described two analog to digital converters, reach two range signal MAG1 and MAG2 and carry out conversion processing, and with the polarity composite signal SIGN and the amplitude composite signal MAG that obtain, wherein two ports of same set of IO output pin by this multiplexing handover module 103, the digital baseband outside sheet sends.Described multiplexing handover module 103 also is provided with the 3rd port, and the sampling clock CLK that analog to digital conversion is used carries out obtaining sampling output clock CLK_OUT after the certain time-delay, and should sample and export clock CLK_OUT and send outside sheet, is used as data sync.
Because in first passage, analog-to-digital output timing required be, when sampling clock CLK carries out data output during for high level; Carry out data during for low level and keep the data consistent when making its polar signal SIGN1 and range signal MAG1 and high level.On the contrary, in second channel, its analog-to-digital output timing requires to be output data when sampling clock CLK is low level; Keep data, the data consistent when making its polar signal SIGN2 and range signal MAG2 and low level during for high level.
Therefore, can be in described multiplexing handover module 103 by CLK_SEL(CLK through certain time-delay) high-low level, decision final on the IO output pin outwards the polarity composite signal SIGN and the amplitude composite signal MAG of output.For example, when CLK_SEL is low level, select final signal to be output as the polar signal SIGN2 and the range signal MAG2 of second channel; And when sampling output clock CLK_SEL was high level, selecting final output signal was the polar signal SIGN1 and the range signal MAG1 of first passage.And because when finally being output as the first passage data, the data of second channel are maintained and can not omit; Same, when finally being output as the second channel data, the data of first passage can not omitted yet.In addition, can also in multiplexing handover module 103, carry out certain delay, guarantee to export the required time of setting (setup) sampling clock CLK.
It below is concrete elaboration to the above-mentioned implementation process of binary channels radio-frequency transmitter of the present invention, wherein all will receive and handle GPS of America signal (being designated hereinafter simply as the GPS passage) with first passage, second channel receives Russian Glonass signal (following replace Glonass with GLN, and abbreviate the GLN passage as) and describes for example.Hereinafter also with the data message of exporting in the GPS passage, promptly the SIGN1 of first passage and MAG1 signal abbreviate gps data as; And with the data message of exporting in the GLN passage, promptly the SIGN2 of second channel and MAG2 signal abbreviate the GLN data as.
Be the GPS passage as shown in Figure 4 with the GLN passage in the sequential of analog-digital conversion data is required: the GPS passage uses identical sampling clock CLK with the GLN passage.When sampling clock CLK for high level time output gps data, at this moment, the GLN data remain on the state of CLK when being low level.When sampling clock CLK for low level time output GLN data, at this moment, gps data remains on the state of CLK when being high level.
On the basis of Fig. 4, cooperate referring to shown in Figure 5, the multiplexing process process of 103 pairs of signals of multiplexing handover module is described.Wherein, delayed clock CLK_SEL carries out forming after the time-delay in 1/4 cycle to the sampling clock CLK that imports multiplexing handover module 103.The benefit of doing like this is when carrying out intelligence sample on GPS and GLN passage, setting (setup) time and maintenance (hold) time about 1/4 cycle to have been arranged.
When delayed clock CLK_SEL was high level, the multiplexing output information OUTPUT(that is sent outside sheet by multiplexing handover module 103 was polarity composite signal SIGN and amplitude composite signal MAG, down together), essence is gps data; When delayed clock CLK_SEL was low level, multiplexing output information OUTPUT essence was the GLN data.In OUTPUT curve shown in Figure 5, N represents to be output as the GLN data, and S represents to be output as gps data.As seen, the high-low level control by delayed clock CLK_SEL can comprise the data message of GPS and GLN passage simultaneously in multiplexing output information OUTPUT.
On the basis of Fig. 4, Fig. 5, further cooperate referring to shown in Figure 6, the sampling output clock CLK_OUT that multiplexing handover module 103 is sent to sheet in addition, on the basis of delayed clock CLK_SEL, postpone the formation of 1/4 cycle again, thereby this sampling output clock CLK_OUT is the equal of described sampling clock CLK through 1 grade of clock after oppositely.At this moment, in binary channels of the present invention navigation radio-frequency transmitter, handle the data message that obtains through multiplexing handover module 103, can be compatible fully with the data-signal that obtains in the single channel GPS navigation radio-frequency transmitter.
That is to say that the high-low level according to described sampling output clock CLK_OUT can restore wherein GPS and GLN data from multiplexing output information OUTPUT.In Fig. 6, by sampling output clock CLK_OUT, multiplexing output information OUTPUT is carried out rising edge to be triggered, just can obtain a new data message GPS ', these data GPS ' carries out the delay of half period to the gps data that first passage is exported, in addition, data GPS ' and gps data basically identical.Similarly, by sampling output clock CLK_OUT, multiplexing output information OUTPUT is carried out negative edge trigger, the data message that obtains is GLN ', is equivalent to the GLN data of second channel output have been carried out the delay of half period.
In addition, to the multiplex process of analog to digital conversion output, can be extended to other binary channels combinations in table 1 for example or the table 2 among above-mentioned use GPS of the present invention and the twin-channel embodiment of GLN.Therefore, the binary channels radio-frequency transmitter of framework of the present invention will be used, finish demodulation by first passage, second channel correspondence to the two-way radiofrequency signal, and the data processing method of in described multiplexing handover module 103, two channel multiplexing analog to digital conversion being exported afterwards, be summarised as following step:
In first passage, output data when sampling clock CLK is high level; Keep data, the data consistent when making its polar signal SIGN1 and range signal MAG1 and high level during for low level;
In second channel, output data when sampling clock CLK is low level; Keep data, the data consistent when making its polar signal SIGN2 and range signal MAG2 and low level during for high level.
According to this delayed clock CLK_SEL, the analog-digital conversion data to two passages in described multiplexing handover module 103 transforms, and with the polarity composite signal SIGN and the amplitude composite signal MAG that obtain, exports outside sheet as its multiplexing output information OUTPUT;
At the above embodiments, when delayed clock CLK_SEL was high level, the multiplexing output information OUTPUT of transmission was the polar signal SIGN1 and the range signal MAG1 of first passage; When delayed clock CLK_SEL was low level, multiplexing output information OUTPUT was the polar signal SIGN2 and the range signal MAG2 of second channel.
In the time of the above-mentioned multiplexing output information OUTPUT of step 3, output,, use during for the data message of two passages among the described multiplexing output information OUTPUT of follow-up reduction by multiplexing handover module 103 outputs one sampling output clock CLK_OUT;
Described sampling output clock CLK_OUT obtains after delayed clock CLK_SEL is further postponed, thereby makes this sampling output clock CLK_OUT be equivalent to described sampling clock CLK oppositely and the clock that obtains behind the delay some cycles;
Thereby, equally at the above embodiments, exporting clock CLK_OUT according to described sampling, in the process that multiplexing output information OUTPUT is reduced, when sampling output clock CLK_OUT negative edge triggered, the information that obtains was the polar signal SIGN2 and the range signal MAG2 of the second channel after the corresponding delay; And when sampling output clock CLK_OUT was the rising edge triggering, the signal that obtains was the polar signal SIGN1 and the range signal MAG1 of the first passage after the corresponding delay.
Need to prove, above-mentioned when setting delayed clock CLK_SEL or sampling output clock CLK_OUT, also can set other time delay.For example, when forming described delayed clock CLK_SEL, can be sampling clock CLK to be postponed (a+1/4) individual cycle (a for more than or equal to 0 integer), come control setting (setup) time and maintenance (hold) time.Perhaps, when the described sampling output of formation clock CLK_OUT, can be delayed clock CLK_SEL to be postponed (b+1/4) individual cycle (b is the integer more than or equal to 0), thereby make sampling output clock CLK_OUT become the clock that described sampling clock CLK is reverse and postpone respective cycle.Or, can also be when the described sampling output of formation clock CLK_OUT, delayed clock CLK_SEL is postponed (c+3/4) individual cycle (c be the integer more than or equal to 0), thereby make sampling output clock CLK_OUT become described sampling clock CLK in the same way and the clock of delay respective cycle.In above-mentioned three kinds of possible embodiment, compare the data of the multiplexing handover module 103 of input, the data message that last multiplexing output or reduction obtain, the delay in corresponding several semiperiods or several cycles will occur, and the data of using rising edge or negative edge triggering to obtain specifically are that corresponding which passage also may be opposite.Therefore, need carry out concrete analysis at the embodiment that provides different time delays.
In sum, binary channels navigation radio-frequency transmitter of the present invention, can binary channels receive two GNSS radiofrequency signals, thereby improve the accuracy of location, and, be provided with multiplexing handover module especially, the data of double-channel analog/digital conversion output are carried out conversion process, and the multiplexing output data that will obtain outwards exported.Because binary channels of the present invention navigation radio-frequency transmitter has and the on all four exterior I O output pin of single channel navigation radio-frequency transmitter, can save the Chip Packaging cost, again can with the single-channel receiver compatibility, as its upgraded version.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple modification of the present invention with to substitute all will be conspicuous.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (9)
1. the binary channels radio-frequency transmitter of a multiplexing analog to digital conversion output, it is characterized in that, be provided with first, second passage and come the corresponding two-way radiofrequency signal (RF1, RF2) that receives, convert radiofrequency signal to corresponding first, second intermediate frequency switching signal (CH1_IF, CH2_IF) separately afterwards, the subsequent conditioning circuit in described two passages sends respectively;
In first, second passage, be provided with variable gain amplifier (71,72) and analog to digital converter (81,82) separately, in these two passages, respectively first, second intermediate frequency switching signal (CH1_IF, CH2_IF) after amplifying is carried out analog to digital conversion, obtain the polar signal (SIGN1) and the range signal (MAG1) of first passage, and polar signal of second channel (SIGN2) and range signal (MAG2); Also be provided with variable gain amplifier control circuit (91,92) in first, second passage separately, range signal (MAG1, MAG2) wherein fed back to the variable gain amplifier (71,72) of correspondence;
Described two passages are an also shared multiplexing handover module (103), come the analog-digital conversion data of first, second passage is carried out multiplexing process, obtain the polarity composite signal (SIGN) that forms by described two polar signals (SIGN1, SIGN2) conversions, and the amplitude composite signal (MAG) that forms by described two range signals (MAG1, MAG2) conversion;
Described two analog to digital converters (81,82) use identical sampling clock (CLK) when carrying out analog to digital conversion; Described multiplexing handover module (103) also receives described sampling clock (CLK), and is translated into the sampling output clock (CLK_OUT) that is used for data sync;
Described multiplexing handover module (103) is provided with some IO output pins, comprise respectively that the digital baseband outside sheet sends described polarity composite signal (SIGN), described amplitude composite signal (MAG), and one group of port of described sampling output clock (CLK_OUT);
Wherein, sampling clock (CLK) with input in described multiplexing handover module (103) obtains delayed clock (CLK_SEL) after carrying out certain time-delay, setting and retention time when carry out multiplexing output and handle as described multiplexing handover module (103) this time delay;
The multiplexing output information (OUTPUT) of described multiplexing handover module (103) output comprises the analog-digital conversion data of first passage and second channel simultaneously;
And when described delayed clock (CLK_SEL) was high level, described multiplexing output information (OUTPUT) was the analog-digital conversion data of a passage in first passage or the second channel; When described delayed clock (CLK_SEL) was low level, described multiplexing output information (OUTPUT) was the analog-digital conversion data of another passage wherein.
2. the binary channels radio-frequency transmitter of multiplexing analog to digital conversion output as claimed in claim 1 is characterized in that,
Radio-frequency (RF) front-end circuit that described two passages are shared is carried out the down-converted first time to the described two-way radiofrequency signal (RF1, RF2) that receives; The required local frequency (LOI, LOQ) of down coversion is provided by two shared frequency synthesizer phaselocked loops of passage for the first time;
In the described radio-frequency (RF) front-end circuit, comprise the outer acoustic filter (2) of low noise amplifier (1), sheet, radio frequency prime amplifier (3) and the quadrature down converter (4,5) that connect successively;
In the described frequency synthesizer phaselocked loop, comprise the backfeed loop that connects and composes by phase frequency detector (12), charge pump (13), loop filter (14), voltage controlled oscillator (15), two-divider (16), pre-divider (17) and feedback divider (18).
3. the binary channels radio-frequency transmitter of multiplexing analog to digital conversion output as claimed in claim 2 is characterized in that,
In described first passage, also be included in the intermediate-frequency filter (61) that described quadrature down converter (4,5) is provided with afterwards, it carries out Filtering Processing to down coversion first time intermediate-freuqncy signal afterwards, obtains and the corresponding first intermediate frequency switching signal (CH1_IF) of first via radiofrequency signal (RF1);
In described second channel, also be included in double down converter (52) and intermediate-frequency filter (62) that described quadrature down converter (4,5) is provided with afterwards, to the intermediate-freuqncy signal after the first time down coversion carry out the second time down coversion and Filtering Processing after, obtain the second intermediate frequency switching signal (CH2_IF) corresponding with the second tunnel radiofrequency signal (RF2).
4. the binary channels radio-frequency transmitter of multiplexing analog to digital conversion output as claimed in claim 3 is characterized in that,
Described two passages are also shared connect successively with lower module:
A clock isolation amplifier (10) after its clock signal to the outside input is carried out shaping, is sent to described frequency synthesizer phaselocked loop with the reference clock (Ref CLK) that obtains;
A sampling clock module (11), it carries out the frequency division processing according to the described reference clock (Ref CLK) that receives to the local frequency (LOI, LOQ) that described frequency synthesizer phaselocked loop sends, and obtains sample frequency;
A clock isolation amplifier (101), its with the sample frequency shaping after, send identical sampling clock (CLK) and give described two analog to digital converters (81,82) and described multiplexing handover module (103).
5. the binary channels radio-frequency transmitter of multiplexing analog to digital conversion output as claimed in claim 1 is characterized in that,
The sampling output clock (CLK_OUT) of described multiplexing handover module (103) output carries out obtaining after the certain time-delay to delayed clock (CLK_SEL);
When sampling output clock (CLK_OUT) triggered for rising edge, the sheet external circuit restored the analog-digital conversion data of a passage in first passage or the second channel from described multiplexing output information (OUTPUT); When sampling output clock (CLK_OUT) triggers for negative edge, restore the wherein analog-digital conversion data of another passage.
6. the binary channels radio-frequency transmitter of multiplexing analog to digital conversion output as claimed in claim 2 is characterized in that,
Described delayed clock (CLK_SEL) forms 1/4 all after date of sampling clock (CLK) time-delay; When delayed clock (CLK_SEL) was high level, described multiplexing output information (OUTPUT) was the analog-digital conversion data of first passage; When delayed clock (CLK_SEL) was low level, described multiplexing output information (OUTPUT) was the analog-digital conversion data of second channel;
Described sampling output clock (CLK_OUT) formed 1/4 cycle of described delayed clock (CLK_SEL) time-delay, and described sampling output clock (CLK_OUT) is a described sampling clock (CLK) through 1 grade of clock after oppositely;
When described sampling output clock (CLK_OUT) triggers for negative edge, from described multiplexing output information (OUTPUT), the analog-digital conversion data that obtains second channel of the reducing data after the half period of delaying time; When sampling output clock (CLK_OUT) triggers for rising edge, the analog-digital conversion data that obtains first passage of the reducing data after the half period of delaying time.
In the binary channels radio-frequency transmitter to the data processing method of multiplexing analog to digital conversion output, it is characterized in that, be provided with first, second passage in the described binary channels radio-frequency transmitter and come the corresponding two-way radiofrequency signal (RF1, RF2) that receives; In first passage, carry out the first time down coversion and Filtering Processing after, obtain and the corresponding first intermediate frequency switching signal (CH1_IF) of first via radiofrequency signal (RF1); In second channel, carry out for the first time, for the second time after down coversion and the Filtering Processing, obtain the second intermediate frequency switching signal (CH2_IF) corresponding with the second tunnel radiofrequency signal (RF2); Afterwards, in first, second passage, carry out analog-to-digital conversion process separately to described first, second intermediate frequency switching signal (CH1_IF, CH2_IF);
Be provided with a multiplexing handover module (103) in the described binary channels radio-frequency transmitter, it is shared by first, second passage; Described multiplexing handover module (103) carries out multiplexing process after by the outside method that sends of same group of IO output pin, specifically comprise following steps with the analog-digital conversion data of first, second passage:
Step 1, in first passage, second channel, carry out analog to digital conversion respectively with identical sampling clock (CLK), its analog-to-digital output timing is as follows:
In first passage, when sampling clock (CLK) is high level, export the polar signal (SIGN1) and the range signal (MAG1) of the corresponding first intermediate frequency switching signal (CH1_IF), as the analog-digital conversion data of this passage; When sampling clock (CLK) is low level, carries out data and keep;
In second channel, when sampling clock (CLK) is low level, export the polar signal (SIGN2) and the range signal (MAG2) of the corresponding second intermediate frequency switching signal (CH2_IF), as the analog-digital conversion data of this passage; When sampling clock (CLK) is high level, carries out data and keep;
Step 2, sampling clock (CLK) the time-delay very first time to input in multiplexing handover module (103) obtain a delayed clock (CLK_SEL); According to this delayed clock (CLK_SEL), comprise the multiplexing output information (OUTPUT) of the analog-digital conversion data of first passage and second channel simultaneously to the outer output of sheet by described multiplexing switching mould (103);
In the time of step 3, the described multiplexing output information of output (OUTPUT), also delayed clock (CLK_SEL) is obtained a sampling output clock (CLK_OUT) after second time of delay by multiplexing handover module (103); According to this sampling output clock (CLK_OUT), by the sheet external circuit described multiplexing output information (OUTPUT) is reduced processing, the data that reduction obtains and the analog-digital conversion data of described two passages data after the very first time of having delayed time added for second time are corresponding.
8. to the data processing method of multiplexing analog to digital conversion output, it is characterized in that in the binary channels radio-frequency transmitter as claimed in claim 7,
Delayed clock described in the step 2 (CLK_SEL) obtained sampling clock (CLK) delay " a+1/4 " individual cycle, and wherein a is the integer more than or equal to 0;
When delayed clock (CLK_SEL) is high level, described multiplexing output information (OUTPUT) be first passage analog-digital conversion data; When delayed clock (CLK_SEL) was low level, described multiplexing output information (OUTPUT) was the analog-digital conversion data of second channel.
9. to the data processing method of multiplexing analog to digital conversion output, it is characterized in that in the binary channels radio-frequency transmitter as claimed in claim 7,
Sampling output clock (CLK_OUT) described in the step 3 postpones " b+1/4 " individual cycle formation to delayed clock (CLK_SEL), and wherein b is the integer more than or equal to 0; And described sampling output clock (CLK_OUT) is the clock after described sampling clock (CLK) process oppositely reaches corresponding delay;
When described sampling output clock (CLK_OUT) triggered for negative edge, what restore was the analog-digital conversion data of second channel after the corresponding delay; And when sampling output clock (CLK_OUT) triggered for rising edge, what restore was the analog-digital conversion data of first passage after the corresponding delay.
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