CN102508415A - Photoetching process flow and method for eliminating photoetching defects - Google Patents
Photoetching process flow and method for eliminating photoetching defects Download PDFInfo
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- CN102508415A CN102508415A CN2011103421719A CN201110342171A CN102508415A CN 102508415 A CN102508415 A CN 102508415A CN 2011103421719 A CN2011103421719 A CN 2011103421719A CN 201110342171 A CN201110342171 A CN 201110342171A CN 102508415 A CN102508415 A CN 102508415A
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- postexposure bake
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- 238000000034 method Methods 0.000 title claims abstract description 73
- 230000007547 defect Effects 0.000 title claims abstract description 28
- 238000001259 photo etching Methods 0.000 title claims abstract description 13
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 13
- 239000011248 coating agent Substances 0.000 claims abstract 2
- 238000000576 coating method Methods 0.000 claims abstract 2
- 230000008030 elimination Effects 0.000 claims description 18
- 238000003379 elimination reaction Methods 0.000 claims description 18
- 238000000206 photolithography Methods 0.000 claims description 8
- 238000011161 development Methods 0.000 claims description 6
- 238000001459 lithography Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 abstract description 14
- 238000004519 manufacturing process Methods 0.000 abstract description 9
- 238000006243 chemical reaction Methods 0.000 abstract description 4
- 230000018044 dehydration Effects 0.000 abstract 1
- 238000006297 dehydration reaction Methods 0.000 abstract 1
- 239000002994 raw material Substances 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 abstract 1
- 230000002950 deficient Effects 0.000 description 33
- 238000005530 etching Methods 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910021642 ultra pure water Inorganic materials 0.000 description 3
- 239000012498 ultrapure water Substances 0.000 description 3
- 238000004140 cleaning Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 230000003292 diminished effect Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
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Abstract
The present invention provides a photoetching process flow and a method for eliminating photoetching defects. The method is used for eliminating satellite spot defects of a contact hole layer in the photoetching process flow during the course of semiconductor apparatus manufacture. The photoetching process flow includes steps of coating photoresist, baking, exposing, postexposure baking, developing and dehydration baking. The method for eliminating satellite spot defects of the contact hole layer is to regulate the postexposure baking time in the postexposure baking step. The photoresist reaction of the exposure region is more complete through the enlarged postexposure baking time by optimizing the postexposure baking time of wafers, thereby eliminating the portion of exposed photoresist more easily during the next developing process, so the satellite spot defects of the contact hole layer can be eliminated thoroughly and the consumption increase of raw materials does not be required, and the yield of final semiconductor products is increased.
Description
Technical field
The present invention relates to field of semiconductor manufacture; More particularly; The photoetching method that the present invention relates to a kind of contact hole layer satellite spot defect elimination method and adopted this contact hole layer satellite spot defect elimination method the invention still further relates to the semiconductor devices of processing thus in addition.
Background technology
Make in the lithographic process at wafer, defective can reduce the yield of wafer, and spot defects is a kind of major defect in the lithographic process.Spot defects is also referred to as " satellite spot defective ", be by the top coat material develop and cleaning step in be deposited on again on the photoresist surface and form.This defective is the most common in the low-density graphics field, and diameter is between 1～10nm.Fig. 1 schematically shows the diagrammatic sketch of the satellite spot defective in the wafer manufacturing lithographic process in the prior art, and wherein the stain position shows the position at defective place.
More particularly; Make in the lithographic process at wafer; Above the contact hole that this satellite spot defective can cover lithographic process after accomplishing, the contact hole after the etching is diminished or etching fully, cause metal interlevel not exclusively to connect or can't connect so that the yield reduction.Fig. 2 schematically shows the diagrammatic sketch of the problem that the satellite spot defective produced.Under the influence of satellite spot defective A, the contact hole layer pattern is not connected with bottom 1 through after the etching, is in off-state.
Classic method reduces the satellite spot defective through time that increases development or the time that increases the ultrapure water cleaning.But classic method can only reduce the satellite spot defective, and can not thoroughly eliminate this satellite spot defective.Fig. 3 schematically shows the diagrammatic sketch that improved wafer of the prior art is made the satellite spot defective in the lithographic process.As shown in Figure 3, even through time of increase developing or increase the time that ultrapure water cleans and still can not thoroughly eliminate this satellite spot defective.And classic method need increase the consumption of the former material of developer solution or ultrapure water, has increased the cost that semiconductor devices is made.
Summary of the invention
An object of the present invention is to deficiency of the prior art, propose a kind of contact hole layer satellite spot defect elimination method of the satellite spot defective that can under the condition of cost that does not increase the semiconductor devices manufacturing, thoroughly eliminate contact hole layer and the photoetching method that has adopted this contact hole layer satellite spot defect elimination method.
According to a first aspect of the invention; Contact hole layer satellite spot defect elimination method in a kind of photolithography process in fabrication of semiconductor device is provided, and its photolithography process comprises: apply photoresist step, baking procedure, step of exposure, postexposure bake step, development step and dewatering roast step; Wherein, in said postexposure bake step, the adjustment postexposure bake time.
Preferably, in described contact hole layer satellite spot defect elimination method, in said postexposure bake step, increase the time of postexposure bake through the adjustment of board technological parameter.
Preferably, in described contact hole layer satellite spot defect elimination method, in said postexposure bake step, to postexposure bake time t, the postexposure bake time is adjusted into nt, wherein n is the rational number greater than 1.
Preferably, in described contact hole layer satellite spot defect elimination method, in said postexposure bake step, the postexposure bake time for 60 seconds, it is adjusted into 110 seconds.
Preferably, in described contact hole layer satellite spot defect elimination method, in said lithography step, cooperate the adjustment of postexposure bake time to adjust photoetching process.
The present invention is through optimizing the time of toasting behind the exposing wafer; Make the postexposure bake time that increases make the reaction of exposed areas photoresist more complete; Thereby the photoresist that this part was made public is more prone to remove in the process of the development of back; Can thoroughly eliminate the satellite spot defective of contact hole layer thus, and need not increase the consumption of former material, and then improve the yield of final semiconductor product.
According to a second aspect of the invention, a kind of photoetching method is provided, it has been used according to the described contact hole layer satellite spot of first aspect present invention defect elimination method.
Owing to adopted according to the described contact hole layer satellite spot of first aspect present invention defect elimination method; Therefore; It will be appreciated by persons skilled in the art that according to the photoetching method of second aspect present invention and can realize the useful technique effect that contact hole layer satellite spot defect elimination method according to a first aspect of the invention can be realized equally.Promptly; The present invention is through optimizing the time of toasting behind the exposing wafer; Make the postexposure bake time that increases make the reaction of exposed areas photoresist more complete, thereby the photoresist that this part was made public is more prone to remove, and can thoroughly eliminate the satellite spot defective of contact hole layer thus in the process of the development of back; And need not increase the consumption of former material, and then improve the yield of final semiconductor product.
According to a third aspect of the invention we, a kind of semiconductor devices is provided, has it is characterized in that its manufacturing approach used the described contact hole layer satellite spot of first aspect present invention defect elimination method.Thus, thoroughly eliminate the satellite spot defective of contact hole layer in the semiconductor devices according to a third aspect of the invention we, yield is greatly enhanced.
Description of drawings
In conjunction with accompanying drawing, and, will more easily more complete understanding be arranged and more easily understand its attendant advantages and characteristic the present invention through with reference to following detailed, wherein:
Fig. 1 schematically shows the diagrammatic sketch of the satellite spot defective in the wafer manufacturing lithographic process in the prior art.
Fig. 2 schematically shows the diagrammatic sketch of the problem that the satellite spot defective produced.
Fig. 3 schematically shows the diagrammatic sketch that improved wafer of the prior art is made the satellite spot defective in the lithographic process.
Fig. 4 schematically shows the diagrammatic sketch of making the satellite spot defective in the lithographic process according to the wafer of the embodiment of the invention.
The diagrammatic sketch of Fig. 5 schematically shows that contact hole layer satellite spot defect elimination method according to the embodiment of the invention obtains when not having satellite spot semiconductor devices.
Need to prove that accompanying drawing is used to explain the present invention, and unrestricted the present invention.Notice that the accompanying drawing of expression structure possibly not be to draw in proportion.And in the accompanying drawing, identical or similar elements indicates identical or similar label.
Embodiment
In order to make content of the present invention clear more and understandable, content of the present invention is described in detail below in conjunction with specific embodiment and accompanying drawing.
The key step of the lithographic process of contact hole layer is: at first apply photoresist; Toast subsequently; Carry out exposure afterwards; Be postexposure bake then; After this develop; Carry out dewatering roast at last.
Usually, the effect of " toasting behind the exposing wafer " this step in the contact hole layer manufacturing is: eliminate the standing wave effect of lithographic process, the live width of control lithographic process.
And making in the lithographic process according to the wafer of the embodiment of the invention, in order to eliminate the satellite spot defective, can be to the contact hole layer lithographic process of wafer manufacturing, baking (the PEB:Post exposure bake) time behind the exposing wafer of optimizing application.
Specifically, making in the lithographic process, eliminating defective through the time that increases postexposure bake according to the wafer of the embodiment of the invention; Make the postexposure bake time that increases make the reaction of exposed areas photoresist more complete, thereby the photoresist that this part was made public is more prone to remove, and can thoroughly eliminate the satellite spot defective of contact hole layer thus in the process of the development of back.And, specifically, for example can increase the time of postexposure bake through the adjustment of board technological parameter.
For example, to postexposure bake time t, can the postexposure bake time be adjusted into nt, wherein n is the rational number greater than 1.
More particularly, in a specific embodiment,, it is adjusted into 110 seconds for 60 seconds the postexposure bake time of script.Perhaps, alternatively,, it is adjusted into 120 seconds for 60 seconds the postexposure bake time of script.
Further; Through utilizing above-mentioned contact hole layer satellite spot defect elimination method; The wafer of accomplishing lithographic process is carried out the scanning of satellite spot defective; Inspection wafer satellite spot defective under scanning electron microscope can find out that the wafer of optimization postexposure bake time is not found the satellite spot defective then.
Specifically, Fig. 4 schematically shows the diagrammatic sketch of making the satellite spot defective in the lithographic process according to the wafer of the embodiment of the invention.As shown in Figure 4, after the contact hole layer satellite spot defect elimination method that has adopted according to the embodiment of the invention, can find that the satellite spot defective is thoroughly eliminated through after the satellite spot defective is scanned.Further the contact hole to metal interlevel scans and can find, the problem that the metal interlevel that causes owing to the satellite spot defective not exclusively connects or can't connect is also thoroughly eliminated.Fig. 5 schematically show according to the embodiment of the invention do not have the satellite spot defective time semiconductor devices diagrammatic sketch.Of Fig. 5, owing to there is not satellite spot defective A shown in Figure 2, the contact hole layer pattern is connected well with bottom 1 through after the etching.
And,, can know that the yield of final products is improved through final products are carried out quality test.
According to another embodiment of the present invention, the invention provides a kind of photoetching method, it has been used according to the described contact hole layer satellite spot of the above embodiment of the present invention defect elimination method.
In addition, according to another embodiment of the present invention, the invention still further relates to the semiconductor devices that utilizes said method to process.
In addition, those skilled in the art it is understandable that though with each step in the above-mentioned flow process the present invention has been described, the present invention does not get rid of the existence of other step except above-mentioned steps.Those skilled in the art it is understandable that, can in described step, add other step to form other structure or to realize other purpose without departing from the scope of the invention.
It is understandable that though the present invention with the preferred embodiment disclosure as above, yet the foregoing description is not in order to limit the present invention.For any those of ordinary skill in the art; Do not breaking away under the technical scheme scope situation of the present invention; All the technology contents of above-mentioned announcement capable of using is made many possible changes and modification to technical scheme of the present invention, or is revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical scheme of the present invention, all still belongs in the scope of technical scheme protection of the present invention any simple modification, equivalent variations and modification that above embodiment did according to technical spirit of the present invention.
Claims (6)
1. a photolithography process comprises coating photoresist step, baking procedure, step of exposure, postexposure bake step, development step and dewatering roast step; Wherein, in said postexposure bake step, the adjustment postexposure bake time.
2. photolithography process according to claim 1 is characterized in that, in said postexposure bake step, increases the time of postexposure bake through the adjustment of board technological parameter.
3. photolithography process according to claim 1 and 2 is characterized in that, in said postexposure bake step, to postexposure bake time t, the postexposure bake time is adjusted into nt, and wherein n is the rational number greater than 1.
4. photolithography process according to claim 1 and 2 is characterized in that, in said postexposure bake step, the postexposure bake time for 60 seconds, it is adjusted into 110 seconds.
5. photolithography process according to claim 1 and 2 is characterized in that, in said lithography step, cooperates the adjustment of postexposure bake time to adjust photoetching process.
6. the removing method of a photomask defect is characterized in that having used according to the described contact hole layer satellite spot of one of claim 1 to 5 defect elimination method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011103421719A CN102508415A (en) | 2011-11-02 | 2011-11-02 | Photoetching process flow and method for eliminating photoetching defects |
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| Application Number | Priority Date | Filing Date | Title |
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| CN2011103421719A CN102508415A (en) | 2011-11-02 | 2011-11-02 | Photoetching process flow and method for eliminating photoetching defects |
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| CN102508415A true CN102508415A (en) | 2012-06-20 |
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| CN2011103421719A Pending CN102508415A (en) | 2011-11-02 | 2011-11-02 | Photoetching process flow and method for eliminating photoetching defects |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109839801A (en) * | 2017-11-24 | 2019-06-04 | 山东华光光电子股份有限公司 | A method of improving photomask defect and extends reticle service life |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1243270A (en) * | 1999-08-27 | 2000-02-02 | 清华大学 | Positive-negative interoperable chemical amplifying slushing agent and photoetching technology |
| US6358672B2 (en) * | 1998-02-05 | 2002-03-19 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device pattern including cross-linking and flow baking a positive photoresist |
| US20040121588A1 (en) * | 2002-12-23 | 2004-06-24 | Choi Jae Sung | Method of forming dual damascene pattern in semiconductor device |
| CN101251715A (en) * | 2008-03-25 | 2008-08-27 | 上海宏力半导体制造有限公司 | Photolithography method capable of improving graphical quality |
| CN101894792A (en) * | 2009-05-18 | 2010-11-24 | 世纪晶源科技有限公司 | Method for forming metal patterns by stripping |
-
2011
- 2011-11-02 CN CN2011103421719A patent/CN102508415A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6358672B2 (en) * | 1998-02-05 | 2002-03-19 | Samsung Electronics Co., Ltd. | Method of forming semiconductor device pattern including cross-linking and flow baking a positive photoresist |
| CN1243270A (en) * | 1999-08-27 | 2000-02-02 | 清华大学 | Positive-negative interoperable chemical amplifying slushing agent and photoetching technology |
| US20040121588A1 (en) * | 2002-12-23 | 2004-06-24 | Choi Jae Sung | Method of forming dual damascene pattern in semiconductor device |
| CN101251715A (en) * | 2008-03-25 | 2008-08-27 | 上海宏力半导体制造有限公司 | Photolithography method capable of improving graphical quality |
| CN101894792A (en) * | 2009-05-18 | 2010-11-24 | 世纪晶源科技有限公司 | Method for forming metal patterns by stripping |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109839801A (en) * | 2017-11-24 | 2019-06-04 | 山东华光光电子股份有限公司 | A method of improving photomask defect and extends reticle service life |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140509 |
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Effective date of registration: 20140509 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corp. Address before: 201203 Shanghai Guo Shou Jing Road, Pudong New Area Zhangjiang hi tech Park No. 818 Applicant before: Grace Semiconductor Manufacturing Corp. |
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Application publication date: 20120620 |