CN102541775A - Double-port RAM (random access memory) alternative system and method of using same to implement data transmission - Google Patents
Double-port RAM (random access memory) alternative system and method of using same to implement data transmission Download PDFInfo
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Abstract
The invention discloses a double-port RAM (random access memory) alternative system and a method of using the same to implement data transmission. The system comprises a first port, a second port, a first SRAM (static random access memory) interface, a second SRAM interface and a peripheral debugging circuit interface. Data transmission among the interfaces is implemented through an on-site programmable gate array. The first interface and the second interface are compatible to a first double-port RAM interface and a second double-port RAM interface respectively, and the first SRAM interface and the second SRAM interface correspond to odd addresses and even addresses of a whole storage space respectively. High-speed bidirectional data transmission is implemented by means of the first interface and the second interface compatible to the two interfaces of the double-port RAM respectively. The double-port RAM alternative system and the method of using the same to implement data transmission have the advantages of low cost, high speed, flexibility, easiness in extension and compatibility.
Description
Technical field
The present invention relates to the power automation field, relate in particular to a kind of dual port RAM alternative system and adopt this system to realize the method for data transmission.
Background technology
In the application of electric automation product; There is quite a few to use dual port RAM to realize in the high speed data transfer process of plate level,, for example has two covers independently to read and write bus on the hardware because dual port RAM has many good qualities; Can realize the read-write of asynchronous data, be easy to the modular design of integrated circuit board; Be easy to realize the isolation of agreement and the buffering of data on the software.But though existing dual port RAM is simple and easy to usefulness, the most outstanding shortcoming is exactly that capacity is little and price is high; Such as the IDT7028 of IDT company, be asynchronous 16 dual port RAMs of the said firm's max cap., capacity can only reach 16 of 64K; Price is but wanted 400 yuans; And a lot of occasions need 256K even higher capacity, and only the dual port RAM of an integrated circuit board just needs 1600 yuan at least, and only this item just possibly surpass the detailed estimate of integrated circuit board.
The inner RAM of the general at present FPGA of employing realizes dual port RAM; This mode realizes also fairly simple, but has the too high problem of cost equally, such as the EP3C55 that uses the lower ALTERA of price; About about 400 yuan of price; Can substitute two IDT7028, but price is still higher, adds that the dual port RAM of peripheral circuit realization 256K16 position approximately needs about 900 yuan; In addition, also there are the FPGA of use and a SRAM to realize dual port RAM, but mostly are to do a little simple logical process; Perhaps realize the data transmission that high speed is unidirectional,, realize bidirectional data transfers at a slow speed perhaps to the bus time-sharing multiplex; The all incompatible dual port RAM of this class interface major part even interface is accomplished compatibility, also can't be realized high speed data transfer; Possibly can only reach the transfer rate of 10-20M; Be unfavorable for transplanting system, more be unfavorable for for example can't realizing bidirectional data transfers of high-speed high capacity or the like the old dual port RAM system upgrade and the upgrading of later stage system performance in other.
Summary of the invention
The technical matters that the present invention will solve is; Cost to prior art is high; Speed is slow and can't compatible defective; A kind of dual port RAM alternative system is provided and adopt this system realize the method for data transmission, this technical scheme have cost low, at a high speed, flexibly, be easy to expand and compatible characteristics.
The technical solution adopted for the present invention to solve the technical problems is: construct a kind of dual port RAM alternative system; Said system comprises first interface, second interface, a SRAM interface, the 2nd SRAM interface and peripheral debug circuit interface; Realize data transmission through field programmable gate array between each interface; Wherein, First interface and second interface respectively with the first dual port RAM interface and the second dual port RAM interface compatibility, a SRAM interface and the 2nd SRAM interface is the odd address and the even address of corresponding whole storage space respectively.
In dual port RAM alternative system of the present invention, first interface, second interface, a SRAM interface and the 2nd SRAM interface include data bus, address bus and control bus.
In dual port RAM alternative system of the present invention, a SRAM interface and the 2nd SRAM interface are 16.
In dual port RAM alternative system of the present invention, the physical connection of a SRAM interface and the 2nd SRAM interface all is in separate state.
The present invention also constructs a kind of method that adopts the dual port RAM alternative system to realize data transmission, and said dual port RAM alternative system is above-mentioned each described dual port RAM alternative system, and said method comprises external interface read-write step and internal SRAM read-write step, wherein,
External interface read-write step comprises:
A1. receive user writable first order of transmission data in advance;
B1. transmit the pairing address of data through first interface and/or second interface in advance to said first and carry out read-write operation, transmit data in advance to read and write said first;
Internal SRAM read-write step comprises:
A2. the second transmission data in advance that receive when a SRAM controller and/or the 2nd SRAM controller are in idle condition that the user need read and write;
B2. according to a SRAM interface and/or the detected read-write of the 2nd SRAM interface, transmit data in advance to said second and handle accordingly.
In method of the present invention, said step B1 specifically may further comprise the steps:
B11. judge whether second interface is is reading and writing this address through first interface when in advance read-write operation is carried out in the pairing address of transmission data to said first, if, then send busy signal, if not, execution in step B12 then;
B12. judge that this address is read operation or write operation, if write operation, execution in step B13 then is if read operation then directly goes to step B16;
B13. under compose buffer is in idle condition, judge whether this compose buffer exists this address, if, execution in step S141 then, if not, execution in step S142 then;
B141. upgrade the transmission data in advance of said first in this address, step finishes;
B142. check whether this compose buffer is full, if, then send busy signal, step finishes, if not, execution in step B15 then;
B15. treat that transmitting data in advance with said first when bus is idle writes buffer zone, step finishes;
B16. judge whether this compose buffer exists this address, if, then directly go to step S182, if not, execution in step S17 then;
B17. judge whether the space of distributing this address is carrying out read-write operation, if, execution in step S181 then, if not, execution in step S182 then;
B181. read said first in the next read-write cycle and transmit data in advance;
B182. read said first and transmit data in advance.
In method of the present invention, said step B11 is further comprising the steps of:
Judge whether first interface is identical with the pairing address of second interface, if, confirm that according to priority first interface carries out write operation, second interface carries out write operation, still two interfaces are not write, if not, execution in step B12 then.
In method of the present invention, said steps A 2 is further comprising the steps of:
Judge whether a SRAM controller and/or the 2nd SRAM controller are in idle condition.
In method of the present invention, said step B2 specifically may further comprise the steps:
B21. judge whether the pairing SRAM interface in current address has the instruction of operating, if, execution in step B221 then, if not, execution in step B222 then;
B221. behind current EO, said preparatory transmission data are carried out read-write operation;
B222. directly said preparatory transmission data are carried out read-write operation.
The technical scheme of embodiment of the present invention; Have following beneficial effect: through realizing bidirectional data transfers at a high speed with first interface and second interface of two interface compatibilities of dual port RAM respectively, this technical scheme have cost low, at a high speed, flexibly, be easy to expand and compatible characteristics.
Description of drawings
To combine accompanying drawing and embodiment that the present invention is described further below, in the accompanying drawing:
Fig. 1 is the structural representation of dual port RAM alternative system of the present invention;
Fig. 2 is the process flow diagram of external tapping read-write step of the present invention;
Fig. 3 is the process flow diagram of internal SRAM read-write step of the present invention;
Fig. 4 is the particular flow sheet of B1 in the external tapping read-write step of the present invention;
Fig. 5 is the particular flow sheet of B2 in the internal SRAM read-write step of the present invention.
Embodiment
In order to make the object of the invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with accompanying drawing and embodiment.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
See also Fig. 1, Fig. 1 is the structural representation of dual port RAM alternative system of the present invention, and is as shown in Figure 1,
Said system comprises first interface, second interface, a SRAM interface, the 2nd SRAM interface and peripheral debug circuit interface; Realize data transmission through FPGA (Field-Programmable Gate Array, field programmable gate array) between each interface, wherein; First interface and second interface respectively with the first dual port RAM interface and the second dual port RAM interface compatibility; The one SRAM interface and the 2nd SRAM interface is the odd address and the even address of corresponding whole storage space respectively, and in the present embodiment, the array ram that the first dual port RAM interface and the second dual port RAM interface can use multi-disc RAM to form is realized the expansion of capacity; What deserves to be mentioned is; In the present embodiment, realize that the price of the dual port RAM of 512K only needs about 160 yuan, the high more average unit cost of capacity is also low more.
Preferably, first interface, second interface, a SRAM interface and the 2nd SRAM interface include data bus, address bus and control bus.
Preferably, a SRAM interface and the 2nd SRAM interface are 16, should be noted that in other embodiment, and the bit number of a SRAM interface and the 2nd SRAM interface can be other, and those skilled in the art should understand, and repeats no more here.
Preferably, the physical connection of a SRAM interface and the 2nd SRAM interface all is in separate state.That is to say that this enforcement can simultaneously and be operated a SRAM and the 2nd SRAM respectively, to accelerate the access speed of random read-write.
The present invention also provides a kind of method that adopts the dual port RAM alternative system to realize data transmission, and said method comprises external interface read-write step and internal SRAM read-write step, wherein,
See also Fig. 2, Fig. 2 is the process flow diagram of external tapping read-write step of the present invention, and is as shown in Figure 2, and external interface read-write step comprises:
In steps A 1, receive user writable first order of transmission data in advance.
In step B1, transmit the pairing address of data through first interface and/or second interface in advance to said first and carry out read-write operation, transmit data in advance to read and write said first.Should be noted that if first interface when write operation, needs to judge whether second interface is is reading and writing this address earlier; Just following step B11; Vice versa, if second interface when write operation, needs to judge whether first interface is is reading and writing this address earlier; Those skilled in the art should understand, and repeats no more here.
See also Fig. 3, Fig. 3 is the process flow diagram of internal SRAM read-write step of the present invention, and is as shown in Figure 3, and internal SRAM read-write step comprises:
In steps A 2, the second transmission data in advance that receive when a SRAM controller and/or the 2nd SRAM controller are in idle condition that the user need read and write.
Preferably, said steps A 2 is further comprising the steps of:
Judge whether a SRAM controller and/or the 2nd SRAM controller are in idle condition.Should be noted that if a SRAM controller and/or the 2nd SRAM controller are in busy condition this step that then circulates is till a SRAM controller and/or the 2nd SRAM controller are in idle condition.
In step B2,, transmit data in advance to said second and handle accordingly according to a SRAM interface and/or the detected read-write of the 2nd SRAM interface.Should be noted that in this enforcement, is odd address if current needs read; And the data in the even address have read-write operation; At this moment can read this data immediately, but if in the odd address order of operating is arranged, need wait for that then current operation reads these data after accomplishing again.
See also Fig. 4, Fig. 4 is the particular flow sheet of B1 in the external tapping read-write step of the present invention, and as shown in Figure 4, said step B1 specifically may further comprise the steps:
In step B11, judge whether second interface is is reading and writing this address through first interface when in advance read-write operation is carried out in the pairing address of transmission data to said first, if, then send busy signal, if not, execution in step B12 then.
Preferably, said step B11 is further comprising the steps of:
Judge whether first interface is identical with the pairing address of second interface, if, confirm that according to priority first interface carries out write operation, second interface carries out write operation, still two interfaces are not write, if not, execution in step B12 then.
Should be noted that in the present embodiment assumed priority is at 0 o'clock, first interface carries out write operation; Priority is 1 o'clock, and second interface carries out write operation; Priority is 2 o'clock, and first interface and second interface do not carry out write operation, and those skilled in the art should understand, and repeats no more here.
In step B12, judge that this address is read operation or write operation, if write operation, execution in step B13 then is if read operation then directly goes to step B16.
In step B13, under compose buffer is in idle condition, judge whether this compose buffer exists this address, if, execution in step S141 then, if not, execution in step S142 then.
In step B141, upgrade the transmission data in advance of said first in this address, step finishes.
In step B142, check whether this compose buffer is full, if, then send busy signal, if not, execution in step B15 then.
In step B15, treat that transmitting data in advance with said first when bus is idle writes buffer zone, step finishes.
In step B16, judge whether this compose buffer exists this address, if, then directly go to step S182, if not, execution in step S17 then.
In step B17, judge whether the space of distributing this address is carrying out read-write operation, if, execution in step S181 then, if not, execution in step S182 then.
In step B181, read said first in the next read-write cycle and transmit data in advance.
In step B182, read said first and transmit data in advance.
See also Fig. 5, Fig. 5 is the particular flow sheet of B2 in the internal SRAM read-write step of the present invention, and as shown in Figure 5, said step B2 specifically may further comprise the steps:
In step B21, judge whether the pairing SRAM interface in current address has the instruction of operating, if, execution in step B221 then, if not, execution in step B222 then.
In step B221, behind current EO, said preparatory transmission data are carried out read-write operation.
In step B222, directly said preparatory transmission data are carried out read-write operation.
Should be noted that in the present embodiment can realize and interface that dual port RAM is fully compatible that speed is superior to dual port RAM, dual port RAM is generally 20ns, be convenient to transplant and can directly substitute original dual port RAM system; On the 256K16 bit capacity, can realize the price of the dual port RAM 25% of different capabilities, under the situation of 1M16 position, have only with the capacity dual port RAM less than 15% price, and capacity be big more that cost is low more; Only need increase address wire during expansion and can expand more jumbo application; Possess read-write BUF at a high speed and reasonably logic control; Can also realize some special function through programming in addition, for example can realize the function that the data between 16 8 32 are changed arbitrarily.
In sum, compared to prior art, through realizing bidirectional data transfers at a high speed with first interface and second interface of two interface compatibilities of dual port RAM respectively, this technical scheme have cost low, at a high speed, flexibly, be easy to expand and compatible characteristics.
The above is merely the preferred embodiments of the present invention, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.All within spirit of the present invention and principle, any modification of being done, be equal to replacement, improvement etc., all should be included within the claim scope of the present invention.
Claims (9)
1. dual port RAM alternative system; It is characterized in that; Said system comprises first interface, second interface, a SRAM interface, the 2nd SRAM interface and peripheral debug circuit interface, realizes data transmission through field programmable gate array between each interface, wherein; First interface and second interface respectively with the first dual port RAM interface and the second dual port RAM interface compatibility, a SRAM interface and the 2nd SRAM interface is the odd address and the even address of corresponding whole storage space respectively.
2. dual port RAM alternative system according to claim 1 is characterized in that, first interface, second interface, a SRAM interface and the 2nd SRAM interface include data bus, address bus and control bus.
3. dual port RAM alternative system according to claim 2 is characterized in that, a SRAM interface and the 2nd SRAM interface are 16.
4. dual port RAM alternative system according to claim 3 is characterized in that, the physical connection of a SRAM interface and the 2nd SRAM interface all is in separate state.
5. method that adopts the dual port RAM alternative system to realize data transmission; It is characterized in that said dual port RAM alternative system is aforesaid right requirement 1 to 4 each described dual port RAM alternative system, said method comprises external interface read-write step and internal SRAM read-write step; Wherein
External interface read-write step comprises:
A1. receive user writable first order of transmission data in advance;
B1. transmit the pairing address of data through first interface and/or second interface in advance to said first and carry out read-write operation, transmit data in advance to read and write said first;
Internal SRAM read-write step comprises:
A2. the second transmission data in advance that receive when a SRAM controller and/or the 2nd SRAM controller are in idle condition that the user need read and write;
B2. according to a SRAM interface and/or the detected read-write of the 2nd SRAM interface, transmit data in advance to said second and handle accordingly.
6. method according to claim 5 is characterized in that, said step B1 specifically may further comprise the steps:
B11. judge whether second interface is is reading and writing this address through first interface when in advance read-write operation is carried out in the pairing address of transmission data to said first, if, then send busy signal, if not, execution in step B12 then;
B12. judge that this address is read operation or write operation, if write operation, execution in step B13 then is if read operation then directly goes to step B16;
B13. under compose buffer is in idle condition, judge whether this compose buffer exists this address, if, execution in step S141 then, if not, execution in step S142 then;
B141. upgrade the transmission data in advance of said first in this address, step finishes;
B142. check whether this compose buffer is full, if, then send busy signal, step finishes, if not, execution in step B15 then;
B15. treat that transmitting data in advance with said first when bus is idle writes buffer zone, step finishes;
B16. judge whether this compose buffer exists this address, if, then directly go to step S182, if not, execution in step S17 then;
B17. judge whether the space of distributing this address is carrying out read-write operation, if, execution in step S181 then, if not, execution in step S182 then;
B181. read said first in the next read-write cycle and transmit data in advance;
B182. read said first and transmit data in advance.
7. method according to claim 6 is characterized in that, said step B11 is further comprising the steps of:
Judge whether first interface is identical with the pairing address of second interface, if, confirm that according to priority first interface carries out write operation, second interface carries out write operation, still two interfaces are not write, if not, execution in step B12 then.
8. method according to claim 7 is characterized in that, said steps A 2 is further comprising the steps of:
Judge whether a SRAM controller and/or the 2nd SRAM controller are in idle condition.
9. method according to claim 8 is characterized in that, said step B2 specifically may further comprise the steps:
B21. judge whether the pairing SRAM interface in current address has the instruction of operating, if, execution in step B221 then, if not, execution in step B222 then;
B221. behind current EO, said preparatory transmission data are carried out read-write operation;
B222. directly said preparatory transmission data are carried out read-write operation.
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| CN109271333A (en) * | 2017-07-17 | 2019-01-25 | 深圳市中兴微电子技术有限公司 | A kind of SRAM control method and controller, control system |
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Application publication date: 20120704 |