CN102543661A - Wafer manufacturing method - Google Patents
Wafer manufacturing method Download PDFInfo
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- CN102543661A CN102543661A CN2010106051865A CN201010605186A CN102543661A CN 102543661 A CN102543661 A CN 102543661A CN 2010106051865 A CN2010106051865 A CN 2010106051865A CN 201010605186 A CN201010605186 A CN 201010605186A CN 102543661 A CN102543661 A CN 102543661A
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- wafer manufacturing
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Abstract
The invention provides a wafer manufacturing method which comprises the following steps: step 1, growing silicon nitride; step 2, etching a shallow groove and growing silicon nitride; step 3, etching silicon oxide and carrying out chemical mechanical polishing on silicon oxide; and step 4, marking a wafer. Compared with the prior art, the wafer manufacturing method provided by the invention has the beneficial effects of ensuring no wafer scratch, and improving the qualification rate of the wafer.
Description
[technical field]
The present invention relates to a kind of wafer manufacturing method, especially relate to a kind of wafer manufacturing method that can avoid mark to cause wafer to scratch unusually.
[background technology]
Usually, the first step after wafer rolls off the production line is to the wafer mark, just adopts the method for laser (laser) directly over wafer, to get the lot number (like A1234) of wafer, and this lot number is arranged by many apertures and formed.Mark place is caved in, the accessory substance of mark then can be deposited in pit around, form projection; By-product deposit height is 1000～8000nm, and its problem is: the by-product deposit height on next door, mark hole is unstable, in the chemico-mechanical polishing process of lapping of subsequent oxidation silicon; Because the chemico-mechanical polishing of silica is relatively more responsive to the by-product deposit on surface; In case when the height of by-product deposit and hardness were unusual, the chemico-mechanical polishing of silica will fracture the by-product deposit, because the by-product deposit that fractures is harder; So scratch crystal column surface easily, cause wafer loss.
[summary of the invention]
To the deficiency of prior art, the technical problem that the present invention solves provides a kind of wafer manufacturing method, and the wafer that can avoid causing because mark instability or mark deposit are unusual scratches.
The object of the invention is realized through following technical scheme is provided:
A kind of wafer manufacturing method wherein, may further comprise the steps:
The first step, silicon nitride growth;
Second step, shallow trench etching and growth of silicon oxide;
The 3rd step, silica etching and silica chemico-mechanical polishing;
The 4th step, wafer mark.
Alternatively, said mark is a laser marking.
Alternatively, said silica is the HDP silica.
Alternatively, stating silicon nitride is to prepare through chemical gaseous phase depositing process.
Alternatively, said silicon nitride is to prepare through the plasma enhanced chemical vapor deposition method.
Compared with prior art, the invention has the beneficial effects as follows: wafer can not take place scratch, improve the wafer qualification rate.
[description of drawings]
Below in conjunction with accompanying drawing the present invention is described further:
Fig. 1 is the flow chart of wafer manufacturing method of the present invention.
[embodiment]
Following with reference to description of drawings preferred forms of the present invention.
Wafer is meant the silicon wafer that the Si semiconductor production of integrated circuits is used, because it is shaped as circle, so be called wafer; On silicon wafer, can manufacture various circuit element structures, the IC of certain electric sexual function product arranged and become.The original material of wafer is a silicon, and there is nexhaustible silicon dioxide on earth's crust surface.The silicon dioxide ore refines via arc furnace, chlorination of hydrochloric acid, and after distillation, processed high-purity polycrystalline, its purity is up to 99.999999999%.Molten state is melted into to this polysilicon again in wafer manufactory; In this molten state, plant seed crystal again; Then it is slowly pulled out; To form columned monocrystalline silicon crystal bar, because silicon crystal bar is to be generated gradually in the silicon raw material of molten state by the seed crystal that a high preferred orientation is confirmed, this process is called " long brilliant ".Silicon crystal bar passes through segment again, barreling, and section, chamfering, polishing, laser is carved, and after the packing, promptly becomes the base stock of I circuit factory---silicon wafer, and Here it is " wafer ".
In wafer production process, generally comprise silicon nitride growth step, shallow trench etching and HDP growth of silicon oxide step, silica etching and HDP silica chemical-mechanical polishing step, and the mark step.Usually, mark all is to carry out through laser.
Laser marking is to utilize the laser of high-energy-density that workpiece is carried out local irradiation, makes the chemical reaction of skin-material vaporization or generation change color, thereby stays a kind of marking method of permanent marker.Laser marking can be got various literal, symbol and pattern etc., and character boundary can be from the millimeter to the micron dimension, and this has special meaning to product false proof.
The basic principle of laser marking is, generates high-octane continuous laser light beam by laser generator, and when laser action during in printable fabric, the atomic transition that is in ground state is to the higher-energy state; The atom that is in the higher-energy state is unsettled, can get back to ground state very soon, when atom returns ground state; Can discharge extra energy with the form of photon or quantum, and be heat energy, make surfacing moment fusion by transform light energy; Even gasification, thereby form graphic context label.
The laser marking technology is as a kind of modern precision processing method, and with corrosion, spark machined, mechanical scratching, traditional processing method such as printing are compared, and have impayable advantage:
1. adopt laser to do manufacturing process, and do not have the effect of operating force between the workpiece, have contactless, no cutting force, the advantage that thermal impact is little has guaranteed original precision of workpiece.Simultaneously, wider to the adaptability of material, can produce very fine mark on the surface of multiple material and durability very good;
The spatial control property of laser and time controlled fine, to the material of processing object, shape, the degree of freedom of size and processing environment are all very big, are specially adapted to automation processing and special processing.And processing mode is flexible, both can adapt to the needs of the individual event design of testing cell-type, also can satisfy requirement of industrialized batch production;
3. laser grooving and scribing is meticulous, and lines can reach millimeter and arrive micron dimension, and mark imitation and the change of adopting Laser mark technology to make are all very difficult, and be very important to product false proof;
4. laser-processing system combines with computer numerical control technology and can constitute the high-efficient automatic process equipment, can get various literal, symbol and pattern; Be easy to software design marking pattern; The change tag content adapts to the modern production high efficiency, allegro requirement;
5. laser processing is compared with traditional silk screen printing, does not have pollutant sources, is a kind of high environmental protection process technology of cleanliness without any pollution.
Wafer manufacturing method of the present invention may further comprise the steps:
The first step, silicon nitride are grown, and can be used as the barrier layer of follow-up shallow trench etching; In microelectronic, often use chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition methods such as (PECVD) to prepare silicon nitride.Silicon nitride can be used as the required protective layer of etch process in the insulator that blocks different structure or the little processing usually.Silicon nitride also is commonly used in the passivation layer in the microchip, because it is compared with silicon dioxide, hydrone and sodium ion is had the ability that better stops diffusion.And hydrone and sodium ion to be microelectronic two cause the greatly corrosion and the factors of instability.Silicon nitride also is used in the dielectric medium of the inter polysilicon of electric capacity in the analog chip in addition.
Second step, the shallow trench etching and the HDP growth of silicon oxide that leave for the shallow trench isolation of doing between device;
The 3rd step, silica etching and the chemico-mechanical polishing of HDP silica;
The 4th step, wafer mark.
The present invention moves on to the mark step after silica etching and the chemico-mechanical polishing of HDP silica, has avoided the influence of mark step to the chemico-mechanical polishing of silica, can not produce wafer and scratch.
Although be the example purpose; Preferred implementation of the present invention is disclosed; But those of ordinary skill in the art will recognize, under the situation that does not break away from disclosed scope of the present invention and spirit by appending claims, various improvement, increase and replacement are possible.
Claims (5)
1. a wafer manufacturing method is characterized in that, may further comprise the steps:
The first step, silicon nitride growth;
Second step, shallow trench etching and growth of silicon oxide;
The 3rd step, silica etching and silica chemico-mechanical polishing;
The 4th step, wafer mark.
2. wafer manufacturing method according to claim 1 is characterized in that, said mark is a laser marking.
3. wafer manufacturing method according to claim 1 is characterized in that, said silica is the HDP silica.
4. wafer manufacturing method according to claim 1 is characterized in that, said silicon nitride is to prepare through chemical gaseous phase depositing process.
5. wafer manufacturing method according to claim 1 is characterized in that, said silicon nitride is to prepare through the plasma enhanced chemical vapor deposition method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010106051865A CN102543661A (en) | 2010-12-27 | 2010-12-27 | Wafer manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010106051865A CN102543661A (en) | 2010-12-27 | 2010-12-27 | Wafer manufacturing method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN102543661A true CN102543661A (en) | 2012-07-04 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010106051865A Pending CN102543661A (en) | 2010-12-27 | 2010-12-27 | Wafer manufacturing method |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103175495A (en) * | 2013-02-27 | 2013-06-26 | 上海华力微电子有限公司 | Standard silicon dioxide wafer and production method thereof |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW400555B (en) * | 1999-01-16 | 2000-08-01 | United Microelectronics Corp | The manufacturing method of laser mark |
| TW434749B (en) * | 1998-07-08 | 2001-05-16 | Taiwan Semiconductor Mfg | Manufacturing method of wafer marks |
| CN1450592A (en) * | 2002-04-08 | 2003-10-22 | 矽统科技股份有限公司 | Manufacturing method of wafer identification mark |
| US6746966B1 (en) * | 2003-01-28 | 2004-06-08 | Taiwan Semiconductor Manufacturing Company | Method to solve alignment mark blinded issues and a technology for application of semiconductor etching at a tiny area |
| KR20060071995A (en) * | 2004-12-22 | 2006-06-27 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
| US20100224876A1 (en) * | 2009-03-05 | 2010-09-09 | International Business Machines Corporation | Two-Sided Semiconductor Structure |
-
2010
- 2010-12-27 CN CN2010106051865A patent/CN102543661A/en active Pending
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW434749B (en) * | 1998-07-08 | 2001-05-16 | Taiwan Semiconductor Mfg | Manufacturing method of wafer marks |
| TW400555B (en) * | 1999-01-16 | 2000-08-01 | United Microelectronics Corp | The manufacturing method of laser mark |
| CN1450592A (en) * | 2002-04-08 | 2003-10-22 | 矽统科技股份有限公司 | Manufacturing method of wafer identification mark |
| US6746966B1 (en) * | 2003-01-28 | 2004-06-08 | Taiwan Semiconductor Manufacturing Company | Method to solve alignment mark blinded issues and a technology for application of semiconductor etching at a tiny area |
| KR20060071995A (en) * | 2004-12-22 | 2006-06-27 | 주식회사 하이닉스반도체 | Manufacturing method of semiconductor device |
| US20100224876A1 (en) * | 2009-03-05 | 2010-09-09 | International Business Machines Corporation | Two-Sided Semiconductor Structure |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103175495A (en) * | 2013-02-27 | 2013-06-26 | 上海华力微电子有限公司 | Standard silicon dioxide wafer and production method thereof |
| CN103175495B (en) * | 2013-02-27 | 2015-11-25 | 上海华力微电子有限公司 | Standard silicon dioxide wafer and manufacture method thereof |
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Application publication date: 20120704 |