CN102543853B - redundant metal filling method and integrated circuit layout structure - Google Patents

Abstract

The present invention provides a method for filling redundant metals. Several redundant metals are filled in the area that needs to be filled with redundant metals. The plurality of redundant metals include first redundant metal and second redundant metal, each The filling area of each first redundant metal is larger than the filling area of each second redundant metal, and the second redundant metal is located between the first redundant metal and the interconnection line of the region. Correspondingly, the present invention also provides an integrated circuit layout structure. By adopting the method for filling redundant metal of the present invention, the thickness consistency of the integrated circuit layout is achieved while reducing the increase in the capacitance between the interconnecting lines of the integrated circuit, which can ensure that the function of the chip will not be damaged due to the introduction of redundant metal. Filling the redundant metal with different sizes in the area where the redundant metal needs to be filled reduces the amount of redundant metal filling and reduces the amount of other computing data.

Description

Redundant metal filling method and integrated circuit layout structure

technical field

The invention relates to the fields of integrated circuit manufacturing and electronic design automation, in particular to a method for filling redundant metal on an integrated circuit layout and an integrated circuit layout structure.

Background technique

In the integrated circuit (Integrated Circuit, IC) manufacturing process, metals, dielectrics and other materials are fabricated on the surface of silicon wafers by various methods such as physical vapor deposition and chemical vapor deposition to form electronic components and components. The metal structure layer of the metal interconnection line is connected with a plurality of metal-filled through holes between each metal structure layer, so that the integrated circuit has high complexity and circuit density. In the manufacture of each metal structure layer, in order to ensure the flatness of the surface of the metal structure layer, the chemical mechanical polishing (CMP) process is usually used to planarize the metal by means of the chemical corrosion of the polishing liquid and the grinding effect of ultrafine particles. and the surface of the medium layer.

When the integrated circuit process node is reduced below 90nm, especially below 65nm and 45nm, the dependence of the surface flatness after the CMP process on the morphology of the underlying metal is highlighted, and the height change due to the different morphology of the underlying metal can be greater than 30 %. At the same time, the CMP process also brings about changes in the surface morphology of the metal and dielectric layers, forming metal discs and erosion of the dielectric layer. These problems are also related to the line width and line spacing of metal interconnections in the integrated circuit layout. In order to minimize the dependence of the surface flatness of each layer of the circuit on the topography of the underlying metal during the CMP process of the layout, the current general method is to use some areas on the layout of the integrated circuit before the CMP process, such as where the interconnection line density is small A certain distance between the area and the interconnection line is filled with redundant metal, so as to improve the surface flatness of each metal structure layer after the CMP process. The existing redundant metal filling method of integrated circuit foundries is to fill all areas according to the same filling mode, that is, each area is filled with multiple redundant metals with the same shape, size and spacing.

Filling the redundant metal in the integrated circuit, because the extra metal is added between the metal interconnection lines, the capacitance between the interconnection lines increases. The increase of the capacitance between the interconnection lines will affect the signal integrity (Signal Integrity, SI) of the integrated circuit, and then cause the function error of the integrated circuit. With the continuous reduction of integrated circuit process nodes, the electronic components in the circuit are becoming more and more refined, and the impact of redundant metal filling on the capacitance between interconnection lines cannot be ignored. How to carry out redundant metal filling in the actual circuit, so that the thickness of the integrated circuit after the CMP process is as consistent as possible, and how to control the increase in the capacitance between the interconnection lines within an acceptable range has become a key issue. question. However, the existing common method of filling multiple redundant metals with the same shape, size and spacing in each region only considers the thickness consistency after the CMP process, and does not consider the increase in the capacitance between interconnection lines. During the research process, the applicant found that the current common redundant metal filling method can make the capacitance increment between interconnection lines reach a huge percentage, which cannot satisfy the requirement that the capacitance increment between interconnection lines be as small as possible. Require.

Contents of the invention

In order to solve the problem of excessive increase in capacitance between interconnection lines after the integrated circuit is filled with redundant metal, the present invention proposes a method for filling redundant metal in different areas in different areas.

In order to achieve the above object, the present invention provides a redundant metal filling method, comprising steps:

providing an integrated circuit layout to be filled, the integrated circuit layout including at least one metal structure layer;

Determining an area that needs to be filled with redundant metal according to the pattern of each metal structure layer, where interconnect lines are distributed in the area;

The region is filled with a plurality of redundant metals, the plurality of redundant metals include a first redundant metal and a second redundant metal, and the filling area of each of the first redundant metals is larger than that of each of the redundant metals. A filling area of the second redundant metal, the second redundant metal is located between the first redundant metal and the interconnection line.

Correspondingly, the present invention also provides an integrated circuit layout structure, including at least one metal structure layer and several redundant metals, wherein,

The metal structure layer includes a region that needs to be filled with redundant metal, and the region includes interconnection lines;

The plurality of redundant metals are located in the area, the plurality of redundant metals include first redundant metals and second redundant metals, and the filling area of each of the first redundant metals is larger than that of each of the redundant metals. The filling area of the second redundant metal, the second redundant metal is located between the first redundant metal and the interconnection line.

Compared with the prior art, the present invention has the following advantages:

The present invention proposes a redundant metal filling method. The technical solution of the method is to fill a number of redundant metals in the area that needs to be filled with redundant metals, wherein the filling area of the redundant metals close to the interconnection line is smaller than that far away from the same The fill area of redundant metal for interconnect lines. Compared with the prior art, by adopting the redundant metal filling method of the present invention, the thickness consistency of the layout of the integrated circuit is realized, and at the same time, the increase of the capacitance between interconnecting lines of the integrated circuit is reduced. The integrated circuit chip manufactured by the method can ensure that the function of the chip will not be damaged due to the introduction of redundant metal while ensuring the flatness of the chip.

In addition, the method of the present invention fills redundant metals of different sizes in the region where redundant metals need to be filled, thereby reducing the number of redundant metals filled. In the existing method of filling redundant metal, a large amount of redundant metal needs to be filled, which makes the amount of mask data too large and increases the computational burden. Compared with the prior art, the calculation burden of the method of the present invention is less.

Description of drawings

The above and other objects of the present invention are more clearly shown by the accompanying drawings. Like reference numerals designate like parts throughout the drawings. The drawings are not deliberately scaled and drawn according to the actual size, and the emphasis is on illustrating the gist of the present invention.

Fig. 1 is the flowchart of redundant metal filling method of the present invention;

FIG. 2 is a schematic diagram of an area that needs to be filled with redundant metal in an embodiment of the present invention;

Fig. 3 is a schematic diagram of filling redundant metal in an embodiment of the present invention;

Figure 4 is a schematic diagram of filling square redundant metal at a position close to the interconnection line;

FIG. 5 is a schematic diagram of filling rectangular redundant metal at a position far from the interconnection line.

detailed description

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the drawings in the embodiments of the present invention. Apparently, the described embodiments are only some of the embodiments of the present invention, but not all of them. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Secondly, the present invention is described in detail in conjunction with the schematic diagrams. When describing the embodiments of the present invention in detail, for the sake of illustration, the schematic diagrams of the interconnection lines and filling metals in the schematic diagrams will not be partially enlarged according to the general scale, and the schematic diagrams are only examples , which shall not limit the protection scope of the present invention. In the plan view, the square redundant metal means that the area occupied by the redundant metal filling is a square, and the rectangular redundant metal means that the area occupied by the redundant metal filling is a rectangle. After the actual integrated circuit is manufactured, the space filled with the redundant metal is a three-dimensional space, and the cross section of the redundant metal is square or rectangular.

The existing redundant metal filling method of integrated circuit foundries is to fill all areas according to the same filling mode, that is, each area is filled with multiple redundant metals with the same shape, size and spacing. During the research process, the applicant found that the current common method of redundant metal filling increases the capacitance between interconnection lines too much, and sometimes can reach a huge percentage, which cannot meet the requirements of the thickness of the integrated circuit after the CMP process. consistent and the smallest possible increase in capacitance between interconnect lines.

In order to solve the problem of excessive increase in capacitance between interconnection lines after the integrated circuit is filled with redundant metal, the present invention proposes a method for filling redundant metal. The technical solution of the method is to fill several redundant metals, wherein the filled area of the redundant metal close to the interconnection line is smaller than the filled area of the redundant metal far away from the same interconnection line. Compared with the prior art, by adopting the redundant metal filling method of the present invention, the thickness consistency of the layout of the integrated circuit is realized, and at the same time, the increase of the capacitance between interconnecting lines of the integrated circuit is reduced. The integrated circuit chip manufactured by the method can ensure that the function of the chip will not be damaged due to the introduction of redundant metal while ensuring the flatness of the chip.

In addition, the method of the present invention fills redundant metals of different sizes in the region where redundant metals need to be filled, thereby reducing the number of redundant metals filled. In the existing method of filling redundant metal, a large amount of redundant metal needs to be filled, which makes the amount of mask data too large and increases the computational burden. Compared with the prior art, the calculation burden of the method of the present invention is less.

The concrete process of redundant metal filling method of the present invention is shown in Fig. 1, comprises steps:

Step S1, providing an integrated circuit layout to be filled, the integrated circuit layout including at least one metal structure layer.

The integrated circuit layout to be filled may include one or more metal structure layers, and each metal structure layer includes electronic components and metal interconnection lines between the components. The layout of the integrated circuit to be filled may be a layout provided in an electronic design automation file format, especially a layout provided in a GDS format.

Step S2 , according to the pattern of each metal structure layer, determine the area that needs to be filled with redundant metal, and interconnection lines are distributed in the area.

In order to ensure the flatness of the surface of each metal structure layer of the integrated circuit layout after the CMP process, the area to be filled with redundant metal is determined on the pattern of each metal structure layer of the integrated circuit layout to be filled. The area to be filled with redundant metal is usually an area with low interconnect line density, or the simulation results of simulation tools such as CMP simulation tools show metal dishing, dielectric layer erosion, or hot spots with large surface height differences.

An interconnection line may be distributed in the middle of the determined area that needs to be filled with redundant metal, or one or more interconnection lines may be distributed at the edge.

In practice, there are many ways to determine the area that needs to be filled with redundant metal. It can be determined according to the interconnection line density of the integrated circuit layout, or it can be determined according to the thickness difference of the interconnection line after the CMP process of the integrated circuit layout, or it can be determined according to the integrated circuit layout. The design rules of the circuit foundry are determined.

Step S3, filling the area with a plurality of redundant metals, the plurality of redundant metals at least including a first redundant metal and a second redundant metal, each filling area of the first redundant metal Greater than the filling area of each of the second redundant metals, the second redundant metals are located between the first redundant metals and the interconnection lines.

In order to ensure the smoothness of the surface of each metal structure layer of the integrated circuit layout after the CMP process and to ensure that the capacitance increase between the interconnection lines is small, multiple redundant metals are filled in the area that needs to be filled with redundant metals. , filling the first redundant metal with a larger area at a position farther away from the interconnection line, and filling the second redundant metal with a smaller area at a position closer to the interconnection line.

The redundant metal filling method of the present invention will be described in detail below with an embodiment in conjunction with the accompanying drawings:

First, an integrated circuit layout to be filled is provided in GDS format, the integrated circuit layout including a metal structure layer.

It is determined that the area to be filled with redundant metal in the layout of the integrated circuit is the area where the difference between the equivalent thickness of the interconnection line and the deposition thickness of the interconnection line is large, and the equivalent thickness of the interconnection line and the deposition thickness of the interconnection line can be given in advance. The setting range of the thickness difference can be preferably filled with redundant metal in the area where the difference between the equivalent thickness of the interconnection line and the deposition thickness of the interconnection line to be filled in the integrated circuit layout is greater than 10%. The specific process of determining the equivalent thickness of the interconnection line is as follows :

First, the layout of the integrated circuit to be filled is divided into grids, and the equivalent line width and equivalent spacing of the interconnection lines in each grid are obtained, where

The equivalent line width can be calculated by weighted average

${\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; eff</span>}}<span\; class="notranslate">\; =</span>\underset{\mathrm{<span\; class="notranslate">\; i</span>}}{\mathrm{<span\; class="notranslate">\; \&Sigma;</span>}}{\mathrm{<span\; class="notranslate">\; A</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; i</span>}}$

Among them, W _eff is the equivalent line width, W _i is the line width of a certain interconnect line contained in the grid, and A _i is the area occupied by the interconnect line with line width W _i in the interconnect line area of the grid area ratio.

The equivalent spacing can be calculated using the following formula:

${\mathrm{<span\; class="notranslate">\; S</span>}}_{\mathrm{<span\; class="notranslate">\; eff</span>}}<span\; class="notranslate">\; =</span>\frac{\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&rho;</span>}}{\mathrm{<span\; class="notranslate">\; \&rho;</span>}}{\mathrm{<span\; class="notranslate">\; W</span>}}_{\mathrm{<span\; class="notranslate">\; eff</span>}}$

Among them, S _eff is the equivalent line spacing, and ρ is the proportion of the interconnection area in the grid to the total area.

Secondly, according to the chemical mechanical polishing process parameters of the integrated circuit layout and the equivalent line width and equivalent spacing of the interconnection lines in the grid, the metal dishing amount and dielectric erosion amount of the grid are obtained;

The chemical mechanical polishing process parameters of the integrated circuit layout include the processing time of the chemical mechanical polishing process, the metal removal rate of the interconnection line, the removal rate of the dielectric layer, and the like.

The metal disc shape D _M can be calculated by the following formula:

D _M ＝D _ss (1-e ^-t/τ )

The amount of medium erosion E _OX can be calculated by the following formula:

E _OX ＝Y ₁ t+Y ₂ D _ss (e ^-t/τ -1)

in,

${\mathrm{<span\; class="notranslate">\; Y</span>}}_{\mathrm{<span\; class="notranslate">\; 1</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; OX</span>}}}{{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&rho;</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; OX</span>}}\mathrm{<span\; class="notranslate">\; \&rho;</span>}}<span\; class="notranslate">\; ,</span>$

${\mathrm{<span\; class="notranslate">\; Y</span>}}_{\mathrm{<span\; class="notranslate">\; 2</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; OX</span>}}\mathrm{<span\; class="notranslate">\; \&rho;</span>}}{{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&rho;</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; OX</span>}}\mathrm{<span\; class="notranslate">\; \&rho;</span>}}<span\; class="notranslate">\; ,</span>$

$\mathrm{<span\; class="notranslate">\; \&tau;</span>}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; d</span>}}_{\mathrm{<span\; class="notranslate">\; max</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&rho;</span>}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&rho;</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; OX</span>}}\mathrm{<span\; class="notranslate">\; \&rho;</span>}}<span\; class="notranslate">\; ,</span>$

${\mathrm{<span\; class="notranslate">\; D.</span>}}_{\mathrm{<span\; class="notranslate">\; SS</span>}}<span\; class="notranslate">\; =</span>\frac{{\mathrm{<span\; class="notranslate">\; d</span>}}_{\mathrm{<span\; class="notranslate">\; max</span>}}<span\; class="notranslate">\; (</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; -</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; OX</span>}}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&rho;</span>}<span\; class="notranslate">\; )</span>}{{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; m</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; 1</span>}<span\; class="notranslate">\; -</span>\mathrm{<span\; class="notranslate">\; \&rho;</span>}<span\; class="notranslate">\; )</span><span\; class="notranslate">\; +</span>{\mathrm{<span\; class="notranslate">\; r</span>}}_{\mathrm{<span\; class="notranslate">\; OX</span>}}\mathrm{<span\; class="notranslate">\; \&rho;</span>}}<span\; class="notranslate">\; ,</span>$

d _max ＝A×(W _eff ) ^α ×(S _eff ) ^β

Among them, t is the processing time of the CMP process, r _M is the metal removal rate of the interconnection, r _ox is the removal rate of the dielectric layer, d _max is the maximum disc shape of the interconnection metal, and A, α, β are fitting parameters.

Finally, the equivalent thickness of the interconnection line of the grid is extracted, and the equivalent thickness of the interconnection line of the grid is equal to the deposition thickness minus the amount of metal dishing and the amount of dielectric erosion. Wherein, the deposition thickness is the design target thickness of the interconnection line during the manufacture of the integrated circuit layout.

The above-mentioned method of extracting the equivalent thickness of the grid interconnection line takes into account the influence of the circuit pattern in the layout of the integrated circuit and the bottom metal morphology on the thickness of the metal interconnection line, and also considers the possible occurrence of metal dishing and dielectric layer erosion on the integrated circuit. The influence of the thickness of the metal interconnection in the layout can obtain a more accurate equivalent thickness of the interconnection.

In this way, it can be obtained that the difference between the equivalent thickness of the interconnection line and the deposition thickness in which areas of the layout of the integrated circuit to be filled after the CMP process is relatively large.

Referring to Figure 2, it is a region where the difference between the equivalent thickness of the interconnection line determined according to the above method and the deposition thickness of the interconnection line to be filled in the integrated circuit layout after the CMP process is large, and the edge of this region includes two Interconnects 100, the middle of the region, ie, spaces 200 between interconnects (shown in dotted boxes), are locations where redundant metal is filled.

In this embodiment, two groups of redundant metals with different areas are filled in the area shown in FIG. Redundant metal 301, each rectangular redundant metal has a side length of 2.4 μm and a width of 0.8 μm, and the length direction of each redundant metal is along the length direction of the interconnection line 100; the second group of 24 square redundant metals 302 , the side length of each redundant metal square is 0.2 μm, and the shortest distance between the redundant metal square 302 and the interconnection line 100 may be 0.14 μm to 0.35 μm. The first set of redundant metal is basically in the middle of two interconnect lines, the second set of 12 squares of redundant metal is located between the first set of redundant metal and an interconnect line, and the second set of another 12 squares The redundant metal is located between the redundant metal of the first set and another interconnection line.

In a conventional redundant metal filling method, multiple redundant metal squares are filled in the area of the integrated circuit layout where redundant metal needs to be filled, for example, the side length of each redundant metal square is 0.8 μm. The solution of the present invention is to fill redundant metal with a smaller area at a position closer to the interconnection line. In order to reduce the amount of redundant metal filling and reduce other calculations, the filling area at a position farther from the interconnection line is larger. For example, a square redundant metal with a side length of 0.2 μm is filled at a position closer to the interconnection line, and a rectangular redundant metal with a length of 2.4 μm and a width of 0.8 μm is filled at a distance from the interconnection line. s position. In order to test the influence of the method of the present invention on the inter-interconnect capacitance, the applicant measured the inter-interconnect capacitance of redundant metals with different filling areas in different regions. Referring to Fig. 4, in the area 210 close to the interconnection line 110, fill the square redundant metal with the same side length, fill the squares with side lengths of 0.8 μm and 0.2 μm respectively, and measure the interconnection line after CMP and other manufacturing processes The capacitance between 110, Table 1 lists the amount of dielectric erosion, the amount of metal disc shape, and the capacitance between interconnection lines after filling the redundant metal of different side lengths. Among them, except for the size of the redundant metal filled , other conditions are the same.

Table 1. Capacitance between interconnect lines when filling square redundant metal with different side lengths

It can be seen from Table 1 that the square redundant metal with a small side length is filled at a position close to the interconnection line, and other conditions for manufacturing integrated circuits are the same. The measurement shows that the square redundant metal with a side length of 0.2 μm The capacitance between the interconnect lines when the metal is left is about 35% smaller than that of the square redundant metal with a filling side length of 0.8 μm.

Referring to Fig. 5, in the space 220 that needs to be filled with redundant metal between the interconnection line 120 and the area farther away from the interconnection line, a rectangular 320 redundant metal or a square redundant metal is filled, and after a manufacturing process such as CMP, the measurement For the capacitance between interconnection lines 120, Table 2 lists the amount of dielectric erosion, the amount of metal disc shape, and the capacitance between interconnection lines after filling rectangular or square redundant metals. Among them, except for the shape of redundant metal filling Other conditions are the same.

Table 2. Capacitance between interconnect lines when filling redundant metal with different shapes

It can be seen from Table 2 that the other conditions for manufacturing integrated circuits are the same when filling a square redundant metal with a side length of 0.8 μm or a rectangle with a length of 2.4 μm and a width of 0.8 μm at a position far from the interconnection line. It is measured that the capacitance between the interconnection lines when filling the rectangular redundant metal with a length of 2.4 μm and a width of 0.8 μm is about 4% smaller than that of a square redundant metal with a side length of 0.8 μm.

Based on the test results in Table 1 and Table 2, the present invention selects a smaller square redundant metal to fill the position closer to the interconnection line, and fills a larger rectangle with a larger side length at a position farther from the interconnection line. Redundant metal can reduce the capacitance increase between interconnect lines, and at the same time can reduce the amount of redundant metal filling, and reduce the amount of computing data such as masks.

In this embodiment, the redundant metal is filled in an area including two interconnection lines, and multiple second redundant metals are filled on both sides of the first redundant metal. In practice, there are many situations where redundant metal needs to be filled at the edge including interconnect lines. If there is only one interconnect line at the edge of the area where redundant metal needs to be filled, the second redundant metal is located between the first redundant metal and the interconnect. between the lines.

Correspondingly, the present invention also provides an integrated circuit layout structure, which includes at least one metal structure layer and several redundant metals, wherein,

The metal structure layer includes a region that needs to be filled with redundant metal, and the region includes interconnection lines;

The plurality of redundant metals are located in the area, the plurality of redundant metals include first redundant metals and second redundant metals, and the filling area of each of the first redundant metals is larger than that of each of the redundant metals. The filling area of the second redundant metal, the second redundant metal is located between the first redundant metal and the interconnection line.

The metal structure layer is a basic structure for realizing integrated circuit functions, including electronic components and metal interconnection lines between components. The purpose of the redundant metal is to reduce as much as possible the dependence of the flatness of the circuit surface of each layer on the morphology of the underlying metal during the CMP process of the metal structure layer.

Preferably, a plurality of interconnection lines are distributed on the edge of the area that needs to be filled with redundant metal, and the middle of the area includes one first redundant metal and a plurality of second redundant metals with equal areas, and the first redundant metal The second redundant metal is included between a redundant metal and each interconnection line.

Preferably, a plurality of interconnection lines are distributed on the edge of the region that needs to be filled with redundant metal, and the middle of the region includes a plurality of first redundant metals with equal areas and a plurality of second redundant metals with equal areas. For redundant metal, the second redundant metal with equal area is included between each first redundant metal with equal area and each interconnection line.

Preferably, an interconnection line is distributed on the edge of the area that needs to be filled with redundant metal, and the middle of the area includes one first redundant metal and a plurality of second redundant metals with equal areas, the A plurality of second redundant metals having equal areas are located between the first redundant metal and the one interconnection line.

Preferably, the area where the redundant metal needs to be filled includes a rectangular first redundant metal and/or a square second redundant metal.

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the content of the technical solution of the present invention, still belong to the scope of protection of the technical solution of the present invention.

Claims (5)

1. A redundant metal filling method, characterized in that, comprising steps: providing an integrated circuit layout to be filled, the integrated circuit layout including at least one metal structure layer; Determining an area that needs to be filled with redundant metal according to the pattern of each metal structure layer, where interconnect lines are distributed in the area; The region is filled with a plurality of redundant metals, the plurality of redundant metals include a first redundant metal and a second redundant metal, and the filling area of each of the first redundant metals is larger than that of each of the redundant metals. a filling area of a second redundant metal, the second redundant metal being located between the first redundant metal and the interconnect; Wherein, according to the pattern of each metal structure layer, it is determined that the area where the difference between the equivalent thickness of the interconnection line and the deposition thickness is greater than the set value is the area that needs to be filled with redundant metal; the equivalent thickness of the interconnection line is equal to the deposition thickness. The thickness minus the amount of metal disc shape and then minus the amount of dielectric erosion, wherein, the deposition thickness is the design target thickness of the interconnection line when the integrated circuit layout is manufactured. 2. The redundant metal filling method according to claim 1, wherein a plurality of interconnect lines are distributed on the edge of the region, and one first redundant metal and a plurality of interconnect lines are filled in the middle of the region. A second redundant metal having an equal area, including the second redundant metal between the first redundant metal and each interconnection line. 3. The redundant metal filling method according to claim 1, wherein a plurality of interconnection lines are distributed on the edge of the region, and a plurality of first redundant metals with equal areas are filled in the middle of the region. A metal and a plurality of second redundant metals with equal areas, each of the first redundant metals with equal areas and each interconnection line includes the second redundant metals with equal areas. 4. The redundant metal filling method according to claim 1, wherein an interconnection line is distributed on the edge of the region, and a first redundant metal and a plurality of areas are filled in the middle of the region The second redundant metals are equal, and the plurality of second redundant metals with equal areas are located between the first redundant metal and the one interconnection line. 5. The redundant metal filling method according to any one of claims 1 to 4, wherein the rectangular first redundant metal and/or the square second redundant metal are filled in the region.