CN102543991B - Electrostatic protection device - Google Patents
Electrostatic protection device Download PDFInfo
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- CN102543991B CN102543991B CN201010593664.5A CN201010593664A CN102543991B CN 102543991 B CN102543991 B CN 102543991B CN 201010593664 A CN201010593664 A CN 201010593664A CN 102543991 B CN102543991 B CN 102543991B
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- 238000009792 diffusion process Methods 0.000 claims abstract description 190
- 230000003068 static effect Effects 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 description 26
- 230000015572 biosynthetic process Effects 0.000 description 8
- 239000012535 impurity Substances 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 2
- 230000024241 parasitism Effects 0.000 description 2
- 238000011144 upstream manufacturing Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
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Abstract
The invention discloses an electrostatic protection device, which comprises an N well and a P well which are adjacent to each other. A first P+ diffusion region, a second P+ diffusion region and a first N+ diffusion region are formed in the N well, and a third P+ diffusion region, a fourth P+ diffusion region and a third N+ diffusion region are formed in the P well. The first P+ diffusion region, the second P+ diffusion region and the first N+ diffusion region form a PNP (positive-negative-positive) transistor or a PMOS (positive channel metal oxide semiconductor) transistor, and the first P+ diffusion region and the first N+ diffusion region which are in short circuit are connected with an electrostatic terminal. The third P+ diffusion region in the P well is the nearest to the N well, the third N+ diffusion region is the second nearest to the N well, and the fourth P+ diffusion region is farthest away from the N well, the third P+ diffusion region and the third N+ diffusion region which are in short circuit are connected with an earth terminal, and the fourth P+ diffusion region and the second P+ diffusion region in the N well are in short circuit. The electrostatic protection device is low in trigger voltage and high in snapback voltage.
Description
Technical field
The present invention relates to semiconductor electrostatic resist technology, particularly a kind of electrostatic protection device.
Background technology
As electrostatic protection device; triode parasitic in thyristor (SCR) has stronger electrostatic leakage ability than Metal-oxide-semicondutor field effect transistor (MOSFET), and the electrostatic leakage ability of general thyristor is 5～7 times of MOSFET.Figure 1 shows that the cross-sectional view of existing high trigger voltage thyristor.In Fig. 1, the collector electrode of the parasitic PNP pipe Vbp that P+/high pressure N trap/high pressure P trap forms is also the base stage of the parasitic NPN pipe Vbn of N+/high pressure P trap/high pressure N trap formation simultaneously; Equally, the collector electrode of the parasitic NPN pipe Vbn that N+/high pressure P trap/high pressure N trap forms is also the base stage of the parasitic PNP pipe Vbp of P+/high pressure N trap/high pressure P trap formation.The equivalent electric circuit that parasitic NPN pipe Vbn in Fig. 1 and PNP pipe Vbp form as shown in Figure 2.From Fig. 1 and Fig. 2, can find out, the trigger voltage of the thyristor that the parasitic NPN pipe Vbn that the parasitic PNP pipe Vbp being formed by P+/high pressure N trap/high pressure P trap and N+/high pressure P trap/high pressure N trap form forms is jointly the reverse breakdown voltage of high pressure N trap/high pressure P trap.Conventionally the reverse breakdown voltage of high pressure N trap/high pressure P trap knot is higher, and therefore, the application of this structure is limited by very large.In addition, because parasitic NPN pipe and PNP after thyristor unlatching itself manage, mutually realize the positive feedback that electric current amplifies, cause its conducting resistance very low, multiplication factor is very large, and the voltage that maintains occurring after suddenly returning will be very low, generally between 2～5V.And the normal working voltage of high-tension circuit is far away on this, therefore use thyristor to do high-pressure electrostatic protective circuit, also easily cause latch-up, and be difficult for recovering.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of electrostatic protection device, and trigger voltage is low, and the rapid pressure of wiring back is high.
For solving the problems of the technologies described above, electrostatic protection device of the present invention, comprises an adjacent N trap
With a P trap;
In described N trap, be formed with a P+ diffusion region, the 2nd P+ diffusion region, a N+ diffusion region;
In described P trap, be formed with the 3rd P+ diffusion region, the 4th P+ diffusion region, the 3rd N+ diffusion region;
A P+ diffusion region in described N trap, the 2nd P+ diffusion region, a N+ diffusion region form a PNP transistor or PMOS pipe, and a described P+ diffusion region and a N+ diffusion region short circuit are used for connecing static end;
The 3rd P+ diffusion region in described P trap, the 4th P+ diffusion region, the 3rd N+ diffusion region, the 3rd P+ diffusion region is nearest apart from N trap, take second place in the 3rd N+ diffusion region, the 4th P+ diffusion region apart from N trap farthest, the 3rd P+ diffusion region and the 3rd N+ diffusion region short circuit are for earth terminal, the 2nd P+ diffusion region short circuit in the 4th P+ diffusion region and N trap.
In N trap, be also formed with the 2nd N+ diffusion region, the 2nd N+ diffusion region distance P trap is near compared with a P+ diffusion region, the 2nd P+ diffusion region, a N+ diffusion region, and the 2nd N+ diffusion region is with a P+ diffusion region and a N+ diffusion region short circuit.
When the P+ diffusion region in described N trap, the 2nd P+ diffusion region, a N+ diffusion region form a PNP transistor, the one P+ diffusion region is as the transistorized emitter of this PNP, the 2nd P+ diffusion region is as the transistorized emitter collector electrode of this PNP, and a N+ diffusion region is as the transistorized base stage of this PNP.
When the P+ diffusion region in described N trap, the 2nd P+ diffusion region, a N+ diffusion region form a PMOS pipe, the one P+ diffusion region, the 2nd P+ diffusion region are respectively as source, the drain electrode of this PMOS pipe, the one N+ diffusion region is as the substrate terminal of this PMOS pipe, top, channel region between the one P+ diffusion region, the 2nd P+ diffusion region is formed with the grid of this PMOS pipe, and the grid of this PMOS pipe is with a P+ diffusion region and a N+ diffusion region short circuit.
The 2nd N+ diffusion region is dark compared with a N+ diffusion region, the 3rd N+ diffusion region.
The 3rd P+ diffusion region is dark compared with a P+ diffusion region, the 2nd P+ diffusion region, the 4th P+ diffusion region.
Electrostatic protection device of the present invention; on the basis of existing thyristor (SCR) structure; increase a parasitic PNP pipe for triggering; the triggering of electrostatic protection device is opened and is controlled by parasitic PNP; the unlatching of parasitic PNP pipe formation electric current flows in P trap thus, improves the current potential of P trap, triggers thus the NPN transistor unlatching that the N+ diffusion region in the N+ diffusion region/P trap/P trap in N trap forms; carry out electrostatic induced current bleed off, trigger voltage is low and be convenient to regulate.Electrostatic protection device of the present invention; can also in N trap, the side near P trap add a N+ diffusion region to be connected to static upstream end; and in P trap near a side of N trap add one P+ diffusion region be connected to and hold; with this, reduced the electric current amplifying power after the parasitic PNP pipe Vbp of P+/NW/PW formation and the parasitic NPN pipe Vbn unlatching of N+/PW/NW formation; can effectively improve rapid telegram in reply and press, prevent from solving electrostatic preventing structure and due to rapid time brownout, easily cause fastening the problem of lock effect.
Accompanying drawing explanation
Below in conjunction with the drawings and the specific embodiments, the present invention is described in further detail.
Fig. 1 is the cross-sectional view of common thyristor
Fig. 2 is the parasitic NPN of the thyristor in Fig. 1 and the equivalent circuit diagram that PNP pipe forms;
Fig. 3 is that electrostatic protection device of the present invention is realized the schematic diagram that triggers parasitic PNP pipe with PNP;
Fig. 4 is that electrostatic protection device of the present invention is realized the schematic diagram that triggers parasitic PNP pipe with PMOS;
Fig. 5 is the equivalent electric circuit of the electrostatic protection device shown in Fig. 3, Fig. 4.
Embodiment
Electrostatic protection device one execution mode of the present invention as shown in Figure 3, Figure 4, comprises adjacent a N trap and a P trap;
In described N trap, be formed with a P+ diffusion region, the 2nd P+ diffusion region, a N+ diffusion region, the 2nd N+ diffusion region, the 2nd N+ diffusion region distance P trap is near compared with a P+ diffusion region, the 2nd P+ diffusion region, a N+ diffusion region;
A P+ diffusion region in described N trap, the 2nd P+ diffusion region, a N+ diffusion region form a PNP transistor (shown in Fig. 3) or PMOS pipe (shown in Fig. 4), and a described P+ diffusion region, a N+ diffusion region and the 2nd N+ diffusion region short circuit are used for connecing static end; When the P+ diffusion region in N trap, the 2nd P+ diffusion region, a N+ diffusion region form a PNP transistor as shown in Figure 3, the one P+ diffusion region is as the transistorized emitter of this PNP, the 2nd P+ diffusion region as the transistorized emitter collector electrode of this PNP, a N+ diffusion region as the transistorized base stage of this PNP; A P+ diffusion region in described N trap, the 2nd P+ diffusion region, a N+ diffusion region form a PMOS pipe, the one P+ diffusion region, the 2nd P+ diffusion region are respectively as source, the drain electrode of this PMOS pipe, the one N+ diffusion region is as the substrate terminal of this PMOS pipe, top, channel region between the one P+ diffusion region, the 2nd P+ diffusion region is formed with the grid of this PMOS pipe, and the grid of this PMOS pipe is with a P+ diffusion region and a N+ diffusion region short circuit;
In described P trap, be formed with the 3rd P+ diffusion region, the 4th P+ diffusion region, the 3rd N+ diffusion region, the 3rd P+ diffusion region is nearest apart from N trap, takes second place in the 3rd N+ diffusion region, and the 4th P+ diffusion region apart from N trap farthest;
The 3rd P+ diffusion region in described P trap and the 3rd N+ diffusion region short circuit are for earth terminal, and the 4th P+ diffusion region is with the 2nd P+ diffusion region short circuit in N trap;
A N-type impurity is injected in the 2nd N+ diffusion region, thereby makes the 2nd N+ diffusion region dark compared with a N+ diffusion region, the 3rd N+ diffusion region;
A p type impurity is injected in the 3rd P+ diffusion region, thereby makes the 3rd P+ diffusion region dark compared with a P+ diffusion region, the 2nd P+ diffusion region, the 4th P+ diffusion region.
The equivalent electric circuit of the electrostatic protection device shown in Fig. 3, Fig. 4 as shown in Figure 5.
Electrostatic protection device of the present invention; on the basis of existing silicon-controlled rectifier structure; increase a parasitic PNP pipe for triggering; the triggering of electrostatic protection device is opened and is controlled by parasitic PNP; the unlatching of parasitic PNP pipe formation electric current flows in P trap thus, improves the current potential of P trap, triggers thus the NPN transistor unlatching that the N+ diffusion region in the N+ diffusion region/P trap/P trap in N trap forms; carry out electrostatic induced current bleed off, trigger voltage is low and be convenient to regulate.For the parasitic PNP pipe triggering, available PNP realizes, the PNP transistor being formed by its P+ diffusion region/N trap/P+ diffusion region that this PNP pipe itself is parasitic, total identical emitter and the base stage of PNP transistor forming with P+ diffusion region/N trap/P trap of thyristor parasitism, the base stage of this PNP pipe and emitter are connected to static end, and collector electrode is connected with the P+ diffusion region in P trap; For the parasitic PNP pipe triggering, also available PMOS realizes, the PNP transistor being formed by its source electrode P+ diffusion region/N trap/drain electrode P+ diffusion region that this PMOS pipe itself is parasitic, total identical emitter and the base stage of PNP transistor forming with P+ diffusion region/N trap/P trap of thyristor parasitism, the source electrode of this PMOS pipe, grid are connected to static end with together with N+ diffusion region in N trap, and drain electrode is connected with the P+ diffusion region in P trap.
Electrostatic protection device of the present invention; can also in N trap, the side near P trap add a N+ diffusion region to be connected to static upstream end; and in P trap near a side of N trap add one P+ diffusion region be connected to and hold; with this, reduced the electric current amplifying power after the parasitic PNP pipe Vbp of P+/NW/PW formation and the parasitic NPN pipe Vbn unlatching of N+/PW/NW formation; can effectively improve rapid telegram in reply and press, prevent because the rapid brownout that returns causes fastening lock effect.Can inject in described P+ diffusion region p type impurity, in described N+ diffusion region, inject a N-type impurity and strengthen and improve the rapid effect of wiring back and pressing.Electrostatic protection device of the present invention can be used for CMOS or BCD technique.
Claims (5)
1. an electrostatic protection device, comprises adjacent a N trap and a P trap, it is characterized in that,
In described N trap, be formed with a P+ diffusion region, the 2nd P+ diffusion region, a N+ diffusion region;
In described P trap, be formed with the 3rd P+ diffusion region, the 4th P+ diffusion region, the 3rd N+ diffusion region;
A P+ diffusion region in described N trap, the 2nd P+ diffusion region, a N+ diffusion region form a PNP transistor or PMOS pipe, and a described P+ diffusion region and a N+ diffusion region short circuit are used for connecing static end;
The 3rd P+ diffusion region in described P trap, the 4th P+ diffusion region, the 3rd N+ diffusion region, the 3rd P+ diffusion region is nearest apart from N trap, take second place in the 3rd N+ diffusion region, the 4th P+ diffusion region apart from N trap farthest, the 3rd P+ diffusion region and the 3rd N+ diffusion region short circuit are for earth terminal, the 2nd P+ diffusion region short circuit in the 4th P+ diffusion region and N trap;
In N trap, be also formed with the 2nd N+ diffusion region, the 2nd N+ diffusion region distance P trap is near compared with a P+ diffusion region, the 2nd P+ diffusion region, a N+ diffusion region, and the 2nd N+ diffusion region is with a P+ diffusion region and a N+ diffusion region short circuit.
2. electrostatic protection device according to claim 1; it is characterized in that; a P+ diffusion region in described N trap, the 2nd P+ diffusion region, a N+ diffusion region form a PNP transistor; the one P+ diffusion region is as the transistorized emitter of this PNP; the 2nd P+ diffusion region is as the transistorized emitter collector electrode of this PNP, and a N+ diffusion region is as the transistorized base stage of this PNP.
3. electrostatic protection device according to claim 1; it is characterized in that; a P+ diffusion region in described N trap, the 2nd P+ diffusion region, a N+ diffusion region form a PMOS pipe; the one P+ diffusion region, the 2nd P+ diffusion region are respectively as source, the drain electrode of this PMOS pipe; the one N+ diffusion region is as the substrate terminal of this PMOS pipe; top, channel region between the one P+ diffusion region, the 2nd P+ diffusion region is formed with the grid of this PMOS pipe, and the grid of this PMOS pipe is with a P+ diffusion region and a N+ diffusion region short circuit.
4. electrostatic protection device according to claim 1, is characterized in that, the 2nd N+ diffusion region is dark compared with a N+ diffusion region, the 3rd N+ diffusion region.
5. electrostatic protection device according to claim 1, is characterized in that, the 3rd P+ diffusion region is dark compared with a P+ diffusion region, the 2nd P+ diffusion region, the 4th P+ diffusion region.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201010593664.5A CN102543991B (en) | 2010-12-17 | 2010-12-17 | Electrostatic protection device |
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|---|---|---|---|
| CN201010593664.5A CN102543991B (en) | 2010-12-17 | 2010-12-17 | Electrostatic protection device |
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| CN102543991A CN102543991A (en) | 2012-07-04 |
| CN102543991B true CN102543991B (en) | 2014-04-16 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101452913A (en) * | 2007-12-03 | 2009-06-10 | 上海华虹Nec电子有限公司 | Device structure using silicon controlled rectifier as electrostatic protection |
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| US7825473B2 (en) * | 2005-07-21 | 2010-11-02 | Industrial Technology Research Institute | Initial-on SCR device for on-chip ESD protection |
| US7834378B2 (en) * | 2007-08-28 | 2010-11-16 | Fairchild Korea Semiconductor Ltd | SCR controlled by the power bias |
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| CN101452913A (en) * | 2007-12-03 | 2009-06-10 | 上海华虹Nec电子有限公司 | Device structure using silicon controlled rectifier as electrostatic protection |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140108 |
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Effective date of registration: 20140108 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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