CN102568573B - Micro electro mechanical system (MEMS) nonvolatile memory and memory units - Google Patents
Micro electro mechanical system (MEMS) nonvolatile memory and memory units Download PDFInfo
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Abstract
Provided are a micro electro mechanical system (MEMS) nonvolatile memory and memory units. The MEMS nonvolatile memory comprises a memory array formed by a plurality of memory units, a row decoder connected with row gate lines of the memory array and used for conducting row decoding, a column decoder connected with column gate lines of the memory array and used for conducting column decoding and a read-write unit used for controlling the read-write state of each gate line in the memory array. One or a plurality of the memory units, the row decoder, the column decoder and the read-write control unit comprise at least one MEMS switch device. The MEMS switch device comprises a first end, a second end, a third end and a control end, and the control end is used for controlling electric communication of one of the third end, the first end and the second end. The MEMS nonvolatile memory and the memory units improve response speed, reduce programming voltage and prolong service life.
Description
Technical field
The present invention relates to memory area, particularly a kind of MEMS nonvolatile memory and storage unit.
Background technology
Along with the development of infotech, various storeies have obtained using widely in electronic equipment.According to the difference of the principle of storer and structure, storer can be divided into static memory (SRAM), dynamic storage (DRAM), flash memory (Flash), ROM (read-only memory) (ROM), EEPROM (Electrically Erasable Programmable Read Only Memo) (EEPROM) etc., wherein, EEPROM has nonvolatile feature, the data that are its storage inside after power down can't be lost, but also can repeatedly carry out eaily erasable, there is in addition higher read-write speed, therefore be widely used in various portable sets, for storing starting up's program and configuration data etc.
Fig. 1 shows the structural representation of a kind of storer of prior art, comprise: storage array 10, line decoder 11, column decoder 12 and read-write control unit 13, wherein, storage array 10 comprises the storage unit of a plurality of one-tenth array arrangements, each storage unit can be stored the data of a bit (bit), storage unit with a line is shared with a line select lines, and the storage unit of same row is shared same row select lines and bit line; Line decoder 11 connects each row select lines, for carrying out row decoding, each row select lines in described storage array is carried out to row gating; Column decoder 12 connects each row select lines, for carrying out column decoding, each row select lines in described storage array is carried out to column selection logical; Read-write control unit 13, controls for the read-write state of each storage unit of storage array 10.
Fig. 2 shows a kind of structural representation of the line decoder 11 shown in Fig. 1, Fig. 2 is only example, wherein row address is 2 (A0 and A1), row select lines has 4 (WL0 to WL3), by the decoding to row address, make in row select lines one for logic high, other be logic low, the truth table after decoding is as shown below:
| A1 | A0 | WL0 | WL1 | WL2 | WL3 |
| 0 | 0 | 1 | 0 | 0 | 0 |
| 0 | 1 | 0 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 | 1 | 0 |
| 1 | 1 | 0 | 0 | 0 | 1 |
In addition, structure and the line decoder in Fig. 2 of the column decoder 12 in Fig. 1 are similar, are only that row address is replaced to column address, and row select lines replaces to row select lines.
Fig. 3 shows the read-write control unit of prior art and the syndeton of storage unit 14, described read-write control unit comprises row gating unit 15 and read-write gating unit 13, wherein, described row gating unit 15 comprises a nmos pass transistor, when the described storage unit 14 affiliated row select lines BL gating (logic high) being listed as, between storage unit 14 and read-write gating unit 13, by described row gating unit 15, electrically conduct, can carry out read operation or write operation to storage unit 14, otherwise this path disconnects, and can not carry out read/write operation to described storage unit 14; Described read-write gating unit 13 is according to chip selection signal
and read-write control signal
the read operation path of described storage unit 14 and write operation path are carried out to gating, carry out read operation or write operation, when described chip selection signal
be 0 (being selected state), described read-write control signal
while being 1 (being read operation), transmission gate 134 is subject to the output signal of described logic gate 132 control and electrically conduct, data in storage unit 14 export input and output pin I/O to by row gating unit 15 and transmission gate 134, complete read operation, when described chip selection signal
be 0, read-write control signal
be 0 o'clock, transmission gate 133 is subject to the output signal of described logic gate 131 control and electrically conduct, and input and output pin I/O carries out write operation by described transmission gate 133 and 15 pairs of described storage unit 14 of row gating unit.
In the storer of prior art, storage unit is used MOS transistor to realize, its manufacture craft is generally used the CMOS technique of standard, and corresponding line decoder, column decoder and read-write control unit are also all used MOS transistor to realize, and its manufacture craft is also the CMOS technique of standard.The EEPROM of take in nonvolatile memory is example, its storage unit is used floating boom tunnel oxidation layer MOS transistor (FLOTOX, Floating Gate Tunnel Oxide MOS Transistor) form, peripheral circuit is realized based on MOS transistor, and its integral body also realizes based on standard CMOS process.But along with constantly reducing of device feature size, the response speed of existing nonvolatile memory more and more cannot meet the demand of practical application, and the durability of repeatedly programming is poor, and the number of times of programming is limited repeatedly, and serviceable life is shorter.
Summary of the invention
The problem that the present invention solves is to provide a kind of MEMS nonvolatile memory and storage unit thereof, improves response speed, increases the service life.
For addressing the above problem, the invention provides a kind of MEMS nonvolatile memory, comprising:
The storage array being formed by a plurality of storage unit;
Line decoder, connects the row select lines of described storage array, for carrying out row decoding;
Column decoder, connects the row select lines of described storage array, for carrying out column decoding;
Read-write control unit, for controlling the read-write state of each bit line of described storage array;
One or more at least one mems switch device that comprise of described storage unit, line decoder, column decoder and read-write control unit, described mems switch device comprises: first end, the second end, the 3rd end and control end, described control end electrically conducts for controlling described the 3rd end and first end and the second end one.
Optionally, described mems switch device comprises:
The first reference electrode and the second reference electrode;
The first link, is connected with described first end;
The second link, is connected with described the second end;
The 3rd link, is connected with described the 3rd end;
Can movable plate electrode, between described the first reference electrode and the second reference electrode, controlled by described control end, can between described the first reference electrode and the second reference electrode, move, when described can movable plate electrode during near described the first reference electrode, described the 3rd link by described can movable plate electrode and described the first link electrically conduct, when described can movable plate electrode during near described the second reference electrode, described the 3rd link by described can movable plate electrode and described the second link electrically conduct.
Optionally, described can comprising by movable plate electrode:
One deck conductive layer at least can move by movable plate electrode by controlling described in the electromotive force official post between described conductive layer and described the first reference electrode, described the second reference electrode between described the first reference electrode and the second reference electrode;
With the conductive contact end of described conductive layer insulation, described conductive layer drives described conductive contact end to realize electrically conducting between described the 3rd link and the first link or the second link.
Optionally, the surface of described conductive layer is also formed with insulation course.
Optionally, the surface of described conductive contact end is through Passivation Treatment.
Optionally, described the 3rd link comprises the first connecting portion and the second connecting portion;
Mutually insulated between described the first connecting portion and described the first link, can be realized mutually and being electrically connected by the conductive contact end on can movable plate electrode;
Mutually insulated between described the second connecting portion and described the second link, can be realized mutually and being electrically connected by the conductive contact end on can movable plate electrode.
Optionally, described the first reference electrode comprises at least one deck conductive layer.
Optionally, the conductive layer surface in described the first reference electrode is formed with insulation course.
Optionally, described the second reference electrode comprises at least one deck conductive layer.
Optionally, the conductive layer surface in described the second reference electrode is formed with insulation course.
Optionally, described line decoder comprises multistage row decoding unit, the quantity of the mems switch device in next stage row decoding unit is the twice of upper level row decoding unit, and the first end of the mems switch device in upper level row decoding unit and the second end are connected the 3rd end of the mems switch device in next stage row decoding unit successively, wherein, the first end of each mems switch device in the row decoding unit of minimum one-level is connected successively each row select lines and is pulled down to logic low with the second end, the 3rd end input logic high level of the mems switch device in highest level row decoding unit, the control end of the mems switch device in row decodings at different levels unit is each binary digit in line of input address successively.
Optionally, described column decoder comprises multistage column decoding unit, the quantity of the mems switch device in next stage column decoding unit is the twice of upper level column decoder unit, and the first end of the mems switch device in upper level column decoding unit and the second end are connected the 3rd end of the mems switch device in next stage column decoding unit successively, wherein, the first end of each mems switch device in the column decoding unit of minimum one-level is connected successively each row select lines and is pulled down to logic low with the second end, the 3rd end input logic high level of the mems switch device in highest level column decoding unit, the control end of the mems switch device in column decodings at different levels unit is inputted each binary digit in column address successively.
Optionally, described storage unit comprises:
The first mems switch device, its first end and the second end be input logic low level and logic high respectively;
The second mems switch device, its first end is high resistant, and its second end connects the control end of described the first mems switch device, and its control end connects row select lines, and its 3rd end connects write bit line;
The 3rd mems switch device, its first end is high resistant, and its second end connects the 3rd end of described the first mems switch device, and its control end connects row select lines, and its 3rd end connects sense bit line, and its cut-in voltage is less than the cut-in voltage of described the second mems switch device.
Optionally, described storage unit comprises:
The 4th mems switch device, its first end and the second end be input logic low level and logic high respectively;
The 5th mems switch device, its first end is high resistant, and its second end connects the control end of described the 4th mems switch device, and its control end connects writes row select lines, and its 3rd end connects write bit line;
The 6th mems switch device, its first end is high resistant, and its second end connects the 3rd end of described the 4th mems switch device, and its control end connects reads row select lines, and its 3rd end connects sense bit line.
Optionally, described line decoder, column decoder and read-write control unit adopt cmos circuit.
Optionally, described read-write control unit also comprises row gating unit, connects described row select lines, controls electrically conducting and off state of each array storage unit.
Optionally, described row gating unit comprises:
The 7th mems switch device, its first end is high resistant, and its second end connects sense bit line, and its control end connects described row select lines;
The 8th mems switch device, its first end is high resistant, and its second end connects write bit line, and its control end connects described row select lines.
Optionally, described read-write control unit also comprises read-write gating unit, receives chip selection signal and read-write control signal, controls described storage unit and carries out read operation or write operation.
Optionally, described read-write gating unit comprises:
The 9th mems switch device, its first end connects the 3rd end of described the 8th mems switch device, and its second end connects the 3rd end of described the 7th mems switch device, and its control end is inputted described read/write control signals;
The tenth mems switch device, its second end is high resistant, and its first end connects the 3rd end of described the 9th mems switch device, and its 3rd end connects input and output pin, and its control end is inputted described chip selection signal.
For addressing the above problem, the invention provides a kind of MEMS nonvolatile memory cell, comprise three mems switch devices, described mems switch device comprises first end, the second end, the 3rd end and control end, described control end electrically conducts for controlling described the 3rd end and first end and the second end one, wherein
The first mems switch device, its first end and the second end be input logic low level and logic high respectively;
The second mems switch device, its first end is high resistant, and its second end connects the control end of described the first mems switch device, and its control end connects row select lines, and its 3rd end connects write bit line;
The 3rd mems switch device, its first end is high resistant, and its second end connects the 3rd end of described the first mems switch device, and its control end connects row select lines, and its 3rd end connects sense bit line, and its cut-in voltage is less than the cut-in voltage of described the second mems switch device.
Optionally, described mems switch device comprises:
The first reference electrode and the second reference electrode;
The first link, is connected with described first end;
The second link, is connected with described the second end;
The 3rd link, is connected with described the 3rd end;
Can movable plate electrode, between described the first reference electrode and the second reference electrode, controlled by described control end, can between described the first reference electrode and the second reference electrode, move, when described can movable plate electrode during near described the first reference electrode, described the 3rd link by described can movable plate electrode and described the first link electrically conduct, when described can movable plate electrode during near described the second reference electrode, described the 3rd link by described can movable plate electrode and described the second link electrically conduct.
Optionally, described can comprising by movable plate electrode:
One deck conductive layer at least can move by movable plate electrode by controlling described in the electromotive force official post between described conductive layer and described the first reference electrode, described the second reference electrode between described the first reference electrode and the second reference electrode;
With the conductive contact end of described conductive layer insulation, described conductive layer drives described conductive contact end to realize electrically conducting between described the 3rd link and the first link or the second link.
Optionally, the surface of described conductive layer is also formed with insulation course.
Optionally, the surface of described conductive contact end is through Passivation Treatment.
Optionally, described the 3rd link comprises the first connecting portion and the second connecting portion;
Mutually insulated between described the first connecting portion and described the first link, can be realized mutually and being electrically connected by the conductive contact end on can movable plate electrode;
Mutually insulated between described the second connecting portion and described the second link, can be realized mutually and being electrically connected by the conductive contact end on can movable plate electrode.
Optionally, described the first reference electrode comprises at least one deck conductive layer.
Optionally, the conductive layer surface in described the first reference electrode is formed with insulation course.
Optionally, described the second reference electrode comprises at least one deck conductive layer.
Optionally, the conductive layer surface in described the second reference electrode is formed with insulation course.
Compared with prior art, the present invention has the following advantages:
The technical program adopts MEMS (Micro-Electro-mechanical System, MEMS (micro electro mechanical system)) switch to realize the part or all of parts in nonvolatile memory, thereby has improved response speed.
Further, mems switch device in the technical program adopts preferred structure, use conductive layer to drive conductive contact end to move, realizing the 3rd link and the first link electrically conducts or electrically conducts with the second link, the durability that its mechanical programming and the process that reads are repeatedly programmed it is better, and serviceable life is longer.
In addition, in the technical program, the leakage current of the structure of preferred mems switch device is less, is conducive to reduce the power consumption of MEMS nonvolatile memory.
Accompanying drawing explanation
Fig. 1 is a kind of memory construction schematic diagram of prior art;
Fig. 2 is a kind of structural representation of line decoder shown in Fig. 1;
Fig. 3 is the read-write control unit of prior art and the syndeton schematic diagram of storage unit;
Fig. 4 is the cross-sectional view of the mems switch device of the embodiment of the present invention;
Fig. 5 is that the mems switch device shown in Fig. 4 is along the combination cross-sectional view of a-a, b-b direction;
Fig. 6 is the 3rd link of mems switch device of the embodiment of the present invention and the second link cross-sectional view while electrically conducting;
Fig. 7 is that the mems switch device shown in Fig. 6 is along the combination cross-sectional view of a-a, b-b direction;
Fig. 8 is the equivalent graphical diagram of the mems switch device of the embodiment of the present invention;
Fig. 9 is the structural representation of line decoder of the MEMS nonvolatile memory of the embodiment of the present invention;
Figure 10 is a kind of structural representation of MEMS nonvolatile memory cell of the MEMS nonvolatile memory of the embodiment of the present invention;
Figure 11 is the structural representation of another kind of MEMS nonvolatile memory cell of the MEMS nonvolatile memory of the embodiment of the present invention;
Figure 12 is the read-write control unit of MEMS nonvolatile memory and the syndeton schematic diagram of storage unit of the embodiment of the present invention;
Figure 13 is that the MEMS nonvolatile memory of the embodiment of the present invention is corresponding to the adjunct circuit structural representation of the line decoder of the storage unit in Figure 11.
Embodiment
Prior art adopts MOS transistor to form storage unit, and its peripheral circuit also uses MOS transistor to build to form, be subject to the restriction of CMOS technique, and its response speed is lower.
The main based semiconductor processing technology of MEMS technology, can be integrated in complicated machinery and circuit structure in one microsystem, realizes sophisticated functions.The technical program adopts mems switch device to realize the part or all of parts in storer, because mems switch device is that mechanical type electrically conducts and turn-offs, therefore, under equal process conditions (suitable characteristic dimension), there is faster response speed and there is better programming durability.
The technical program further adopts preferred mems switch device architecture, use conductive layer to drive conductive contact end to move, realizing the 3rd link and the first link electrically conducts or electrically conducts with the second link, this structure is mechanical construction of switch, has faster response speed and has good durability.
For above-mentioned purpose of the present invention, feature and advantage can more be become apparent, below in conjunction with accompanying drawing, the specific embodiment of the present invention is described in detail.
Set forth detail in the following description so that fully understand the present invention.But the present invention can be different from alternate manner described here and implements with multiple, and those skilled in the art can do similar popularization without prejudice to intension of the present invention in the situation that.Therefore the present invention is not subject to the restriction of following public embodiment.
The one-piece construction of the MEMS nonvolatile memory of the present embodiment is please continue to refer to Fig. 1, wherein, and the one or more mems switch devices that comprise in storage array 10, line decoder 11, column decoder 12 and read-write control unit 13.Describedly comprise that mems switch device refers to above-mentioned all parts and can be all by mems switch device, built and be formed, for example by mems switch device, build the storage array 10 forming, by mems switch device, built line decoder 11, the column decoder 12 forming, by mems switch device, built the read-write control unit 13 forming; In addition, above-mentioned each parts also can part be built and be formed by mems switch device, as one or more in line decoder 11, column decoder 12 and read-write control unit 13 are built and to be formed by mems switch device, and storage array 10 remains and mainly floating boom tunnel oxidation layer MOS transistor, consists of; In addition, above-mentioned each parts also can be mixed and be formed by mems switch device and MOS transistor, realize, and remainder are used MOS transistor to realize as the partial logic in line decoder 11 is used mems switch device.Described mems switch device comprises: first end, the second end, the 3rd end and control end, described control end electrically conducts for controlling described the 3rd end and first end and the second end one.In a preferred embodiment, described storage array 10 adopts mems switch device to form, and described line decoder 11, column decoder 12 and read-write control unit 13 adopt cmos circuit, adopt cmos circuit to refer to herein the circuit being built by MOS transistor that adopts traditional CMOS technique to make.
Fig. 4 shows the cross-sectional view of the preferred structure of the mems switch device in the present embodiment, Fig. 5 shows mems switch device in Fig. 4 along the combination cross-sectional view of a-a, b-b direction, in conjunction with Fig. 4 and Fig. 5, the mems switch device of the present embodiment comprises: the first link 33, is connected with described first end; The second link 32, is connected with described the second end; The 3rd link 31, is connected with described the 3rd end; Can movable plate electrode 20; The first reference electrode 26, the second reference electrode 25, described can movable plate electrode 20 between described the first reference electrode 26 and described the second reference electrode 25, controlled by described control end, can between the first reference electrode 26, the second reference electrode 25, move; When described can movable plate electrode 20 during near the second reference electrode 25, the 3rd link 31 and the second link 32 are by can movable plate electrode 20 electrically conduct (with reference to figure 6 and Fig. 7); When described can movable plate electrode 20 during near the first reference electrode 26, the 3rd link 31 and the first link 33 (are not expressed the 3rd link 31 and the first link 33 electrically conducts by can movable plate electrode 20 electrically conduct in diagram, the example that those skilled in the art electrically conduct according to the 3rd link 31 and the second link 32, can be informed in what situations, the 3rd link 31 and the first link 33 electrically conduct).
Described can comprising by movable plate electrode 20: at least one deck conductive layer 21, be connected with described control end, by controlling conductive layer 21 described in the electromotive force official post between described conductive layer 21 and described the first reference electrode 26, described the second reference electrode 25, between described the first reference electrode 26 and the second reference electrode 25, move; Conductive contact end 22 with described conductive layer 21 insulation, when described conductive layer 21 moves near the second reference electrode 25, conductive layer 21 drives described conductive contact end 22 to realize electrically conducting between the 3rd link 31 and the second link 32, when described conductive layer 21 moves near the first reference electrode 26, drive described conductive contact end 22 to realize electrically conducting between the 3rd link 31 and the first link 33.In specific embodiments of the invention, can comprise two conductive layers 21 by movable plate electrode 20, on the surface of every one deck conductive layer 21, there is insulation course 23, can by two links 24, be fixed on the dielectric layer 41 on substrate 40 surfaces by movable plate electrode 20, two links 24 are electrically connected with conductive layer 21, by two links 24, can apply voltage to conductive layer 21.And in this specific embodiment, two links 24 and insulation course 23 play the effect of bracing frame, play the effect that support can movable plate electrode 20.Conductive contact end 22 has two elongated ends, be respectively the first elongated end 221 and the second elongated end 222, by the first elongated end 221 and the second elongated end 222 can make that the 3rd link 31 and the second link 32 electrically conduct, the 3rd link 31 and the first link 33 electrically conduct, wherein, the first elongated end 221 is for contacting with the 3rd link 31, and the second elongated end 222 is for contacting with the second link 32, the first link 33.
By control the first reference electrode 26, the second reference electrode 25 and can the conductive layer 21 of movable plate electrode 20 between electric potential difference, can make movable pole plate 20 move between the first reference electrode 26 and the second reference electrode 25, the 3rd link 31 and the second link 32 are electrically conducted by described conductive contact end 22, or the 3rd link 31 and the first link 33 electrically conduct by described conductive contact end 22.With reference to figure 6 and Fig. 7, when applying logic high at the first reference electrode 26, for example the first reference electrode 26 connects positive source, the first reference electrode 26 is applied to supply voltage, the second reference electrode 25 applies logic low, the second reference electrode 25 ground connection for example, the second reference electrode 25 is applied to no-voltage, by 24 pairs of conductive layers 21 of link, apply logic high simultaneously, while being supply voltage, between the second reference electrode 25 and conductive layer 21, there is electric potential difference, exist attractive force (to comprise electrostatic effect between the two, ferroelectric effect, capacity effect), therefore, can under the effect of attractive force, to the second reference electrode 25 directions, move by movable plate electrode 20, make conductive contact end 22 connect the 3rd link 31 and the second link 32, the first elongated end 221 contacts with the 3rd link 31, the second elongated end 222 contacts with the second link 32, thereby the 3rd link 31 and the second link 32 are electrically conducted.It should be noted that, at this, example that the 3rd link 31 and the second link 32 electrically conduct has been described, those skilled in the art instruct according to this, can unquestionablely know the situation that the 3rd link 31 and the first link 33 electrically conduct.Generally speaking, between the first reference electrode 26 and conductive layer 21, have electric potential difference, thereby while there is attractive force, the 3rd link 31 and the first link 33 electrically conduct; Between the second reference electrode 25 and conductive layer 21, have electric potential difference, thereby while there is attractive force, the 3rd link 31 and the second link 32 electrically conduct.
In the technical program, conductive layer 21 is at least one deck, in a preferred embodiment, conductive layer 21 is two-layer rhythmo structure, compare the interaction force that can increase between conductive layer 21 and the first reference electrode 26, the second reference electrode 25 with one deck conductive layer 21, thus the sensitivity that can increase mems switch device.The insulation course 23 forming on conductive layer 21 surfaces can prevent that the second reference electrode 25 from contacting with conductive layer 21.
In the present embodiment, the surface of described conductive contact end 22 is through Passivation Treatment, preferred, and the surface of described the first elongated end 221 and the second elongated end 222 is through Passivation Treatment.Described Passivation Treatment refers to surface through oxidation processes, form the thin layer of oxide layer, after peroxidating passivation, do not affect on the one hand the electric conductivity of described conductive contact end 22, can prevent that again conductive contact end 22 from producing adhesion with the 3rd link 31, the second link 32 while contacting with the first link 33.
In specific embodiments of the invention, described the second reference electrode 25 is positioned in substrate 40, be specially, be positioned on the lip-deep dielectric layer 41 of substrate 40, described the first reference electrode 26 is positioned at described the second reference electrode 25 tops, the first reference electrode 26 and the second reference electrode 25 comprise at least one deck conductive layer, can movable plate electrode 20 between the first reference electrode 26 and the second reference electrode 25.In other embodiments of the invention, can there is no substrate 40 yet.
In specific embodiments of the invention, described the 3rd link 31 comprises the second connecting portion 312 and the first connecting portion 311, wherein the second connecting portion 312 and the first connecting portion 311 are electrically connected, and the electrical connection of the second connecting portion 312 and the first connecting portion 311 is not shown in figure.Described the second connecting portion 312 and described the second link 32 are at same metal level, and mutually insulated; Described the first connecting portion 311 and described the first link 33 are at same metal level, and mutually insulated.And the first reference electrode 26 and the second reference electrode 25 comprise respectively one deck conductive layer, the surface with can movable plate electrode 20 close at the first reference electrode 26 has insulation course 27, to prevent that can movable plate electrode 20 during near the first reference electrode 26, the first reference electrode 26 contacts with conductive layer 21.In specific embodiments of the invention, the surface of the second reference electrode 25 does not have insulation course, this be because corresponding thereto can have insulation course 23 by movable plate electrode 20, can prevent that the second reference electrode 25 from contacting with conductive layer 21, certainly, the surface of the second reference electrode 25 also can have insulation course.
In the specific embodiment of the invention, the material of the conductive layer 21 can movable plate electrode 20 comprising can be aluminium, titanium, copper, cobalt, nickel, tantalum, thallium, platinum, silver, gold etc. or its combination, and well known to a person skilled in the art other conductive materials.The material of conductive contact end 22 can be aluminium, titanium, copper, cobalt, nickel, tantalum, thallium, platinum, silver, gold etc. or its combination, and well known to a person skilled in the art other conductive materials.The material of the first reference electrode 26 and the second reference electrode 25 can be aluminium, titanium, copper, cobalt, nickel, tantalum, thallium, platinum, silver, gold etc. or its combination, and well known to a person skilled in the art other conductive materials.The material of the 3rd link 31, the second link 32 and the first link 33 can be aluminium, titanium, copper, cobalt, nickel, tantalum, thallium, platinum, silver, gold etc. or its combination, and well known to a person skilled in the art other conductive materials.
The material of the insulation course 23 on conductive layer 21 surfaces is SiO
2, Si
3n
4, SiN
x, SiON, SiCO
xetc..The material of the insulation course on the first reference electrode 26 surfaces is SiO
2, Si
3n
4, SiN
x, SiON, SiCO
xetc..
In the specific embodiment of the invention, substrate 40 can be also silicon-on-insulator (SOI) for monocrystalline silicon or SiGe (SiGe), can also comprise other material, for example indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide or gallium antimonide.Can also there is MOS device substrate 40 is interior.
It should be noted that, the above is only a specific embodiment of the present invention, in other embodiments, the distribution mode of the first link, the second link and the 3rd link is also not limited to the mode shown in diagram, other modes that can be known to the skilled person, can do corresponding change to it, yet all not depart from spirit of the present invention.For example, in other embodiments, the second connecting portion 312 can be used as the second link, and the first connecting portion 311 can be used as the first link, after the first link 33 and the second link 32 are electrically connected jointly as the 3rd link.
Fig. 8 shows the equivalent schematic symbol diagram of the mems switch device of the present embodiment, comprise: control end A, first end B, the second end C and the 3rd end D, control end A can control described the 3rd end D and first end B or the second end C and electrically conduct, or all disconnects with the two.Wherein, control end A is connected with described conductive layer in can movable plate electrode, and first end B is connected with described the first link, and the second end C is connected with described the second link, and the 3rd end D is connected with described the 3rd link.Follow-up accompanying drawing and description herein is all as the criterion with the equivalent structure shown in Fig. 8.
Fig. 9 shows the structural representation of the line decoder of the present embodiment, this figure is only example, wherein row address is 2 (A0 and A1), corresponding row select lines has 4 (WL0 to WL3), with the function class of the line decoder of prior art seemingly, by row address is carried out to decoding, making one in row select lines is logic high, other be logic low, a line storage unit corresponding to the row select lines of logic high carried out to gating.Described line decoder comprises multistage row decoding unit, the quantity of the mems switch device in next stage row decoding unit is the twice of upper level row decoding unit, the first end of the mems switch device in upper level row decoding unit and the second end are connected the 3rd end of the mems switch device in next stage row decoding unit successively, wherein, the first end of each mems switch device in the row decoding unit of minimum one-level is connected successively each row select lines and is pulled down to logic low with the second end, the 3rd end input logic high level of the mems switch device in highest level row decoding unit, the control end of the mems switch device in row decodings at different levels unit is each binary digit in line of input address successively.In addition, described pull down resistor can be realized with materials such as polysilicons.
Concrete, the line decoder in Fig. 9 comprises 2 grades of row decoding unit, is respectively row decoding unit 52, the first order (being lowermost level in the present embodiment) the 51He second level, row decoding unit (being the superlative degree in the present embodiment).Described first order row decoding unit 51 comprises 2 mems switch devices, and their first end is connected successively described row select lines WL0, WL1, WL2 and WL3 and is pulled down to logic low VCC-with the second end, drop-down process can realize by pull down resistor, the lowest order A0 of their control end line of input address.Row decoding unit, the described second level 52 comprises 1 mems switch device, and its first end and the second end are connected respectively the 3rd end of two mems switch devices in first order row decoding unit 51, the most significant digit A1 of its control end line of input address, its 3rd end is connected to logic high VCC+.The line decoder of the present embodiment can be realized the truth table identical with line decoder in background technology.Certainly, in actual applications, can increase according to demand more multistage row decoding unit, as adopt 3 grades of row decoding unit, the number of the mems switch device comprising from minimum one-level to highest level row decoding unit is once 4,2,1, thereby realizes the decode procedure of 8 row select liness.In addition, described pull down resistor can be realized with materials such as polysilicons.
As a preferred embodiment, in described line decoder, in next stage row decoding unit, be connected in upper level row decoding unit two mems switch devices of same mems switch device can share same can movable plate electrode, still take Fig. 9 as example, two MEMS transistors in first order row decoding unit 51 can share same can movable plate electrode, thereby improve integrated level.
The column decoder of the present embodiment comprises multistage column decoding unit, the quantity of the mems switch device in next stage column decoding unit is the twice of upper level column decoding unit, the first end of the mems switch device in upper level column decoding unit and the second end are connected the 3rd end of the mems switch device in next stage column decoding unit successively, wherein, the first end of each mems switch device in the column decoding unit of minimum one-level is connected successively each row select lines and is pulled down to logic low with the second end, the 3rd end input logic high level of the mems switch device in highest level column decoding unit, the control end of the mems switch device in column decodings at different levels unit is inputted each binary digit in column address successively.The structure of its structure and line decoder is similar, the first end that is only the mems switch device in the column decoding unit of minimum one-level is connected each row select lines successively with the second end, the control end of the mems switch device in column decodings at different levels unit is inputted each binary digit of column address successively, its course of work and line decoder are similar, repeat no more here.
Figure 10 shows the structural representation of a kind of storage unit of the present embodiment, comprising: the first mems switch device M1, and its first end B1 and the second end C1 be input logic low level VCC-and logic high VCC+ respectively; The second mems switch device M2, its first end B2 is high resistant, and its second end C2 connects the control end A1 of described the first mems switch device M1, and its control end A2 connects row select lines WL, and its 3rd end D2 connects write bit line writebit; The 3rd mems switch device M3, its first end B3 is high resistant, its second end C3 connects the 3rd end D1 of described the first mems switch device M1, its control end A3 connects row select lines WL, its the 3rd end D3 connects sense bit line readbit, and its cut-in voltage is less than the cut-in voltage of described the second mems switch device M2.Described cut-in voltage refers to the magnitude of voltage that can make the 3rd end of mems switch device and first end or the second end electrically conduct, cut-in voltage can be by regulating to realize to the parameter of device in manufacture process, as change the distance between the first reference electrode and the second reference electrode, under same voltage, realize different electric field intensity, thereby while making can movable plate electrode to move up and down, needed voltage changes.In addition, described high resistant can be realized by materials such as polysilicons in Practical manufacturing process.
When carrying out write operation, row select lines WL decoding backgating, on it, be higher row select lines voltage, the second end C2 and the 3rd end D2 of the second mems switch device M2 are electrically conducted, the second end C2 and write bit line writebit electrically conduct, data write to the first mems switch device M1 by write bit line writebit, electric charge by write bit line writebit enter in the first mems switch device M1 can movable plate electrode in conductive layer; Although now the 3rd mems switch device M3 also electrically conducts, owing to being now write operation, sense bit line readbit is high-impedance state, does not therefore affect write operation.After described write operation finishes, electric charge on conductive layer in the first mems switch device M1 still exists, if there is electric potential difference between the first reference electrode of described the first mems switch device and the second reference electrode, its 3rd end D1 is connected to logic high VCC+ or logic low VCC-; After power-off, the first reference electrode and the disappearance of the electric potential difference between the second reference electrode due to the first mems switch device M1, what make the first mems switch device M1 can return back to original state by movable plate electrode, and its 3rd end D1 and first end B1, the second end C1 disconnect; After again powering on, due to the first mems switch device M1 can movable plate electrode in conductive layer on electric charge still exist, under the electric field action between the first reference electrode and the second reference electrode, the 3rd end D1 of the first mems switch device M1 reconnects to first end B1 or the second end C1, thereby has realized non-volatile holographic storage.
When carrying out read operation, row select lines WL decoding backgating, on it, be a lower row select lines voltage, under this voltage, the 3rd end D3 and the second end C3 of the 3rd mems switch device electrically conduct, simultaneously, this voltage does not reach the cut-in voltage of the second mems switch device M2, therefore, the second end C2 of the second mems switch device M2 and write bit line writebit are still for disconnecting, the control end A1 of the first mems switch device M1 and write bit line writebit disconnect, therefore wherein can movable plate electrode in conductive layer on electric charge can't lose.
The EEPROM realizing with the employing floating boom tunnel oxidation layer MOS transistor of prior art compares, the storage unit that above-mentioned use mems switch device builds can realize the identical function of storage unit in the EEPROM with prior art, but because this structure is mechanical, therefore its response speed will be higher than floating boom tunnel oxidation layer MOS transistor, and its program voltage is also less than the EEPROM based on floating boom tunnel oxidation layer MOS transistor of prior art, power consumption reduces relatively.In addition, because the structure of the present embodiment is mechanical, so its durability of repeatedly programming is very good, and programming number of times approaches infinitely repeatedly in theory, is far longer than the EEPROM of prior art its serviceable life.In like manner, compare with the flash memory of prior art, the MEMS static storage cell that above-mentioned use mems switch device builds also has response speed faster, lower advantages such as program voltage.And the leakage current of the mems switch device of the present embodiment is less, make the leakage current of corresponding MEMS nonvolatile memory cell and MEMS nonvolatile memory also less, be conducive to reduce power consumption.
Figure 11 shows the structural representation of the another kind of storage unit of the present embodiment, comprising: the 4th mems switch device M4, and its first end B4 and the second end C4 be input logic low level VCC-and logic high VCC+ respectively; The 5th mems switch device M5, its first end B5 is high resistant, and its second end C5 connects the control end A4 of described the 4th mems switch device M4, and row select lines writeword is write in its control end A5 connection, and its 3rd end D5 connects write bit line writebit; The 6th mems switch device M6, its first end B6 is high resistant, and its second end C6 connects the 3rd end D4 of described the 4th mems switch device M4, and row select lines readword is read in its control end A6 connection, and its 3rd end D6 connects sense bit line readbit.
Structure for the storage unit shown in Figure 11, when carrying out write operation, after decoding, writing row select lines writeword is strobed, the 3rd end D5 and the second end C5 of the 5th mems switch device M5 are electrically conducted, the control end A4 of write bit line writebit and the 4th mems switch device M4 electrically conducts, electric charge by write bit line writebit enter the 4th mems switch device M4 can movable plate electrode in conductive layer, similar with the storage unit shown in Figure 10, after power-off, the 4th mems switch device M4 can movable plate electrode in conductive layer on electric charge still keep, after again powering on, still can make the 3rd end D4 be connected to logic high VCC+ or logic low VCC-, realize the non-volatile storage of data.
When carrying out read operation, read the decoded gating of row select lines readword, the 3rd end D6 and its second end C6 of the 6th mems switch device are electrically conducted, thereby the 3rd end D4 and the sense bit line readbit of the 4th mems switch device are electrically conducted, thereby can read the data of storing in the 4th mems switch device M4 by sense bit line readbit, and the process that reads can't cause the 4th mems switch device M4 can movable plate electrode in conductive layer on the loss of electric charge.
Said structure has been realized the function of non-volatile storage, but different from structure in Figure 10 is, this storage unit is connected to respectively to be read row select lines readword and writes row select lines writeword, gating while being respectively used to read operation and write operation, owing to having used different row select liness, make the cut-in voltage of the 5th mems switch device M5 and the 6th mems switch device M6 can be identical, in manufacture process, can use standardized unit, thereby simplify its manufacturing process.But because same storage unit is connected to two row select liness, so row decoding unit need to adjust accordingly, below will be described in detail.
Figure 12 shows the nonvolatile memory cell 30 of the present embodiment and the syndeton schematic diagram of read-write control unit, this figure is only signal, only with a storage unit 30, be described, in actual applications, the storage unit that can have multiple row, described read-write control unit is controlled each array storage unit.Described read-write control unit comprises: row gating unit 61, connects row select lines BL, the electrically conducting and off state of control store unit 30; Read-write gating unit 62, receives chip selection signal
with read-write control signal R/
control described storage unit 30 and carry out read operation or write operation.
Concrete, described row gating unit 61 comprises: the 7th mems switch device M7, and its first end B7 is high resistant, and its second end C7 connects sense bit line readbit, and its control end A7 connects row select lines BL; The 8th mems switch device M8, its first end B8 is high resistant, and its second end C8 connects write bit line writebit, and its control end A8 connects row select lines BL.Described read-write gating unit 62 comprises: the 9th mems switch device M9, its second end C9 connects the 3rd end D7 of described the 7th mems switch device M7, its first end B9 connects the 3rd end D8 of described the 8th mems switch device M8, and its control end A9 inputs read/write control signals
the tenth mems switch device M10, its second end C10 is high resistant, and its first end B10 connects the 3rd end D9 of described the 9th mems switch device M9, and its 3rd end D10 connects input and output pin I/O, and its control end A10 inputs chip selection signal
In actual applications, by row decoding and column decoding, described row select lines WL and row select lines BL are strobed, row select lines BL gating electrically conducts the second end C7 of described the 7th mems switch device M7 and the 3rd end D7, the second end C8 and the 3rd end D8 of the 8th mems switch device M8 electrically conduct, and sense bit line readbit and write bit line writebit that described storage unit 30 connects electrically conduct.Meanwhile, chip selection signal
effectively, the first end B10 of the tenth mems switch device M10 and the 3rd end D10 electrically conduct, and electrically conduct with input and output pin I/O; If write operation, i.e. read/write control signals
for logic low, the 3rd end D9 and the first end B9 of the 9th mems switch device M9 electrically conduct, thereby make input and output pin I/O to storage unit 30, carry out write operation by write bit line writebit; If read operation, i.e. read/write control signals
for logic high, the 3rd end D9 of the 9th mems switch device M9 and the second end C9 electrically conduct, thereby the input and output pin I/O making carries out read operation by sense bit line readbit to storage unit 30.
Syndeton in Figure 12 goes for the structure of the storage unit shown in Figure 10.For the storage unit shown in Figure 11, need to adjust the structure of line decoder, as shown in figure 13, use read/write control signals
row select lines WL is carried out to a decoding again, and gating is to writing row select lines writeword or reading row select lines readword, and thus, the structure in Figure 12 also goes for the storage unit shown in Figure 11.
In the present embodiment, use mems switch device to realize all parts in storer, as a preferred embodiment, storage array adopts mems switch device to form, line decoder, column decoder and read-write control unit adopt conventional cmos circuit, thereby improved response speed, improved the programming durability of MEMS nonvolatile memory, extended serviceable life.In addition, in other embodiments, described MEMS nonvolatile memory comprises that storage unit, line decoder, column decoder and read-write control unit also can all adopt mems switch device to build at interior whole parts and form, owing to all adopting mems switch device, realize, thereby unified process, simplified manufacture process.
To sum up, in the technical program, preferred mems switch device can utilize the last part technology of CMOS technique, only needs metal level and insulation course can realize MEMS nonvolatile memory and row decoding and column decoder.Simplified technique performing step.And the MEMS nonvolatile memory cell of the technical program and MEMS nonvolatile memory have advantages of that program voltage is low, fast response time.In addition, the MEMS nonvolatile memory of the technical program and the leakage current of MEMS nonvolatile memory cell are less, are conducive to reduce power consumption.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; can utilize method and the technology contents of above-mentioned announcement to make possible change and modification to technical solution of the present invention; therefore; every content that does not depart from technical solution of the present invention; any simple modification, equivalent variations and the modification above embodiment done according to technical spirit of the present invention, all belong to the protection domain of technical solution of the present invention.
Claims (27)
1. a MEMS nonvolatile memory, comprising:
The storage array being formed by a plurality of storage unit;
Line decoder, connects the row select lines of described storage array, for carrying out row decoding;
Column decoder, connects the row select lines of described storage array, for carrying out column decoding;
Read-write control unit, for controlling the read-write state of each bit line of described storage array;
It is characterized in that, one or more at least one mems switch device that comprise of described storage unit, line decoder, column decoder and read-write control unit, described mems switch device comprises: first end, the second end, the 3rd end and control end, and described control end electrically conducts for controlling described the 3rd end and first end and the second end one;
Described mems switch device comprises:
The first reference electrode and the second reference electrode;
The first link, is connected with described first end;
The second link, is connected with described the second end;
The 3rd link, is connected with described the 3rd end;
Can movable plate electrode, between described the first reference electrode and the second reference electrode, controlled by described control end, can between described the first reference electrode and the second reference electrode, move, when described can movable plate electrode during near described the first reference electrode, described the 3rd link by described can movable plate electrode and described the first link electrically conduct, when described can movable plate electrode during near described the second reference electrode, described the 3rd link by described can movable plate electrode and described the second link electrically conduct, described line decoder comprises multistage row decoding unit, the quantity of the mems switch device in next stage row decoding unit is the twice of upper level row decoding unit, and the first end of the mems switch device in upper level row decoding unit and the second end are connected the 3rd end of the mems switch device in next stage row decoding unit successively, wherein, the first end of each mems switch device in the row decoding unit of minimum one-level is connected successively each row select lines and is pulled down to logic low with the second end, the 3rd end input logic high level of the mems switch device in highest level row decoding unit, the control end of the mems switch device in row decodings at different levels unit is each binary digit in line of input address successively.
2. MEMS nonvolatile memory according to claim 1, is characterized in that, described can comprising by movable plate electrode:
One deck conductive layer at least can move by movable plate electrode by controlling described in the electromotive force official post between described conductive layer and described the first reference electrode, described the second reference electrode between described the first reference electrode and the second reference electrode;
With the conductive contact end of described conductive layer insulation, described conductive layer drives described conductive contact end to realize electrically conducting between described the 3rd link and the first link or the second link.
3. MEMS nonvolatile memory according to claim 2, is characterized in that, the surface of described conductive layer is also formed with insulation course.
4. MEMS nonvolatile memory according to claim 2, is characterized in that, the surface of described conductive contact end is through Passivation Treatment.
5. MEMS nonvolatile memory according to claim 1, is characterized in that, described the 3rd link comprises the first connecting portion and the second connecting portion;
Mutually insulated between described the first connecting portion and described the first link, can be realized mutually and being electrically connected by the conductive contact end on can movable plate electrode;
Mutually insulated between described the second connecting portion and described the second link, can be realized mutually and being electrically connected by the conductive contact end on can movable plate electrode.
6. MEMS nonvolatile memory according to claim 1, is characterized in that, described the first reference electrode comprises at least one deck conductive layer.
7. MEMS nonvolatile memory according to claim 6, is characterized in that, the conductive layer surface in described the first reference electrode is formed with insulation course.
8. MEMS nonvolatile memory according to claim 1, is characterized in that, described the second reference electrode comprises at least one deck conductive layer.
9. MEMS nonvolatile memory according to claim 8, is characterized in that, the conductive layer surface in described the second reference electrode is formed with insulation course.
10. MEMS nonvolatile memory according to claim 1, it is characterized in that, described column decoder comprises multistage column decoding unit, the quantity of the mems switch device in next stage column decoding unit is the twice of upper level column decoder unit, and the first end of the mems switch device in upper level column decoding unit and the second end are connected the 3rd end of the mems switch device in next stage column decoding unit successively, wherein, the first end of each mems switch device in the column decoding unit of minimum one-level is connected successively each row select lines and is pulled down to logic low with the second end, the 3rd end input logic high level of the mems switch device in highest level column decoding unit, the control end of the mems switch device in column decodings at different levels unit is inputted each binary digit in column address successively.
11. MEMS nonvolatile memorys according to claim 1, is characterized in that, described storage unit comprises:
The first mems switch device, its first end and the second end be input logic low level and logic high respectively;
The second mems switch device, its first end is high resistant, and its second end connects the control end of described the first mems switch device, and its control end connects row select lines, and its 3rd end connects write bit line;
The 3rd mems switch device, its first end is high resistant, and its second end connects the 3rd end of described the first mems switch device, and its control end connects row select lines, and its 3rd end connects sense bit line, and its cut-in voltage is less than the cut-in voltage of described the second mems switch device.
12. MEMS nonvolatile memorys according to claim 1, is characterized in that, described storage unit comprises:
The 4th mems switch device, its first end and the second end be input logic low level and logic high respectively;
The 5th mems switch device, its first end is high resistant, and its second end connects the control end of described the 4th mems switch device, and its control end connects writes row select lines, and its 3rd end connects write bit line;
The 6th mems switch device, its first end is high resistant, and its second end connects the 3rd end of described the 4th mems switch device, and its control end connects reads row select lines, and its 3rd end connects sense bit line.
13. according to the MEMS nonvolatile memory described in claim 11 or 12, it is characterized in that, described line decoder, column decoder and read-write control unit adopt cmos circuit.
14. according to the MEMS nonvolatile memory described in claim 11 or 12, it is characterized in that, described read-write control unit also comprises row gating unit, connects described row select lines, controls electrically conducting and off state of each array storage unit.
15. MEMS nonvolatile memorys according to claim 14, is characterized in that, described row gating unit comprises:
The 7th mems switch device, its first end is high resistant, and its second end connects sense bit line, and its control end connects described row select lines;
The 8th mems switch device, its first end is high resistant, and its second end connects write bit line, and its control end connects described row select lines.
16. MEMS nonvolatile memorys according to claim 15, is characterized in that, described read-write control unit also comprises read-write gating unit, receive chip selection signal and read-write control signal, control described storage unit and carry out read operation or write operation.
17. MEMS nonvolatile memorys according to claim 16, is characterized in that, described read-write gating unit comprises:
The 9th mems switch device, its first end connects the 3rd end of described the 8th mems switch device, and its second end connects the 3rd end of described the 7th mems switch device, its control end input read/write control signals;
The tenth mems switch device, its second end is high resistant, and its first end connects the 3rd end of described the 9th mems switch device, and its 3rd end connects input and output pin, and its control end is inputted described chip selection signal.
18. 1 kinds of MEMS nonvolatile memory cells, is characterized in that, comprise three mems switch devices, described mems switch device comprises first end, the second end, the 3rd end and control end, described control end electrically conducts for controlling described the 3rd end and first end and the second end one, wherein
The first mems switch device, its first end and the second end be input logic low level and logic high respectively;
The second mems switch device, its first end is high resistant, and its second end connects the control end of described the first mems switch device, and its control end connects row select lines, and its 3rd end connects write bit line;
The 3rd mems switch device, its first end is high resistant, and its second end connects the 3rd end of described the first mems switch device, and its control end connects row select lines, and its 3rd end connects sense bit line, and its cut-in voltage is less than the cut-in voltage of described the second mems switch device.
19. MEMS nonvolatile memory cells according to claim 18, is characterized in that, described mems switch device comprises:
The first reference electrode and the second reference electrode;
The first link, is connected with described first end;
The second link, is connected with described the second end;
The 3rd link, is connected with described the 3rd end;
Can movable plate electrode, between described the first reference electrode and the second reference electrode, controlled by described control end, can between described the first reference electrode and the second reference electrode, move, when described can movable plate electrode during near described the first reference electrode, described the 3rd link by described can movable plate electrode and described the first link electrically conduct, when described can movable plate electrode during near described the second reference electrode, described the 3rd link by described can movable plate electrode and described the second link electrically conduct.
20. MEMS nonvolatile memory cells according to claim 19, is characterized in that, described can comprising by movable plate electrode:
One deck conductive layer at least can move by movable plate electrode by controlling described in the electromotive force official post between described conductive layer and described the first reference electrode, described the second reference electrode between described the first reference electrode and the second reference electrode;
With the conductive contact end of described conductive layer insulation, described conductive layer drives described conductive contact end to realize electrically conducting between described the 3rd link and the first link or the second link.
21. MEMS nonvolatile memory cells according to claim 20, is characterized in that, the surface of described conductive layer is also formed with insulation course.
22. MEMS nonvolatile memory cells according to claim 20, is characterized in that, the surface of described conductive contact end is through Passivation Treatment.
23. MEMS nonvolatile memory cells according to claim 19, is characterized in that, described the 3rd link comprises the first connecting portion and the second connecting portion;
Mutually insulated between described the first connecting portion and described the first link, can be realized mutually and being electrically connected by the conductive contact end on can movable plate electrode;
Mutually insulated between described the second connecting portion and described the second link, can be realized mutually and being electrically connected by the conductive contact end on can movable plate electrode.
24. MEMS nonvolatile memory cells according to claim 19, is characterized in that, described the first reference electrode comprises at least one deck conductive layer.
25. MEMS nonvolatile memory cells according to claim 24, is characterized in that, the conductive layer surface in described the first reference electrode is formed with insulation course.
26. MEMS nonvolatile memory cells according to claim 19, is characterized in that, described the second reference electrode comprises at least one deck conductive layer.
27. MEMS nonvolatile memory cells according to claim 26, is characterized in that, the conductive layer surface in described the second reference electrode is formed with insulation course.
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| CN101359504A (en) * | 2008-08-05 | 2009-02-04 | 中国科学院上海微系统与信息技术研究所 | High-speed writing phase-change memory and its high-speed writing method |
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