CN102572437B - Hardware realization method for rapidly decoding CAVLC (context-adaptive variable-length coding) run_before code - Google Patents

Abstract

The invention belongs to the technical field of digital video signal encoding and decoding, in particular to a hardware implementation method for quickly decoding a CAVLCrun_before codeword. This method adopts two methods of code table splitting and codeword merging, and can decode up to 14 run_before codewords whose value is 0, or two run_before codewords whose value is not equal to 0 in one clock cycle. The input video code stream first passes through the leading 1 detector to detect whether the decoded run_before codeword is zero. The leading 1 detector can detect 14 leading 1 bits at a time. The value of the current run_before codeword is not zero. If we record the total number of 0s contained before the current decoding position as zerosLeft, the run_before codeword can be divided into 7 types according to the value of zerosLeft, and the original standard specifies The run_before code table is decomposed into 7 sub-code tables, which are decoded for each type. The invention can greatly improve the data processing capability of the hardware decoder.

Description

A hardware implementation method for fast decoding of CAVLC run_before codewords

technical field

The invention belongs to the technical field of digital video signal encoding and decoding, and in particular relates to a hardware implementation method for decoding a CAVLC run_before codeword.

Background technique

H.264/AVC (Advanced Video Coding) is an international video coding standard jointly formulated by the International Telecommunications Organization (ITU) and the Moving Picture Experts Group (MPEG), and has been widely used in the field of multimedia audio and video. H.264/AVC stipulates that its entropy coding can adopt two methods: Context Adaptive Variable Length Coding (CAVLC) and Context Adaptive Arithmetic Coding (CABAC). CABAC has higher encoding efficiency, but the complexity of encoding and decoding is also greatly increased, while CAVLC has a better balance between encoding efficiency and complexity. Compared with the previous generation of video standards such as MPEG-1 and MPEG-2, the coding efficiency of CAVLC has been significantly improved.

The video header information and prediction information in the video code stream generally use fixed-length codes or exponential Golomb codes with lower complexity, while the residual coefficient information occupies the vast majority of the video code stream, and the encoding of this part of information needs to use more Efficient CAVLC encoding method. There are 5 types of codewords in CAVLC:

1. Coeff_token: This codeword represents the number of non-zero coefficients and the number of trailing ones (TrailingOnes).

2. Sign_trail: This codeword is a trailing 1 symbol. Each symbol is encoded as one bit, with 0 representing a positive 1 and 1 representing a negative 1.

3. Levels: This codeword refers to the amplitude of other non-zero coefficients other than TrailingOnes.

4. Total_zeros: It encodes the number of total zero coefficients after the first non-zero coefficient in reverse Zig-Zag scanning order.

5. Run_before: This codeword refers to the number of zeros before each non-zero coefficient.

For hardware decoding, calculating the magnitude of non-zero coefficients and the run_before codeword is the most time-consuming process in the entire CAVLC decoding process. For a graphic block with a length and height of 4 pixels, if the CAVLC encoding method is used, some codewords such as Coeff_token, sign_trial and Total_zero only need to be decoded once in the decoding process, while run_before codewords can be up to 14. In order to speed up hardware processing, it is necessary to propose a fast decoding method for the run_before codeword.

Contents of the invention

The object of the present invention is to propose a hardware implementation method for fast decoding run_before code words suitable for the CAVLC decoding process specified by the H.264 video specification.

The hardware implementation method for quickly decoding run_before codewords proposed by the present invention can complete the decoding of at most two run_before codewords within one clock cycle. The hardware block diagram of the entire codeword decoding is shown in Figure 1. This method adopts the two methods of code table splitting and codeword merging, and can decode up to 14 run_before codewords whose value is 0, or two run_before codewords whose value is not equal to 0 in one clock cycle. The input video code stream first passes through the leading 1 detector to detect whether the decoded run_before codeword is zero. The leading 1 detector can detect 14 leading 1 bits at a time. If the value of the current run_before codeword is not zero, we record the total number of 0s contained before the current decoding position as zerosLeft. According to the value of zerosLeft, the run_before codeword can be divided into 7 types, that is, the original standard The run_before code table is decomposed into 7 sub-code tables, which are decoded for each type. Up to 2 run_before codewords can be decoded in each clock cycle.

CAVLC defines a variety of codewords. When encoding a 4x4 residual data block, the run_before codeword can appear up to 14 times. Therefore, this hardware implementation method can greatly improve the data processing capability of the hardware decoder.

The specific decoding process is divided into the following four steps:

(1) Code table splitting and codeword merging.

(2) Detect the number of leading 1s.

(3) Select the correct value from the output of 7 code tables according to the value of zerosLeft.

(4) Update the zerosLeft variable. The zerosLeft variable is updated after each run_before codeword is decoded, and the updated value needs to be used in the next decoding.

A code table for decoding the run_before codeword is specified in the H.264 video specification, and the code table is shown in Table 1. The present invention decomposes this code table into 7 smaller code tables, as shown in table 2-table 8, and carries out 5 code tables (table 3, table 4, table 5, table 6, table 7) wherein The codewords are combined so that it can complete the decoding of two codewords in one clock cycle.

CAVLC defines 6 codewords, among which the codeword with non-zero coefficient amplitude and the run_before codeword appear most frequently, and the run_before codeword can appear up to 14 times when encoding a 4x4 residual data block, so this hardware implementation method The data processing capability of the hardware decoder can be greatly improved.

Beneficial effects of the present invention:

The existing method can only decode one run_before codeword in one clock cycle, but the method described in the present invention can double the speed, and can decode the values of multiple run_before codewords in one clock cycle, thereby improving the overall performance of CAVLC decoding speed. Applicable to various electronic devices with H.264 video decoding function.

Description of drawings

Figure 1: Block diagram of hardware decoding of the run_before codeword.

Detailed ways

The present invention will be further described below in conjunction with the accompanying drawings.

The specific implementation of the fast decoding run_before codeword of the present invention is as follows:

(1) Code table splitting and codeword merging.

The code table for decoding the run_before codeword specified in the H.264 video standard is shown in Table 1. Only one run_before codeword value can be obtained by querying this code table once. In order to speed up the decoding process, we split this code table into 7 code tables according to the value of zerosLeft. Table 2 is the code table for zerosLeft>6. Table 3 is the code table for zerosLeft=6. Table 4 is the code table for zerosLeft=5. Table 5 is the code table for zerosLeft=4. Table 6 is the code table for zerosLeft=3. Table 7 is the code table for zerosLeft=2. Table 8 is for the code table when zerosLeft=1. Among them, Table 3, Table 4, Table 5, Table 6, and Table 7 adopt the technique of combining codewords, and each time these 5 tables are queried, 2 run_before codewords can be obtained. Table 2 and Table 8 are obtained directly from Table 1, and each time Table 2 and Table 8 are queried, only one run_before codeword can be obtained.

(2) Detect the number of leading 1s.

When decoding the run_before codeword, first detect the number of leading 1s in the current code stream. The preamble 1 detector in the present invention can detect up to 14 preamble 1s at a time. If the first bit of the input video code stream is 0, then the number of leading 1s is zero, indicating that the current value of run_before is greater than zero, and this process ends and enters step (3). Otherwise, multiple run_before codewords can be decoded simultaneously according to the number of leading 1s, and the decoded values of these run_before codewords are all 0. We record the number of leading 1s as N, if zerosLeft>6 and N≥3, then the values of consecutive N/3 run_before codewords including the current codeword are all 0; if 2<zerosLeft<6 and N ≥2, then the values of N/2 consecutive run_before codewords including the current codeword are all 0; if zerosLeft≤2, then the values of N consecutive run_before codewords including the current codeword are all 0. In the above calculation, if N is not an integer multiple of 3 or 2, N/3 and N/2 take the integer part of the operation result. In the present invention, the maximum value of N is 14, so the leading 1 detector can decode at most 14 run_before codewords whose value is zero at one time.

(3) Select the correct value from the output of 7 code tables according to the value of zerosLeft.

The value range of zerosLeft can be divided into 7 types: greater than 6, 6, 5, 4, 3, 2, 1. At this time, the corresponding code tables are Table 2, Table 3, Table 4, Table 5, Table 6, Table 7, and Table 8 respectively. According to the current value of zerosLeft, select the corresponding code table output as the final decoding result. Every time Table 2 or Table 8 is queried, one run_before codeword value can be obtained, and every time Table 3, Table 4, Table 5, Table 6 or Table 7 is queried, two run_before codeword values can be obtained.

(4) Update the zerosLeft variable.

If the current zerosLeft is equal to 1 or greater than 6, according to the value of the current run_before codeword decoded in step (3), the zerosLeft variable minus the value obtained after decoding the current run_before codeword is the new zerosLeft variable; if the current zerosLeft is equal to For any value in 2, 3, 4, 5, or 6, according to the decoded values of the two run_before codewords obtained in step (3), the zerosLeft variable minus the sum of the two codeword values is the new zerosLeft variable.

After the above four steps, two run_before codewords can be decoded within one clock cycle. The hardware architecture proposed in this invention can greatly accelerate the decoding speed of H.264 CAVLC.

Table 1: Code table for decoding run_before code specified in the H.264 standard

Table 2: Code table for zerosLeft>6 (Table 1)

run_before zerosLeft>6 0 111 1 110 2 101 3 100 4 011 5 010 6 001 7 0001 8 00001 9 000001 10 0000001 11 00000001 12 000000001 13 0000000001 14 00000000001

Table 3: Code table for zerosLeft=6 (Table 2)

Table 4: Code table for zerosLeft=5 (Table 3)

Table 5: Code table for zerosLeft=4 (Table 4)

Table 6: Code table for zerosLeft=3 (Table 5)

Table 7: Code table for zerosLeft=2 (Table 6)

Table 8: Code table for zerosLeft=1 (Table 7)

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Claims (2)

1. the Hardware Implementation of a fast decoding CAVLC run_before code word, it is characterized in that whether first the video code flow of inputting detects run_before code word to be decoded through leading 1 detector is zero, and leading 1 detector at most once can detect 14 leading 1; Input coefficient sorts according to the zigzag mode of stipulating in standard H.264, and the corresponding nonzero coefficient of current run_before code word is designated as to zerosleft to 0 the total number comprising between first coefficient; According to the value of non-zero zerosLeft, run_before code word is divided into 7 types, the run_before code table that is about to stipulate in primary standard is decomposed into 7 sub-code tables, for each type, decodes respectively; Concrete steps are:

(1) code table partition and code word merge;

(2) detect leading 1 number;

(3) according to the value of zerosLeft, from the output of 7 code tables, select correct value;

(4) upgrade zerosLeft variable, after the non-zero run_before code word of at every turn having decoded, zerosLeft variable is upgraded, when decoding next time, use the value after upgrading;

Wherein, described code table partition and code word merge, and are H.264 in video standard, to be given for the code table partition of decoding run_before code word and to merge 7 tables as shown in following table 2-table 8:

Table 2: the code table during for zerosLeft>6

run_before zerosLeft>6 0 111 1 110 2 101 3 100 4 011 5 010 6 001 7 0001 8 00001 9 000001 10 0000001 11 00000001 12 000000001 13 0000000001 14 00000000001

Table 3: the code table during for zerosLeft=6

Table 4: the code table during for zerosLeft=5

Table 5: the code table during for zerosLeft=4

Table 6: the code table during for zerosLeft=3

Table 7: the code table during for zerosLeft=2

Table 8: the code table during for zerosLeft=1

；

Wherein, the step of the number of described detection leading 1 is, if first bit of video code flow of input is 0, so leading 1 number is zero, illustrates that the value of current run_before is greater than zero, and this process finishes, and enters step (3); Otherwise, a plurality of run_before code words of simultaneously decoding of the number according to leading 1, the decode value of these run_before code words is all 0;

The described concrete steps of selecting correct value from the output of 7 code tables according to the value of zerosLeft are:

The span of zerosLeft is divided into 7 kinds: be greater than 6,6,5,4,3,2,1; Corresponding code table is respectively table 2, table 3, table 4, table 5, table 6, table 7, table 8; According to the value of current zerosLeft, select corresponding code table output as final decoded result, every inquiry is table 2 or table 8 once, obtains the value of a run_before code word, every inquiry is table 3, table 4, table 5, table 6 or table 7 once, obtains the value of two run_before code words.

2. the Hardware Implementation of fast decoding CAVLC run_before code word according to claim 1, is characterized in that the concrete steps of described renewal zerosLeft variable are:

If current zerosLeft equals 1 or be greater than 6, according to decoding in step (2), obtain the value of current run_before code word, zerosLeft variable deducts the value that current run_before code word obtains after decoding, is new zerosLeft variable; If current zerosLeft equals any one value in 2,3,4,5,6, according to the value after two run_before codeword decodings that draw in step (2), zerosLeft variable deduct these two code word values and, be new zerosLeft variable.