CN102610501A - Side wall etching method for improving writing speed of floating body effect storage unit - Google Patents
Side wall etching method for improving writing speed of floating body effect storage unit Download PDFInfo
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- CN102610501A CN102610501A CN2012100812132A CN201210081213A CN102610501A CN 102610501 A CN102610501 A CN 102610501A CN 2012100812132 A CN2012100812132 A CN 2012100812132A CN 201210081213 A CN201210081213 A CN 201210081213A CN 102610501 A CN102610501 A CN 102610501A
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- 238000000034 method Methods 0.000 title claims abstract description 28
- 230000000694 effects Effects 0.000 title claims abstract description 24
- 238000005530 etching Methods 0.000 title claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 54
- 230000007935 neutral effect Effects 0.000 claims abstract description 12
- 238000002347 injection Methods 0.000 claims abstract description 10
- 239000007924 injection Substances 0.000 claims abstract description 10
- 238000000137 annealing Methods 0.000 claims abstract description 7
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 10
- 238000004519 manufacturing process Methods 0.000 claims description 8
- 229910052732 germanium Inorganic materials 0.000 claims description 6
- 229910052724 xenon Inorganic materials 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 2
- 230000005684 electric field Effects 0.000 abstract description 7
- 150000002500 ions Chemical class 0.000 abstract 4
- 239000000969 carrier Substances 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 description 8
- 239000002800 charge carrier Substances 0.000 description 6
- 238000005516 engineering process Methods 0.000 description 6
- 239000003990 capacitor Substances 0.000 description 3
- 230000005685 electric field effect Effects 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 230000008447 perception Effects 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
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Abstract
The invention discloses a side wall etching method for improving the writing speed of a floating body effect storage unit. Neutral ions are adopted for carrying out ion injection on the side wall above a drain electrode region so that the etching speed on side wall films above the drain electrode region is higher than the etching speed on side wall films above a source electrode region in the side wall etching process, after etching, the width of the side wall above the drain electrode region is smaller, while the width of the side wall above the source electrode region is greater, after source and drain heavy doping injection and annealing process are carried out, the distance from the doping ions in a drain electrode heavy doping region to a channel is shortened, the distance from the doping ions in a source electrode heavy doping region to the channel is increased, the longitudinal electric field in the drain electrode channel is enhanced, the substrate current is increased, and in addition, the speed of accumulated current carriers leaking from the source electrode heavy doping region is reduced, so the writing speed of the floating body effect storage unit is improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, relate in particular to a kind of side wall lithographic method that improves floater effect memory cell writing speed.
Background technology
The development of embedded dynamic memory technology makes that big capacity dynamic memory (DRAM) is used in present system level chip (SOC) very general.The big embedded dynamic memory of capacity (EDRAM) can only improve the bandwidth of SOC and the power consumption that reduces SOC through embedded technology.Each memory cell of traditional embedded dynamic memory also comprises a deep trench capacitor structure except comprising transistor, the deep trench of capacitor makes that its width of aspect ratio of memory cell is a lot of greatly, causes the manufacturing process difficulty.In addition, the manufacture craft of the manufacture craft of embedded dynamic memory and CMOS (complementary metal oxide semiconductors (CMOS)) very lagre scale integrated circuit (VLSIC) is very incompatible, has limited its application in embedded SOC.
Floater effect memory cell (Floating Body Cell, i.e. FBC) is a kind of dynamic memory that is hopeful to substitute EDRAM.FBC utilizes floater effect (Floating Body Effect; Be FBE) DRAM cell; Its principle is to utilize silicon-on-insulator (Silicon on Insulator; Be SOI) buffer action of oxygen buried regions (BOX) is brought in the device floater effect, segregate buoyancy aid (Floating Body) as memory node, is realized one writing and write " 0 ".
Figure 1A～1B is the operation principle sketch map of FBC.With the nmos pass transistor is example, please with reference to Figure 1A, adds forward bias at grid (G) 13 and drain electrode (D) 12 ends; The nmos pass transistor conducting, because nmos pass transistor inner transverse effect of electric field, thereby electronics produces electron hole pair with the silicon atom ionization by collision near drain electrode 12; Wherein a part of hole is swept substrate 11 by longitudinal electric field, forms substrate current, again because the existence of aerobic buried regions (BOX); Substrate current can't discharge; Make the hole gather as buoyancy aid, be first kind of store status this moment, may be defined as one writing.The situation of writing " 0 " applies positive bias on grid 13 shown in Figure 1B, apply back bias voltage in drain electrode on 12, and through the PN junction forward bias, the hole is transmitted into the drain electrode 12 and source electrode 14 at two ends from buoyancy aid, and be second kind of store status this moment, is defined as and writes " 0 ".Because gathering of substrate electric charge can change the threshold voltage (V of nmos pass transistor device
t), thereby the difference of big or small threshold of perception current voltage that therefore can be through electric current judge and write " 0 " and this two states of one writing, promptly realize read operation.Because the floater effect memory cell removed the capacitor among traditional DRAM, its technological process fully with the CMOS process compatible, simultaneously can the higher memory of component density, therefore be hopeful alternative existing traditional E DRAM and be applied in the embedded system chip.
The floater effect memory cell is when one writing, and charge carrier gathers at substrate on one side, on one side can be from source electrode leakage slowly.The speed of one writing by the size of substrate current and the charge carrier that gathers from the common decision of speed of source leakage.Improve the substrate current of floater effect memory cell, just can improve the writing speed of floater effect memory cell.In addition, the charge carrier that the minimizing substrate gathers also can reach the purpose that improves floater effect memory cell writing speed from source leakage.
Shown in Fig. 2 A～2C, in the technology, the side wall etching technics of floater effect memory cell may further comprise the steps usually:
At first; Substrate 21 is provided, and said substrate 21 comprises source region and drain region, is formed with source electrode extension area 24 in the said source region; Be formed with drain electrode extension area 25 in the said drain region; Be formed with grid structure 22 on the said substrate 21, deposition forms side wall sedimentary deposit 23 on substrate 21 and grid structure 22 subsequently, shown in Fig. 2 A;
Next; Adopt anisotropic dry etch process that side wall sedimentary deposit 23 is carried out etching,, above the drain region, form drain electrode side wall 23b above the source region, to form source electrode side wall 23a; Said source electrode side wall 23a and drain electrode side wall 23b are symmetrical structure, shown in Fig. 2 B;
Then; Shown in Fig. 2 C, carry out the source and leak heavy doping and annealing process, in substrate, form source electrode heavily doped region 241 and drain electrode heavily doped region 251; Can learn; The position of source electrode heavily doped region 241 and drain electrode heavily doped region 251 receives the influence of source electrode side wall 23a and drain electrode side wall 23b, that is, dopant ion determines apart from the distance of the device channel width by side wall in source electrode heavily doped region 241 and the drain electrode heavily doped region 251.
Summary of the invention
The object of the present invention is to provide a kind of side wall lithographic method that can effectively improve floater effect memory cell writing speed.
For solving the problems of the technologies described above, the present invention provides a kind of side wall lithographic method that improves floater effect memory cell writing speed, and said method comprises: substrate is provided, is formed with grid structure on the said substrate, said substrate comprises source region and drain region; On said substrate, form the side wall sedimentary deposit; On the side wall sedimentary deposit above the said source region, form photoresist layer; Adopt neutral ion that the side wall sedimentary deposit of top, drain region is carried out the ion injection; Remove said photoresist layer, said side wall sedimentary deposit is carried out etching, with formation source electrode side wall above said source region, and above said drain region, form the drain electrode side wall, the cross-sectional width of said source electrode side wall is greater than the cross-sectional width of said drain electrode side wall.
Preferable, in the side wall lithographic method of described raising floater effect memory cell writing speed, said neutral ion is germanium ion or xenon ion.
The present invention also provides a kind of method, semi-conductor device manufacturing method, comprising: on substrate, form grid structure, said substrate comprises source region and drain region; With said grid structure is mask, in the substrate of grid structure both sides, carries out light dope, forms source electrode extension area and drain electrode extension area; On said substrate, form the side wall sedimentary deposit; On the side wall sedimentary deposit above the said source region, form photoresist layer; Adopt neutral ion that the side wall sedimentary deposit of top, drain region is carried out the ion injection; Remove said photoresist layer, said side wall sedimentary deposit is carried out etching, above said source region, to form the source electrode side wall, above said drain region, form the drain electrode side wall, the cross-sectional width of said source electrode side wall is greater than the cross-sectional width of said drain electrode side wall; Carry out the source and leak heavy doping and annealing process.
Preferable, in described method, semi-conductor device manufacturing method, said neutral ion is germanium ion or xenon ion.
The present invention also provides a kind of semiconductor device, comprising: substrate, and said substrate comprises source region and drain region; Be formed at the grid structure on the said substrate; Be formed at the source electrode side wall of top, said source region and the drain electrode side wall that is formed at top, said drain region, the cross-sectional width of said source electrode side wall is greater than the cross-sectional width of drain electrode side wall; Be formed in the said substrate the source electrode heavily doped region with the drain electrode heavily doped region, said source electrode heavily doped region with the drain electrode heavily doped region be unsymmetric structure, said drain electrode heavily doped region than source electrode heavily doped region more near raceway groove.
The present invention utilizes photoresist to cover the side wall sedimentary deposit of top, source region and adopts neutral ion that the side wall sedimentary deposit of top, drain region is carried out the ion injection; Make in the side wall etching technics etching speed to the side wall sedimentary deposit above the drain region be greater than the etching speed of the side wall sedimentary deposit above the source region; The cross-sectional width of drain electrode side wall is less relatively after the etching, and the cross-sectional width of source electrode side wall increases relatively; After heavy doping injection and annealing process were leaked in the source, the dopant ion of drain electrode heavily doped region was furthered from channel distance, and the dopant ion of source electrode heavily doped region and the distance of raceway groove are zoomed out.Behind the grid making alive, the drain region longitudinal electric field is strengthened, and makes the hole of ionization under stronger longitudinal electric field effect, swept substrate, has increased substrate current; Reduced on the other hand and gathered the leakage rate of charge carrier, thereby improved the writing speed of floater effect memory cell from the source electrode heavily doped region.
Description of drawings
Figure 1A-Figure 1B is the sketch map of buoyancy aid dynamic random memory cell one writing and " 0 ";
Fig. 2 A-Fig. 2 C is the device profile sketch map in the side wall lithographic method in the prior art;
Fig. 3 A-Fig. 3 F is the device profile sketch map in the side wall lithographic method of the present invention's one specific embodiment.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
Please with reference to Fig. 3 A-Fig. 3 C, can adopt nmos device as buoyancy aid dynamic random memory cell in the buoyancy aid dynamic random access memory technology, the side wall lithographic method of raising floater effect memory cell writing speed of the present invention comprises:
At first; Shown in Fig. 3 A; On substrate 31, form grid structure 32, said substrate comprises source region and drain region, and said source region is meant the follow-up zone that will form source electrode extension area and source electrode heavily doped region; In like manner, said drain region is meant the follow-up zone that will form drain electrode extension area and drain electrode heavily doped region;
Then, shown in Fig. 3 B, be mask with grid structure 32, in the substrate 31 of grid structure 32 both sides, carry out light dope, form source electrode extension area 33 and drain electrode extension area 34;
Subsequently; Shown in Fig. 3 C; On above-mentioned substrate 31 and grid structure 32, form side wall sedimentary deposit 35; Said side wall sedimentary deposit 35 comprises side wall sedimentary deposit 351 that covers the top, source region and the side wall sedimentary deposit 352 that covers the top, drain region, and wherein, side wall sedimentary deposit material is silica or silicon nitride;
Then; Please with reference to Fig. 3 D; On the side wall sedimentary deposit 351 above the source region, cover photoresist layer 36, and adopt neutral ion that the side wall sedimentary deposit 352 of top, drain region is carried out the ion injection, wherein said neutral ion can be germanium, xenon plasma; The embodiment of the invention adopts germanium ion that the side wall sedimentary deposit 352 of drain electrode top is carried out the ion injection, can increase the etch rate of the side wall sedimentary deposit 352 of top, drain region with respect to the side wall sedimentary deposit 351 of top, source region;
Then,, remove the photoresist 36 of top, source region, side wall sedimentary deposit 35 is carried out the side wall etching please with reference to Fig. 3 E.Because the etch rate of the side wall sedimentary deposit 352 of top, drain region will be higher than the etch rate of the side wall sedimentary deposit 351 of top, source region; Suitably regulate the side wall etching menu (recipe) of etching machine bench, the side wall after the final etching can reduce at the width that drains; Can increase at source electrode; Be the width of the width of source electrode side wall 351A greater than drain electrode side wall 352A, those skilled in the art can be known through the limited number of time experiment will not limit process menu at this;
At last, please with reference to Fig. 3 F, above-mentioned device is carried out the source leak heavy doping and annealing steps; Leak in heavy doping and the annealing process in the source, because the distance of dopant ion and device channel determines by the width of side wall, so after the doping; The dopant ion of drain electrode heavily doped region and the distance of device channel are furthered, and behind the grid making alive, drain terminal zone longitudinal electric field is strengthened; Make the hole of ionization under stronger longitudinal electric field effect, swept substrate; Increased substrate current, and the distance of the dopant ion of source electrode heavily doped region and device channel is zoomed out, reduced charge carrier that substrate gathers speed from source leakage.But owing to source electrode side wall 351A remains unchanged with the width sum of drain electrode side wall 352A, so the distance that leak between the heavy doping ion in the source remains unchanged.
Accordingly, the present invention also provides a kind of semiconductor device, and with reference to figure 3F, said semiconductor device comprises:
Be formed at the grid structure 32 on the said substrate;
Be formed at the source electrode side wall 351A of top, said source region and the drain electrode side wall 352A that is formed at top, said drain region, the cross-sectional width of said source electrode side wall 351A is greater than the cross-sectional width of drain electrode side wall 352A;
Be formed at source electrode heavily doped region 331 and drain electrode heavily doped region 341 in the said substrate 31, said source electrode heavily doped region 331 is a unsymmetric structure with drain electrode heavily doped region 341, said drain electrode heavily doped region 341 than source electrode heavily doped region more near raceway groove 331.
Because the dopant ion of drain electrode heavily doped region and the distance of device channel are furthered; Thereby improved the longitudinal electric field in the drain channel, the electron hole pair that the carrier impact of being quickened by transverse electric field produces, the hole can be swept substrate under stronger longitudinal electric field effect; Increased substrate current; On the other hand, the dopant ion of source electrode heavily doped region and the distance of device substrate are zoomed out, and gather the leakage rate of charge carrier from the source electrode heavily doped region thereby reduced.The present invention has improved the writing speed of floater effect memory cell through improving the side wall etching technics.
In addition; Because when the distance of the heavy doping ion of source electrode heavily doped region and raceway groove is zoomed out; The heavy doping ion of drain electrode heavily doped region and the distance of raceway groove are furthered; The distance that leak between the heavy doping ion in total source remains unchanged, so the length of effective channel of device (Effective Channel Length) remains unchanged basically, and other performances of device are able to keep.
The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim example of the present invention change and modify, and all should belong to claim covering scope of the present invention.
Claims (5)
1. a side wall lithographic method that improves floater effect memory cell writing speed is characterized in that, comprising:
Substrate is provided, is formed with grid structure on the said substrate, said substrate comprises source region and drain region;
On said substrate, form the side wall sedimentary deposit;
On the side wall sedimentary deposit above the said source region, form photoresist layer;
Adopt neutral ion that the side wall sedimentary deposit of top, drain region is carried out the ion injection;
Remove said photoresist layer, said side wall sedimentary deposit is carried out etching, with formation source electrode side wall above said source region, and above said drain region, form the drain electrode side wall, the cross-sectional width of said source electrode side wall is greater than the cross-sectional width of said drain electrode side wall.
2. the side wall lithographic method of raising floater effect memory cell writing speed as claimed in claim 1 is characterized in that said neutral ion is germanium ion or xenon ion.
3. a method, semi-conductor device manufacturing method is characterized in that, comprising:
On substrate, form grid structure, said substrate comprises source region and drain region;
With said grid structure is mask, in the substrate of grid structure both sides, carries out light dope, forms source electrode extension area and drain electrode extension area;
On said substrate, form the side wall sedimentary deposit;
On the side wall sedimentary deposit above the said source region, form photoresist layer;
Adopt neutral ion that the side wall sedimentary deposit of top, drain region is carried out the ion injection;
Remove said photoresist layer, and said side wall sedimentary deposit is carried out etching, above said source region, to form the source electrode side wall, above said drain region, form the drain electrode side wall, the cross-sectional width of said source electrode side wall is greater than the cross-sectional width of said drain electrode side wall;
Carry out the source and leak heavy doping and annealing process, form source electrode heavily doped region and drain electrode heavily doped region, said source electrode heavily doped region is a unsymmetric structure with the drain electrode heavily doped region, said drain electrode heavily doped region than source electrode heavily doped region more near raceway groove.
4. method, semi-conductor device manufacturing method as claimed in claim 3 is characterized in that, said neutral ion is germanium ion or xenon ion.
5. a semiconductor device is characterized in that, comprising:
Substrate, said substrate comprises source region and drain region;
Be formed at the grid structure on the said substrate;
Be formed at the source electrode side wall of top, said source region and the drain electrode side wall that is formed at top, said drain region, the cross-sectional width of said source electrode side wall is greater than the cross-sectional width of drain electrode side wall;
Be formed in the said substrate the source electrode heavily doped region with the drain electrode heavily doped region, said source electrode heavily doped region with the drain electrode heavily doped region be unsymmetric structure, said drain electrode heavily doped region than source electrode heavily doped region more near raceway groove.
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| CN2012100812132A CN102610501A (en) | 2012-03-23 | 2012-03-23 | Side wall etching method for improving writing speed of floating body effect storage unit |
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| CN2012100812132A CN102610501A (en) | 2012-03-23 | 2012-03-23 | Side wall etching method for improving writing speed of floating body effect storage unit |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6168999B1 (en) * | 1999-09-07 | 2001-01-02 | Advanced Micro Devices, Inc. | Method for fabricating high-performance submicron mosfet with lateral asymmetric channel and a lightly doped drain |
| KR20040002204A (en) * | 2002-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing the same |
| CN101647108A (en) * | 2005-10-07 | 2010-02-10 | 国际商业机器公司 | Structure and method for forming asymmetrical overlap capacitance in field effect transistors |
| CN102394228A (en) * | 2011-11-17 | 2012-03-28 | 上海华力微电子有限公司 | Method for enhancing read-in speed of floating body effect storage unit and semiconductor device |
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2012
- 2012-03-23 CN CN2012100812132A patent/CN102610501A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6168999B1 (en) * | 1999-09-07 | 2001-01-02 | Advanced Micro Devices, Inc. | Method for fabricating high-performance submicron mosfet with lateral asymmetric channel and a lightly doped drain |
| KR20040002204A (en) * | 2002-06-29 | 2004-01-07 | 주식회사 하이닉스반도체 | Semiconductor device and method for manufacturing the same |
| CN101647108A (en) * | 2005-10-07 | 2010-02-10 | 国际商业机器公司 | Structure and method for forming asymmetrical overlap capacitance in field effect transistors |
| CN102394228A (en) * | 2011-11-17 | 2012-03-28 | 上海华力微电子有限公司 | Method for enhancing read-in speed of floating body effect storage unit and semiconductor device |
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Application publication date: 20120725 |