CN102611853B - A kind of complementary metal oxide semiconductors (CMOS) time delay integration formula sensor - Google Patents

Abstract

The invention discloses a Complementary Metal Oxide Semiconductor (CMOS) time delay and integration (TDI) image sensor composed of M pixels. Each pixel is formed by a row of N time delay and integration stages. Each time delay and integration stage includes: a photodiode, which collects the photocharge; and a preamplifier, which proportionally converts the photocharge into a voltage. Each time delay and integration stage also includes a set of capacitors, amplifiers, and switches to store the integrated signal voltage, while correlated double sample and hold (CDS) techniques (real or pseudo) maintain the optical signal and reset the voltage simultaneously. This CMOS time delay and integration architecture is particularly beneficial for implementing X-ray scanning detector systems that require large pixel size and signal processing circuitry and allows the signal processing circuitry to be physically separated from the photodiode array for shielding Signal circuits are protected from X-ray radiation damage.

Description

A Complementary Metal Oxide Semiconductor Time Delay Integral Sensor

technical field

The present invention relates to the field of solid state image sensors, and more particularly to a complementary metal oxide semiconductor (CMOS) time delay and integration (TDI) sensor for X-ray image scanning applications.

Background technique

The present invention relates to time-delay and integration (TDI) complementary metal-oxide-semiconductor (CMOS) linear image sensors suitable for high-speed X-ray image scanning applications. Typically time-delay and integrating image sensors are used in high-speed line scan applications where the integrating input light signal is very low. In normal line scan applications, one way to increase the integration of the input light signal is to reduce the scan speed and thus increase the integration time. This time delay and integrating sensor allows line scan detector systems to increase the light signal without sacrificing scan rate. This time delay and integration sensor uses a charge transfer device, such as a charge coupled device (CCD), and is implemented in the normal way.

In a CCD time delay and integration array, each detector pixel includes N stages of time delay and integration positions. For example, for a linear detector with M pixels, which includes a two-dimensional M×N-level CCD array, the N-level CCDs for each pixel are parallel to the scanning direction. In operation, the first stage CCD integrates the light signal for an integration time equal to one line time. This signal charge will be transferred from the first stage of the CCD to the second stage, and the object under scanning will also be moved from the first stage of the CCD to the second stage synchronously with the movement of the signal charge. The second stage CCD integrates the signal charge for the same object during a second integration time. Therefore, at the end of the integration time, the signal charge of the CCD at the second stage is twice that of the signal charge it received from the first stage. Then, the signal charge of the second-stage charge-coupled device is moved to the third stage synchronously with the movement of the object. This third stage CCD again integrates the light signal in addition to the signal received by the second stage. This process repeats, and when it reaches the last N stage of CCD, the light signal is increased by N times. Then, M pixel signals are sequentially read out by using an output charge-coupled device register.

Although, the charge-coupled device time-delay and integral imaging system is widely used in visual high-speed industrial inspection applications and medical X-ray scanning applications, such as computer tomography (CT) scanning and dental panoramic scanning, which are used in X-ray industrial inspection There are indeed shortcomings in the application. In X-ray industrial inspection systems, under normal conditions, the detector pixel size is quite large compared to the normal CCD sensor pixel size. In such applications, the required pixel size ranges from a few millimeters to tens of millimeters. As the pixel size increases, the scan rate of CCDs drops drastically, making them unsuitable for this application.

A second disadvantage of the CCD time-delay and integral imaging system is that it is very susceptible to damage from X-ray radiation. In medical X-ray scanning applications, the X-ray energy and dose used are much lower than in industrial inspection applications under normal circumstances. In medical applications, not only is X-ray dose regulated by the Federal Drug Administration (FDA), but due to human soft tissue, its energy is normally below 100K electron volts (ev). For industrial applications, the energy used ranges from 50KeV to 15MeV, depending on the type of material to be inspected. Since there is no regulation to limit the X-ray dose in the industrial inspection system, the dose used can be much higher than that used in the medical scanning system. This cumulative radiation exposure of the CCD sensor to X-rays increases its dark current, shifts its well potential, and thus reduces its useful life.

Contents of the invention

It is an object of the present invention to implement a complementary metal-oxide-semiconductor (CMOS) detector system that alleviates the disadvantages of CCD detectors in X-ray industrial inspection systems. Since the signal charge does not move from one CMOS circuit to another in the charge domain, it is more difficult to use CMOS circuits to implement time-delay and integrating sensors. The method of the present invention uses a charge integrating and summing amplifier to implement a time delay and integrating sensor in a CMOS circuit.

It is therefore an object of the present invention to provide a time delay and integration (TDI) image sensing structure which can be implemented using standard CMOS processes.

Another object of the present invention is to provide a time-delay and integration image sensing detector system that is suitable for technologies such as larger pixel-to-pixel pitches used in X-ray industrial inspection systems without at the expense of read speed.

Still another object of the present invention is to provide an X-ray time delay and integration detection system, wherein the CMOS circuit can be separated from the photodiode detector, so that the CMOS circuit can be easily shielded, To avoid X-ray radiation damage.

An advantage of the present invention is that CMOS circuits can be used in many ways to implement time delay and integrate sensors. First, all peripheral devices such as amplifiers, timing generators, and drivers can be integrated with the photodiodes using standard commercial CMOS processes. Second, it can be implemented using a large pixel size detector, for example a large pixel detector with a pixel size of 0.8 millimeters to several millimeters. This is especially beneficial for X-ray scanning applications that require large pixel sizes, such as container and oil pipeline inspection. It is well known that CCDs work better with smaller pixel sizes. As the pixel size gets larger, the speed of the CCD drops dramatically. Therefore, CMOS time delay and integration sensors are more suitable for X-ray industrial scanning applications. Third, it is well known that CCDs and CMOS circuits are susceptible to X-ray radiation damage. In this CMOS implementation, peripheral circuitry can be integrated on the same die as the photodiode array, but with sufficient separation or clearance from the photodiode detector. Therefore, peripheral circuits can be easily covered with heavy metals such as lead, shielding them from X-ray radiation damage.

The present invention uses photodiodes as detectors to integrate incoming light signals. Each time delay and integration stage includes: a photodiode detector, amplifiers, storage capacitors, and switches. Each photodiode is connected to an integral amplifier, a summing circuit, and a plurality of storage circuits. This integrating and summing function can be implemented in single or multiple amplifiers. The storage circuit is implemented using a storage capacitor and a buffer amplifier. Use correlated double sample and hold (CDS) technique to maintain optical signal and reset voltage at the same time. Correlated double sampled and held optical signal (signal and reset) voltages can be passed to a later time delay and integration stage for summing without accumulating bias noise. This latter time delay and integration stage in the sequence not only integrates the optical signal during an integration time (line time), but also receives the stored associated double sample and hold voltage from the previous time delay and integration stage. The summing circuit combines the current with the previous time-delayed and integrating stage correlated double-sampled and held light signal and outputs this new correlated double-sampled and held voltage to the storage circuit. The stored correlated double sample and hold voltages are passed to the next time delay and integration stage. This process is repeated until the last time delay and integration stage is reached, and the correlated double sample and hold signal is read by the difference amplifier. Normally, reading is performed using a digital scan shift register similar to a standard CMOS linear photodiode array (PDA). The operation of the time delay and integration function, including charge integration, summation and correlated double sample and hold signal storage and transfer, is controlled by a plurality of control switches and a set of timing signals.

The advantage of using CMOS circuits to implement a time delay and integration detector system is that it can be integrated on a single chip with all operating clock generators and signal processing circuits using standard CMOS processes . Therefore, manufacturing cost can be reduced.

Another advantage of using CMOS circuits to implement an X-ray time-delay and integration detector system is that it can be implemented at very high scan speeds at the same time with larger pixel sizes.

Another advantage of using CMOS circuits in the present invention to implement a time delay and integration detector system is that the CMOS circuits can be separated from the photodiodes. Therefore, the CMOS circuits can be properly shielded from X-ray radiation damage.

These and other objects and advantages of the present invention will become apparent to those skilled in the art from the description of the best mode currently known for carrying out the invention and with reference to the accompanying drawings.

Description of drawings

1 is a circuit diagram of a Complementary Metal Oxide Semiconductor (CMOS) Time Delay and Integrator (TDI) stage according to the present invention;

2 is a circuit diagram of a row of time delay and integration pixels with N time delay and integration stages, and a block diagram of a digital scanning shift register;

Fig. 3 is the block diagram of output differential amplifier reading video signal;

FIG. 4 is a timing diagram of operating a time delay and integration sensor;

Fig. 5 is the circuit diagram of another preferred embodiment of the present invention; And

FIG. 6 is another timing diagram of operating the time delay and integration sensor.

Explanation of reference signs: 10-scan shift register; 20-differential amplifier; 30-gain stage; 50-first stage; 52-summing capacitor; 60-integrating amplifier; 61-summing capacitor; 62- Summing capacitor; 70-summing amplifier; 100-time delay and integration stage; 101-photodiode; 102-summing capacitor; 103-integrating and summing amplifier; 104-correlated double sampling and holding circuit; stage; 205-buffer amplifier; 206-buffer amplifier; 207-switch.

detailed description

1 to 4 illustrate a preferred embodiment of the present invention. FIG. 1 shows a circuit diagram of a time delay and integrate (TDI) stage 100 . FIG. 2 shows a circuit diagram of a pixel of a linear detector with N time delay and integration stages. For an M pixel array, it includes M rows of circuits, as shown in FIG. 2 . Figure 3 shows a block diagram of a correlated double sample and hold differential amplifier for reading the signal at the final time delay and integration stage. Figure 4 shows a timing diagram for operating a time delay and integration sensor.

As shown in FIG. 1 , each time delay and integration stage 100 includes: a photodiode 101 , a summing capacitor 102 , an integrating and summing amplifier 103 , and a correlated double sample and hold circuit 104 . The integrating and summing amplifier 103 includes: an amplifier A1, an integrating capacitor C1, and a reset switch SW1. An integrating capacitor C1 and a reset switch SW1 are connected between the input and output terminals of the amplifier A1. Correlated double sampling and holding circuit 104 includes: two input switches SW2 and SW3; a first storage circuit, which includes capacitor C2 and buffer amplifier A2; a transfer switch SW4; a second storage circuit, which includes capacitor C3 and buffer amplifier Amplifier A3; a third storage circuit including capacitor C4 and buffer amplifier A4; and two output switches SW5 and SW6. A summing capacitor 102 is used to receive the reset and light signal voltages from the previous time delay and integration stage. The integrating and summing amplifier 103 is used to reset the photodiode 101 and the reset and light signal voltage from the previous time delay and integrating stage with its own photodiode 101 is integrated and summed. The combined reset and light signal voltage from the output of integrating and summing amplifier 103 is sampled and held using correlated double sample and hold circuit 104 .

Figure 2 shows a row of pixels with individual time delay and integration circuits connected in series with N stages. Each individual time delay and integration stage is a duplicate of the time delay and integration stage 100 , except that the first stage 50 and the last stage 200 are different. In the first time delay and integration stage 50, since there is no previous stage, one end of the summing capacitor 52 is connected to ground. In the final stage 200, buffer amplifiers A3 and A4 are replaced by buffer amplifiers 205 and 206, which have larger drive power to drive the heavier capacitive load of output differential amplifier 20, as shown in FIG. In order to read the reset and light signals conveniently, the output switches SW5 and SW6 of the last stage 200 are replaced by a set of switches 207 . The switch 207 is driven by SM representing the output from the digital scan shift register 10 . The scan shift register 10 sequentially reads the pixels of the M-level array similar to the standard photodiode array. All switches SW1 to SW6 in each time delay and integration stage are driven by the same clock pulse, as shown in FIG. 4 .

Referring to FIG. 1 , in operation, photodiode 101 and integrating and summing amplifier 103 are reset by closing switch SW1 before their optical signal integration process begins. At the same time, the switches SW2 and SW6 are also turned off. Closing of this switch SW6 allows the reset voltage stored on capacitor C4 to be transferred to subsequent time delay and integration stages. Thus, the reset voltage of the previous time delay and integration stage is summed with the reset voltage of the amplifier 103 via the summing capacitor 102 . The combined reset voltage is stored on capacitor C2 via switch SW2. To start the integration process for each time delay and integration stage, switch SW1 is opened, followed by switches SW2 and SW6. There is a delay between SW2 and SW1 turning on (SW1 turns on earlier than SW2), as shown in the timing diagram of FIG. 4 . This shows that amplifier A1 is pre-set before sampling this reset voltage in capacitor C2.

Once the integration process begins, switch SW5 is closed to allow the optical signal stored on capacitor C3 to be transferred to subsequent time delay and integration stages. Thus, the previous time-delayed and integrated-level optical signal is summed with the current time-delayed and integrated-level optical signal from the photodiode 101 via the summing capacitor 102 . At the end of this integration cycle, switch SW3 is closed and the combined optical signal is sampled and stored in capacitor C3. After switch SW3 is turned on, switch SW4 is turned off, and the reset voltage stored on C2 is transferred to capacitor C4. The photodiode 101 and the amplifier A1 are reset again to start the next integration cycle. This process repeats until it reaches the final time delay and integration stage 200, as shown in FIG. 2 .

The scan of the shift register 10 is then initiated by the start pulse SI, and the signal is read from a linear array of M pixels similar to a standard photodiode array. When a pixel is addressed by the output SM of the scan register 10, the pixel's reset and light signal voltages are diverted to a correlated double sample and hold output differential amplifier 20 for video processing. A gain stage 30 can be added to increase the signal level. Thus, a single-ended video signal is obtained, as shown in FIG. 4 .

Figure 5 shows a circuit diagram of another preferred embodiment of the present invention to illustrate a time delay and integration stage. The only difference between the circuits in FIG. 1 and FIG. 5 is that the functions of the integrating and summing amplifier 103 in FIG. 1 are replaced by the integrating amplifier 60 and the summing amplifier 70 in FIG. 5 . The correlated double sampling and holding circuits in FIG. 1 and FIG. 5 are the same. The integrating amplifier 60 includes: an amplifier A1a, an integrating capacitor C1a, and a reset switch SW1a. The function of the integrating amplifier 60 is to reset the photodiode 101 and integrate the light signal in the integrating capacitor C1a. The summing amplifier 70 includes: an amplifier A1b, an integrating capacitor C1b, and a reset switch SW1b. The function of summing amplifier 70 is to add the reset and photovoltage of photodiode 101 via summing capacitor 61 to the reset and photovoltage received from the previous time delay and integration stage via summing capacitor 62 .

Correlated double sample and hold circuit 104 then performs the same sample-and-hold function as explained above. The timing diagram in Figure 4 needs to be modified slightly to facilitate the separation of the integrating function from the summing function.

As shown in FIGS. 1 and 4, the correlated double sample and hold circuit 104 uses two parallel independent storage circuits to transmit the reset signal and the optical signal. Alternatively, a chain of storage circuits can be used, and the reset signal and optical signal can be sent through the chain one at a time. The advantage of using a single chain storage circuit is that the reset voltage has the same offset as the optical signal caused by the buffer amplifier. Therefore, this deviation can be completely removed by later time delays and integration stages.

In yet another preferred embodiment of the present invention, the time delay and integration stages shown in FIG. 1 can be operated alternately in the timing sequence shown in FIG. 6 . In this mode of operation, the difference between the reset signal and the light signal may first be obtained before being added to the light signal of the photodiode 101 in the storage correlated double sample and hold circuit 104 . The accumulated light signal can then be sampled and held in capacitor C3, and the reset signal of photodiode 101 can also be sampled and held in capacitor C2 without being combined with the reset signal of the previous time delay and integration stage. Therefore, the advantages of the present invention can be maintained for the two operation modes represented by the timing diagrams in FIGS. 4 and 6 .

Similarly, the new mode of operation represented by FIG. 6 can also be applied to the time delay and integration circuit in FIG. 5 with a slight timing modification, so as to facilitate the separation of the integrating and summing functions.

The preferred embodiments described above are only examples of the present invention, and various changes can be derived from the present invention.

Claims (24)

1. a complementary metal oxide semiconductors (CMOS) time delay and integration type sensor, it is characterised in that including:

One integration with add up amplifier, it has an integration input terminal, switch reseted by the totalling input terminal that can engage with described integration input terminal or separate, a lead-out terminal, an integrating condenser and;

One optical detector, is connected to described integration and the described integration input terminal adding up amplifier;

One adds up capacitor, and its first electrode is connected to the output of previous time delay and integration stages, and its second electrode is connected to described integration and adds up the described totalling input terminal of amplifier;

One correlated double sampling and holding circuit, it includes multiple switch and multiple storage circuits, described correlated double sampling and holding circuit have an input terminal and are connected to described integration and add up the described lead-out terminal of amplifier, and described correlated double sampling has a lead-out terminal with holding circuit and is connected to the described totalling capacitor of time delay and integration stages thereafter; And

Wherein, first pass through and described switch of reseting cuts out, described integration is reset with adding up amplifier, and when described reset switch later on time, by described optical detector reset signal and the signal of reseting being stored in described previous time delay with the correlated double sampling of integration stages and holding circuit adds assembly one combination and resets signal, and sampled at once by described correlated double sampling and holding circuit and kept;Then described integration starts the optical signal integration of described optical detector with adding up amplifier, and the integral light signal of described optical detector is added assembly one combination optical signal with being stored in the described previous time delay described correlated double sampling with integration stages with the described optical signal in holding circuit simultaneously, and sampled by described correlated double sampling and holding circuit and keep; And described combination optical signal resets signal with described combination and is maintained at described correlated double sampling and in holding circuit, is ready for being sent to later described time delay and integration stages.

2. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 1 and integration type sensor, it is characterised in that described integration includes one or more level with adding up amplifier.

3. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 1 and integration type sensor, it is characterized in that, described integration input terminal and described totalling input terminal are bonded into an input terminal, and wherein said integration has one first electrode with the described integrating condenser adding up amplifier and is connected to described input terminal, and one second electrode is connected to described lead-out terminal.

4. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 3 and integration type sensor, it is characterised in that described integration is an analogue amplifier with totalling amplifier, has single or differential input.

5. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 1 and integration type sensor, it is characterized in that, described integration has a two-stage amplifier with adding up amplifier, described optical signal integration implemented by its first order amplifier, and amplifier enforcement in the second level adds general function, and the input of described first order amplifier becomes described integration and adds up the integration input terminal of amplifier, the input of described second level amplifier is connected to the output of described first order amplifier, and become described integration and the described totalling input terminal adding up amplifier, and the described lead-out terminal being output into described integration and totalling amplifier of described second level amplifier.

6. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 5 and integration type sensor, it is characterized in that, described first order amplifier is analogue amplifier, there is single or differential input, and one first electrode of described integrating condenser is connected to described integration input terminal, and one second electrode of described integrating condenser is connected to the output of described first order amplifier.

7. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 5 and integration type sensor, it is characterized in that, described second level amplifier is an analogue amplifier, there is single or differential input, and have more an additional capacitor, one first electrode of described additional capacitor is connected to the input of described second level amplifier, and one second electrode of described additional capacitor is connected to the output of described second level amplifier.

8. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 1 and integration type sensor, it is characterised in that described optical detector has a light sensitive diode, and it can convert light to electric current.

9. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 1 and integration type sensor, it is characterised in that the described storage circuit of described correlated double sampling and holding circuit has a reservior capacitor and a buffer amplifier.

10. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 1 and integration type sensor, it is characterized in that, it is transmit abreast in the described correlated double sampling independent storage circuit with holding circuit that described combination resets signal with described combination optical signal.

11. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 1 and integration type sensor, it is characterised in that it is transmit in the single chain of described storage circuit that described combination resets signal with described combination optical signal; And described combination reseted signal and transmitted one at a time by each described storage circuit with described combination optical signal.

12. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 1 and integration type sensor, it is characterized in that, described optical detector, described integration is integrated on an one chip with adding up amplifier and described correlated double sampling with holding circuit, and plurality of described integration with add up amplifier, described correlated double sampling is physically isolated with holding circuit and multiple described optical detectors, so that multiple described integrations and totalling amplifier, described correlated double sampling and holding circuit can be shielded from harmful width in receiving light line process and penetrate, and multiple described optical detector is exposed to harmful width penetrates.

13. a complementary metal oxide semiconductors (CMOS) time delay and integration type sensor, it is characterised in that including:

One integration with add up amplifier, it has an integration input terminal, switch reseted by the totalling input terminal that can engage with described integration input terminal or separate, a lead-out terminal, an integrating condenser and;

One optical detector, is connected to described integration and the described integration input terminal adding up amplifier;

One adds up capacitor, and its first electrode is connected to the output of previous time delay and integration stages, and its second electrode is connected to described integration and adds up the described totalling input terminal of amplifier;

One correlated double sampling and holding circuit, it includes multiple switch and multiple storage circuits, described correlated double sampling and holding circuit have an input terminal and are connected to described integration and add up the described lead-out terminal of amplifier, and described correlated double sampling has a lead-out terminal with holding circuit and is connected to the described totalling capacitor of time delay and integration stages thereafter; And

Wherein, first pass through and described switch of reseting cut out, described integration is reset with adding up amplifier, and when described reset switch later on time, described correlated double sampling and holding circuit reseted sample of signal and maintenance by producing; Then described integration starts the optical signal integration of described optical detector with adding up amplifier, and produce an accumulating signal, its integral light signal being described optical detector and reset the summation of the difference of signal with the described correlated double sampling in described previous time delay with integration stages with institute's maintenance in holding circuit with institute's maintenances prior cumulative signal in holding circuit at the described correlated double sampling of described previous time delay and integration stages, described accumulating signal is sampled and maintenance by described correlated double sampling and holding circuit; And described accumulating signal and described signal of reseting are maintained at described correlated double sampling and in holding circuit, are ready for being sent to later described time delay and integration stages.

14. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 13 and integration type sensor, it is characterised in that described integration includes one or more level with adding up amplifier.

15. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 13 and integration type sensor, it is characterized in that, described integration input terminal and described totalling input terminal are bonded into an input terminal, and wherein said integration has one first electrode with the described integrating condenser adding up amplifier and is connected to described input terminal, and one second electrode is connected to described lead-out terminal.

16. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 15 and integration type sensor, it is characterised in that described integration is an analogue amplifier with totalling amplifier, has single or differential input.

17. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 13 and integration type sensor, it is characterized in that, described integration has a two-stage amplifier with adding up amplifier, described optical signal integration implemented by its first order amplifier, and amplifier enforcement in the second level adds general function, and the input of described first order amplifier becomes described integration and adds up the integration input terminal of amplifier, the input of described second level amplifier is connected to the output of described first order amplifier, and become described integration and the described totalling input terminal adding up amplifier, and the described lead-out terminal being output into described integration and totalling amplifier of described second level amplifier.

18. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 17 and integration type sensor, it is characterized in that, described first order amplifier is an analogue amplifier, there is single or differential input, and one first electrode of described integrating condenser is connected to described integration input terminal, and one second electrode of described integrating condenser is connected to the output of described first order amplifier.

19. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 17 and integration type sensor, it is characterized in that, described second level amplifier is analogue amplifier, there is single or differential input, and have more an additional capacitor, one first electrode of described additional capacitor is connected to the input of described second level amplifier, and one second electrode of described additional capacitor is connected to the output of described second level amplifier.

20. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 13 and integration type sensor, it is characterised in that described optical detector has a light sensitive diode, and it can convert light to electric current.

21. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 13 and integration type sensor, it is characterised in that the described storage circuit of described correlated double sampling and holding circuit has a reservior capacitor and a buffer amplifier.

22. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 13 and integration type sensor, it is characterised in that described in reset signal with described accumulating signal be transmit abreast in the described correlated double sampling independent storage circuit with holding circuit.

23. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 13 and integration type sensor, it is characterised in that described in reset signal with described accumulating signal be transmit in the single chain of described storage circuit; And described in reset signal and described accumulating signal and transmitted one at a time by each described storage circuit.

24. complementary metal oxide semiconductors (CMOS) time delay as claimed in claim 13 and integration type sensor, it is characterized in that, described optical detector, described integration is integrated on an one chip with adding up amplifier and described correlated double sampling with holding circuit, and plurality of described integration with add up amplifier, described correlated double sampling is physically isolated with holding circuit and multiple described optical detectors, so that multiple described integrations and totalling amplifier, described correlated double sampling and holding circuit can be shielded from harmful width in receiving light line process and penetrate, and multiple described optical detector is exposed to harmful width penetrates.