CN102623383A - Bulk-silicon-based manufacturing method for vertically stacked under-gate type silicon nano-wire metal oxide semiconductor field effect transistor (SiNWFET) - Google Patents
Bulk-silicon-based manufacturing method for vertically stacked under-gate type silicon nano-wire metal oxide semiconductor field effect transistor (SiNWFET) Download PDFInfo
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Abstract
The invention discloses a bulk-silicon-based manufacturing method for a vertically stacked under-gate type silicon nano-wire metal oxide semiconductor field effect transistor (SiNWFET). The method comprises the following steps of: providing a bulk silicon substrate on which SiGe layers and Si layers are alternately grown; photo-etching and etching the SiGe layers and the Si layers to form fin-shaped active regions, and taking the residual SiGe layers and the residual Si layers as source and drain regions; selectively etching and removing the SiGe layers in the fin-shaped active regions to form silicon nano-wires which are vertically stacked; forming a virtual isolation layer on the bulk silicon substrate between the source region and the drain region; forming a gate trench in the virtual isolation layer; forming gate oxide layers on the silicon nano-wires; forming a gate in the gate trench; removing the virtual isolation layer to form an isolated trench; and forming an isolation dielectric layer in the isolated trench. Due to the adoption of the virtual isolation layer, control over the contour of the gate trench is facilitated; the conventional gate oxide layers are adopted; and the silicon nano-wires are vertically stacked, so that the integration level and current driving capability of a device can be improved.
Description
Technical field
The present invention relates to field of semiconductor manufacture, particularly relate to a kind of based on grid type silicon nanowires field-effect transistor (SiNWFET) preparation method after the vertical stack formula of body silicon.
Background technology
In the prior art, through dwindle transistorized size improve chip operating rate and integrated level, to reduce chip power-consumption density be the target that microelectronics industry development is pursued always.In in the past 40 years, Moore's Law is being followed in the microelectronics industry development always.Current; The physical gate of field-effect transistor is long near 20nm; Gate medium also only has several oxygen atom bed thickness; Improve performance through the size of dwindling conventional field effect transistor and faced some difficulties, this mainly is because of short-channel effect under the small size and grid leakage current transistorized switch performance to be degenerated.
(Nanowire MOSFET NWFET) is expected to address this problem nano-wire field effect transistor.On the one hand; Little channel thickness and width make the grid of nano-wire field effect transistor more approach the various piece of raceway groove; Help the enhancing of transistor gate modulation capability, and their mostly adopt and enclose the grid structure, grid is modulated raceway groove from a plurality of directions; Further the enhanced modulation ability is improved the subthreshold value characteristic.Therefore, nano-wire field effect transistor can suppress short-channel effect well, makes transistor size be able to further dwindle.On the other hand, nano-wire field effect transistor utilizes the rill road of self and encloses the grid structure and improve the grid modulation forces and suppress short-channel effect, has alleviated the requirement of attenuate grid medium thickness, is expected to reduce grid leakage current.In addition, nanowire channel can undope, and has reduced impurity discrete distribution and Coulomb scattering in the raceway groove.For the 1-dimention nano wire channel, because quantum limitation effect, charge carrier so carrier transport receives surface scattering and channel laterally influence little, can obtain higher mobility away from surface distributed in the raceway groove.Based on above advantage, nano-wire field effect transistor more and more receives scientific research personnel's concern.Because silicon materials and technology are occupied dominant position in semi-conductor industry, compare the easier and current process compatible of the making of silicon nanowires field-effect transistor (SiNWFET) with other materials.
The critical process of nano-wire field effect transistor is the making of nano wire, can be divided into from top to bottom and two kinds of process routes from bottom to top.Making for silicon nanowires; The former mainly utilizes photoetching (optical lithography or electron beam lithography) and etching (ICP, RIE etching or wet etching) technology; The latter is mainly based on gas-liquid-solid (VLS) growth mechanism of metal catalytic, in the growth course with catalyst granules as nucleating point.At present; The silicon nanowires of process route preparation from bottom to top not too is fit to the preparation of silicon nanowires field-effect transistor owing to its randomness, the silicon nanowires in the therefore present silicon nanowires field-effect transistor mainly is through top-down process route preparation.
At present; Field-effect transistor (MOSFET) its preparation process research based on single silicon nanowires is relatively more popular; Like application number is 200710098812.4, and denomination of invention is the Chinese patent of " a kind of preparation method of bulk silicon nano line transistor device ", discloses a kind of process that top-down approach realizes the bulk silicon nano line structure of passing through based on body silicon; Because its process characteristic, the effectively self-heating effect of suppression device based on body silicon.
But along with dwindling of silicon nanowires sectional area; The current driving ability of device can receive the restriction of nano wire sectional area; Make the application of silicon nanowires field-effect transistor in simulation or radio circuit be restricted; Therefore, the someone begins one's study and adopts many nano wires as transporting raceway groove, to address this problem.But because many nanowire channel structures are laterally preparations, its integration density will be had a greatly reduced quality.
People such as W.W.Fang are at IEEE ELECTRON DEVICE LETTERS; VOL.28; NO.3 has proposed a kind of vertical method for preparing silicon nanowires in the paper of delivering on the MARCH 2007 " Vertically Stacked SiGe Nanowire Array Channel CMOS Transistors ", makes the silicon nanowires FET device at vertical integrated many silicon nanowires; Thereby make the current driving ability of device increase exponentially, integration density is unaffected simultaneously.Not only can keep the advantage of planar structure field-effect transistor (FET) but also strengthened the grid modulation capability.Its process is to go up alternately growth (Ge/Si Ge)/Si/ (Ge/SiGe)/Si layer at SOI (Silicon on Insulator); And define fin-shaped (Fin) structure above that; Carry out 750 ℃ of dry-oxygen oxidations then; Because the SiGe layer has faster oxidation rate so that SiGe layer oxidized fully than the Si layer, Ge gets into contiguous Si laminar surface and forms the SiGe alloy in the oxidizing process, erodes and obtains three-dimensional pile up, Si nano wire that the surface is wrapped with the SiGe alloy behind the oxidized fully SiGe layer.Carry out thermal oxidation then, form Si on silicon nanowires (SiNW) surface
1-XGe
XO
2As grid oxic horizon, unformed silicon of deposit or polysilicon form grid through photoetching and etching at last again.This method can realize vertical stack type silicon nanowires field-effect transistor structure, but has a shortcoming: in SiGe layer oxidizing process, Ge can be concentrated to the surface of Si layer, behind the removal SiO2, is wrapped with the SiGe alloy after one deck concentrates at surface of silicon nanowires.Because GeO2 is water-soluble, it makes subsequent technique face huge inconvenience, and in addition, the dielectric constant of GeO2 is little than SiO2, and the interfacial state of GeO2 and Si is bigger, is not suitable for the gate oxide as field-effect transistor (FET).
Summary of the invention
The object of the present invention is to provide a kind of based on grid type SiNWFET preparation method after the vertical stack formula of body silicon; Can effectively control gate profile and device is electrical; Effectively increase integrated level and the device current driving force of SiNWFET, and realize the conventional grid oxic horizon structure of silicon nanowires field-effect transistor.
For solving the problems of the technologies described above, the invention provides a kind ofly based on grid type SiNWFET preparation method after the vertical stack formula of body silicon, comprise the following steps:
The one silicon substrate is provided, and alternately growing on the said body silicon substrate has SiGe layer and Si layer;
Said SiGe layer and Si layer are carried out photoetching and etching, form the fin-shaped active area, remaining SiGe layer and Si layer are as source-drain area;
Remove the SiGe layer in the said fin-shaped active area through selective etch, form silicon nanowires, said silicon nanowires vertical stack;
On the body silicon substrate between the said source-drain area, form virtual separator;
In said virtual separator, form gate trench;
On said silicon nanowires, form grid oxic horizon;
In said gate trench, form grid;
Remove virtual separator, form isolated groove;
In said isolated groove, form the spacer medium layer.
Described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, the nearest one deck of the said body silicon substrate of distance is the SiGe layer, also is the SiGe layer apart from body silicon substrate one deck farthest.
Optional, described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, said SiGe layer and Si layer are carried out ion being carried out in the zone between the said source-drain area injecting before photoetching and the etching.
Optional, described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, said SiGe layer and Si layer are carried out said source-drain area being carried out ion injecting before photoetching and the etching.
Optional, described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, form on the body silicon substrate between said source-drain area after the virtual separator, said source-drain area is carried out ion injects.
Described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, said selective etch adopts time normal pressure chemical gas phase etching method.
Described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method; Said time normal pressure chemical gas phase etching method adopts hydrogen and chlorine hydride mixed gas body; Wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 ℃～800 ℃, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
Described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, said silicon nanowires diameter is between 1 nanometer～1 micron.
Described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, the cross sectional shape of said silicon nanowires is circular, laterally track shape or vertical track shape.
Described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, before forming virtual separator on the body silicon substrate between the said source-drain area, also comprise:
Said silicon nanowires is carried out thermal oxidation;
Etch away the silicon dioxide that said thermal oxidation forms.
Preferably, described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, the material of said virtual separator is an amorphous carbon.
Preferable, described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, on said silicon nanowires, form in the grid oxic horizon step and adopt technique for atomic layer deposition.
Described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, the material of said grid oxic horizon is silicon dioxide, silicon oxynitride or high K dielectric layer.
Described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, said high K dielectric layer is a kind of or its combination in any among HfO2, Al2O3, the ZrO2.
Described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, the material of said grid is a kind of or its combination in any in polysilicon, amorphous silicon, the metal.
Described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, before removing virtual separator, the upper surface of said source-drain area and said grid is carried out autoregistration silicon, germanium silicon metal alloy technology.
Described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, the material of said spacer medium layer is a silicon dioxide.
Preferable, described based on the vertical stack formula of body silicon after among the grid type SiNWFET preparation method, in said isolated groove, form in the spacer medium layer step, form interlayer dielectric layer simultaneously.
Grid type silicon nanowires field-effect transistor structure has the following advantages after the present invention is based on the vertical stack formula of body silicon:
1, based on body silicon, silicon nanowires field-effect transistor source-drain area is connected with the body silicon substrate, and a large amount of heats that device produces in the course of the work can effectively be passed to the body silicon substrate through source-drain area and shed, thereby do not have self-heating effect.
2, adopt virtual spacer processes, in virtual separator, form gate trench, be beneficial to the control of gate trench profile; In gate trench, form grid again, be the back grid technique, and do not have side wall technology; Simplify technological process, in isolated groove, formed the spacer medium layer at last, be the back spacer processes; Further; Be beneficial to the profile control and the electrical control of device of grid and spacer medium layer, and can make source-drain area and spacer medium layer and gate upper surface, be beneficial to follow-up contact hole technology at same horizontal plane.
3, on silicon nanowires, forming the gate oxidation layer process is independently to carry out, thereby can adopt conventional grid oxic horizon, gets final product like silicon dioxide;
4, adopt vertical stack formula silicon nanowire structure to come design of Si nano-wire field effect transistor (SiNWFET) structure, vertical stack formula structure increases the device integrated level, and the nanometer number of lines increases, thereby the device current driving force is also increased.
Description of drawings
Fig. 1 is based on grid type SiNWFET preparation method flow chart after the vertical stack formula of body silicon in one embodiment of the invention;
Fig. 2 is that the X-X ' of body silicon substrate in one embodiment of the invention is to generalized section;
Fig. 3 for the X-X ' that ion implantation technology carried out in the zone between the source-drain area in one embodiment of the invention to generalized section;
Fig. 4 a and Fig. 4 b be respectively in one embodiment of the invention fin-shaped active area X-X ' to and Y-Y ' to generalized section;
Fig. 5 a and Fig. 5 b be respectively in one embodiment of the invention the fin-shaped active area X-X ' that removes behind the SiGe layer to and Y-Y ' to generalized section;
Fig. 6 is the schematic perspective view that forms nano wire in one embodiment of the invention;
Fig. 7 is the cross sectional shape sketch map of silicon nanowires in one embodiment of the invention;
Fig. 8 a and Fig. 8 b be in one embodiment of the invention the deposition amorphous carbon after X-X ' to and Y-Y ' to generalized section;
Fig. 9 a and Fig. 9 b be respectively in one embodiment of the invention to amorphous carbon carry out behind the cmp X-X ' to and Y-Y ' to generalized section;
Figure 10 for the X-X ' that source-drain area carried out ion implantation technology in one embodiment of the invention to generalized section;
Figure 11 a and Figure 11 b be respectively in one embodiment of the invention the X-X ' that forms behind the gate trench to and Y-Y ' to generalized section;
Figure 11 c is the schematic perspective view behind the formation gate trench in one embodiment of the invention;
Figure 12 a and Figure 12 b be respectively in one embodiment of the invention the X-X ' that forms behind the grid oxic horizon to and Y-Y ' to generalized section;
Figure 13 a and Figure 13 b be respectively in one embodiment of the invention the X-X ' after the deposition of gate material to and Y-Y ' to generalized section;
Figure 14 a and Figure 14 b be respectively in one embodiment of the invention to grid material carry out behind the cmp X-X ' to and Y-Y ' to generalized section;
Figure 15 a and Figure 15 b be respectively the X-X ' that carries out autoregistration silicon, germanium silicon metal alloy (Salicidation) technology in one embodiment of the invention to and Y-Y ' to generalized section;
Figure 15 c is the schematic perspective view that carries out in one embodiment of the invention after autoregistration silicon, germanium silicon metal alloy (Salicidation) technology
Figure 16 a and Figure 16 b be respectively in one embodiment of the invention through cineration technics remove behind the amorphous carbon X-X ' to and Y-Y ' to generalized section;
Figure 16 c is through the schematic perspective view behind the cineration technics removal amorphous carbon in one embodiment of the invention;
Figure 17 a and Figure 17 b be respectively in one embodiment of the invention the X-X ' behind the deposit medium to and Y-Y ' to generalized section;
Figure 17 c is the schematic perspective view behind the deposit medium in one embodiment of the invention;
Figure 18 a and Figure 18 b be respectively in one embodiment of the invention the X-X ' that forms after source electrode connector, gate plug and the drain plug to and Y-Y ' to generalized section;
Figure 18 c is the schematic perspective view after formation source electrode connector, gate plug and the drain plug in one embodiment of the invention;
Figure 19 is a grid type silicon nanowires field-effect transistor structure schematic top plan view after the vertical stack formula in one embodiment of the invention.
Embodiment
For make above-mentioned purpose of the present invention, feature and advantage can be more obviously understandable, does detailed explanation below in conjunction with the accompanying drawing specific embodiments of the invention.
At first, shown in figure 19, for clearer description present embodiment, the length direction of the silicon nanowires 6 of definition fin-shaped active area 5 or follow-up formation is X-X ' to, X-X ' to running through grid 10 and source-drain area 17, perpendicular to X-X ' to be Y-Y ' to.Manufacture method below in conjunction with the detailed description one embodiment of the invention of Fig. 1 to Figure 19 based on grid type SiNWFET after the vertical stack formula of body silicon.
As shown in Figure 1, the manufacture method based on grid type SiNWFET after the vertical stack formula of body silicon of one embodiment of the invention comprises the steps:
As shown in Figure 2, one silicon substrate 1 is provided, alternately growing on the body silicon substrate 1 has SiGe layer 3 and Si layer 2; The quantity of supposing Si layer 2 is the n layer, and then the quantity of SiGe layer 3 is the n+1 layer, wherein; N >=1; That is, (below) epitaxial loayer nearest apart from body silicon substrate 1 is SiGe layer 3, also is SiGe layer 3 apart from body silicon substrate 1 (the top) epitaxial loayer farthest.Owing to the present invention is based on body silicon, silicon nanowires field-effect transistor source-drain area 17 is connected with body silicon substrate 1, and a large amount of heats that device produces in the course of the work can effectively be passed to body silicon substrate 1 through source-drain area 17 and shed, thereby do not have self-heating effect.In the present embodiment, be example with four layers of SiGe layer of alternating growth and three layers of Si layer.
As shown in Figure 3, ion is carried out in the zone between the source-drain area inject, the channel region that is field-effect transistor mixes.Concrete; This step can realize through following process: at first on SiGe layer 3, form patterned photoresist layer 4 through photoetching (Photo) technology; Be that mask carries out ion injection (Imp) technology then with patterned photoresist layer 4; Then, remove said patterned photoresist layer 4 (PR Strip), carry out trap annealing (Well Anneal) technology subsequently.Need to prove that this step is an optional step, electrically require to omit under the permission situation according to device.
As shown in Figs. 4a and 4b, SiGe layer 3 and Si layer 2 are carried out photoetching and etching, form fin-shaped active area 5, remaining SiGe layer 3 and Si layer 2 are as source-drain area 17.Preferable, can adopt optical lithography (Photolithography) or electron beam lithography (electron beam lithography), etching runs through all epitaxy Si Ge layers 3 and Si layer 2, until the surface that exposes body silicon substrate 1.
Shown in Fig. 5 a and 5b, remove the SiGe layer 3 in the fin-shaped active area 5 through selective etch; Preferably, utilize time normal pressure chemical gas phase etching method to carry out selective etch, temperature can adopt 600 ℃～800 ℃, and etching gas is selected the mist of H2 and HCl for use, and wherein the dividing potential drop of HCl is greater than 300Torr.This selective etch step will be till will all etching away along the SiGe layer 3 between the Si layer 2 of Y-Y ' direction; Remaining Si layer 2 is as silicon nanowires 6; Silicon nanowires 6 vertical stacks, and make SiGe layer 3 part of X-X ' direction keep are with as source-drain area 17.Optional, before this step, also can carry out ion implantation technology to source-drain area 17 earlier.
As shown in Figure 6, silicon nanowires 6 is optimized and subtracts thin.This step can be passed through thermal oxidation technology, and oxidation is carried out on silicon nanowires 6, body silicon substrate 1 and source-drain area 17 surfaces.Further, if described thermal oxidation is furnace oxidation (Furnace Oxidation), then the oxidization time scope is 1 minute to 20 hours; If rapid thermal oxidation (RTO), then the oxidization time scope is 1 second to 30 minutes.Remove the silicon dioxide that above-mentioned steps forms through wet-etching technology on silicon nanowires 6, body silicon substrate 1 and source-drain area 17 surfaces then.Silicon nanowires 6 diameters that form at last are between 1 nanometer～1 micron.It is understandable that; Thickness and fin-shaped active area 5 lateral dimensions according to Si layer 2 vary in size; Silicon nanowires 6 cross sectional shapes also can be different; For example, silicon nanowires 6 cross sectional shapes can be the vertical track shape shown in circle, the horizontal track shape shown in the centre or the rightmost side shown in the leftmost side among Fig. 7.If, can more accurately control fin-shaped active area (Fin) physical dimension so through more advanced figure transfer technology, thus the Shape optimization that more helps silicon nanowires 6 with subtract carefully, and can accurately control the diameter of silicon nanowires 6.
Shown in Fig. 8 a and Fig. 8 b, form virtual separator in the body silicon substrate 1 between source-drain area 17, preferred; The material of virtual separator is an amorphous carbon 7 '; Amorphous carbon 7 ' has high etching selection ratio and high absorptive, is beneficial to the gate trench 8 profiles control of follow-up formation, and amorphous carbon 7 ' ashing easily after the back grid technique is accomplished; Optional, adopt chemical gaseous phase depositing process to carry out the deposition of amorphous carbon 7 '.Need to prove; Present embodiment adopts the material of amorphous carbon 7 ' as virtual separator; But the present invention is not limited thereto; Conspicuous, as long as the material of virtual separator has high etching selection ratio and the performance of removing easily, so just can be used as the material of the virtual separator of the present invention.
Because the existence of amorphous carbon among the present invention, all correlation step from Fig. 8 A to 15C can not occur all that dry method is removed photoresist and cineration technics, and need to adopt wet processing, with the pattern of protection amorphous carbon in this process.
Shown in Fig. 9 a and Fig. 9 b, adopt chemical mechanical milling tech, remove unnecessary amorphous carbon 7 ', make remaining amorphous carbon 7 ' as amorphous carbon layer 7; The upper surface of amorphous carbon layer 7 and SiGe layer 3 carries out ion implantation technology thereby convenience is follow-up to source-drain area 17 at same horizontal plane.
Shown in figure 10, be mask with patterned photoresist layer 4, source-drain area 17 is carried out ion implantation technology; Concrete; This step can realize through following process: at first on SiGe layer 3 and amorphous carbon layer 7 upper surfaces, form patterned photoresist layer 4 through photoetching (Photo) technology; Be that mask carries out ion injection (Imp) technology then with patterned photoresist layer 4; Then, remove said patterned photoresist layer 4 (PR Strip), carry out source-drain electrode annealing (S/D Anneal) technology subsequently.Need to prove that this step can be carried out before fin-shaped active area 5 graphical definition, also can carry out afterwards through cmp (CMP) at amorphous carbon 7 '.
Shown in Figure 11 a, Figure 11 b and Figure 11 c, amorphous carbon layer 7 is carried out photoetching and etching technics, form gate trench 8.Concrete, can adopt hard mask or photo-resistive mask in the said photoetching process, amorphous carbon layer 7 is carried out photoetching and the surface of etching until exposure body silicon substrate 1.Owing to adopted amorphous carbon as the virtual separator in the grid technique of back with high etching selection ratio and high absorptive; Be beneficial to the control of gate trench 8 profiles; Further; Be more conducive to the profile control and the electrical control of device of the grid 10 and the spacer medium layer 12 of follow-up formation, and amorphous carbon ashing easily after the back grid technique is accomplished.
Shown in Figure 12 a and 12b; On body silicon substrate 1 between amorphous carbon layer 7, silicon nanowires 6 and the source-drain area 17 and SiGe layer 3 upper surface, form grid oxic horizon 9; Said grid oxic horizon 9 can be SiO2, SiON or high K dielectric layer, and said high K dielectric layer for example is a kind of or its combination in any among HfO2, Al2O3, the ZrO2.Preferably, adopt ald (ALD) deposition techniques silicon dioxide, thereby can form conventional grid oxic horizon 9, and the grid oxic horizon 9 of shape will become the separator of subsequent gate 10 and body silicon substrate 1 on the body silicon substrate 1 between the source-drain area 17.
Shown in Figure 13 a and 13b; Deposition of gate material 10 ' in SiGe layer 3 upper surface and gate trench 8, said grid material 10 ' can be a kind of or its combination in any in polysilicon, amorphous silicon, the metal (being preferably the metallic compound of aluminium or titanium or tantalum).
Shown in Figure 14 a and Figure 14 b, adopt chemical mechanical milling tech, remove unnecessary grid material 10 ', make remaining grid material 10 ' as grid 10; The upper surface of grid 10 and amorphous carbon layer 7 and SiGe layer 3 is at same horizontal plane.This step is being carried out after the source-drain area ion injects, and carries out the formation technology of grid again, is the back grid technology, thereby helps the control of grid 10 profiles and device is electrically controlled.
Shown in Figure 15 a, Figure 15 b and Figure 15 c, carry out autoregistration alloy (Salicidation) technology, form silicon, germanium silicon metal alloy layer 11.
Shown in Figure 16 a, Figure 16 b and 16c, remove amorphous carbon layer 7 through cineration technics (Ashing), form isolated groove 12 ', make things convenient for subsequent deposition spacer medium layer 12.
Shown in Figure 17 a, Figure 17 b and 17c, deposit medium in the upper surface of SiGe layer 3 and isolated groove 12 '; The spacer medium of deposition is as the spacer medium layer 12 between source-drain area 17 and the grid 10 in isolated groove 12 '; After the spacer medium of the upper surface of SiGe layer 3 deposition carried out planarization; As adopt cmp (CMP) technology; This layer is as inter-level dielectric (ILD) layer 13, and spacer medium is generally silicon dioxide.Because autoregistration silicon alloy technology is accomplished, this two-layer can deposition simultaneously, this also is an effect adopting virtual (Dummy) separator, has simplified technology.
Shown in Figure 18 a, Figure 18 b and 18c, form source electrode connector 14, gate plug 15 and drain plug 16 through the metal interconnected technology in road, back, with source electrode, grid and the drain electrode of drawing field-effect transistor (FET) respectively.
Finally, please refer to Figure 18 c and Figure 19, it is schematic perspective view and schematic top plan view based on grid type SiNWFET after the vertical stack formula of body silicon after last the completion.
In sum, the present invention is based on the vertical stack formula of body silicon after grid type silicon nanowires field-effect transistor structure have the following advantages:
1, based on body silicon, silicon nanowires field-effect transistor source-drain area 17 is connected with body silicon substrate 1, and a large amount of heats that device produces in the course of the work can effectively be passed to body silicon substrate 1 through source-drain area 17 and shed, thereby do not have self-heating effect.
2, adopt have high etching selection ratio and high absorptive amorphous carbon 7 ' as the virtual separator in the grid technique of back, be beneficial to the control of gate trench 8 profiles, and amorphous carbon 7 ' in the back grid technique accomplish the easy ashing in back; Source-drain area 17 is carried out the ion injection, in amorphous carbon layer 7, formed gate trench 8, in gate trench 8, formed grid 10 again; Be the back grid technique, and do not have side wall technology, simplified technological process; Carry out the deposition of spacer medium layer 12 at last; Be the back spacer processes, further, be more conducive to the profile control and the electrical control of device of grid 10 and spacer medium layer 12; And make source-drain area 17 and spacer medium layer 12 and grid 10 upper surfaces at same horizontal plane, be beneficial to follow-up contact hole technology.
3, on silicon nanowires 6, forming grid oxic horizon 9 technologies is independently to carry out, thereby can adopt conventional grid oxic horizon, gets final product like silicon dioxide.
4, adopt vertical stack formula silicon nanowire structure to come design of Si nano-wire field effect transistor (SiNWFET) structure, vertical stack formula structure increases the device integrated level, and the nanometer number of lines increases, thereby the device current driving force is also increased.
Obviously, those skilled in the art can carry out various changes and modification to the present invention and not break away from the spirit and scope of the present invention.Like this, belong within the scope of claim of the present invention and equivalent technologies thereof if of the present invention these are revised with modification, then the present invention also is intended to comprise these changes and modification interior.
Claims (18)
1. one kind based on grid type SiNWFET preparation method after the vertical stack formula of body silicon, it is characterized in that, comprising:
The one silicon substrate is provided, and alternately growing on the said body silicon substrate has SiGe layer and Si layer;
Said SiGe layer and Si layer are carried out photoetching and etching, form the fin-shaped active area, remaining SiGe layer and Si layer are as source-drain area;
Remove the SiGe layer in the said fin-shaped active area through selective etch, form silicon nanowires, said silicon nanowires vertical stack;
On the body silicon substrate between the said source-drain area, form virtual separator;
In said virtual separator, form gate trench;
On said silicon nanowires, form grid oxic horizon;
In said gate trench, form grid;
Remove said virtual separator, form isolated groove;
In said isolated groove, form the spacer medium layer.
2. as claimed in claim 1ly it is characterized in that the nearest one deck of the said body silicon substrate of distance is the SiGe layer, also is the SiGe layer apart from body silicon substrate one deck farthest based on grid type SiNWFET preparation method after the vertical stack formula of body silicon.
3. as claimed in claim 1ly it is characterized in that, said SiGe layer and Si layer are carried out ion being carried out in the zone between the said source-drain area injecting before photoetching and the etching based on grid type SiNWFET preparation method after the vertical stack formula of body silicon.
4. as claimed in claim 1ly it is characterized in that, said SiGe layer and Si layer are carried out said source-drain area being carried out ion injecting before photoetching and the etching based on grid type SiNWFET preparation method after the vertical stack formula of body silicon.
5. as claimed in claim 1ly it is characterized in that, form on the body silicon substrate between said source-drain area after the virtual separator, said source-drain area is carried out ion inject based on grid type SiNWFET preparation method after the vertical stack formula of body silicon.
6. as claimed in claim 1ly it is characterized in that said selective etch adopts time normal pressure chemical gas phase etching method based on grid type SiNWFET preparation method after the vertical stack formula of body silicon.
7. as claimed in claim 6 based on grid type SiNWFET preparation method after the vertical stack formula of body silicon; It is characterized in that; Said time normal pressure chemical gas phase etching method adopts hydrogen and chlorine hydride mixed gas body; Wherein the temperature of hydrogen and chlorine hydride mixed gas body is between 600 ℃～800 ℃, and wherein the dividing potential drop of hydrogen chloride is greater than 300Torr.
8. as claimed in claim 1ly it is characterized in that said silicon nanowires diameter is between 1 nanometer～1 micron based on grid type SiNWFET preparation method after the vertical stack formula of body silicon.
9. as claimed in claim 1ly it is characterized in that the cross sectional shape of said silicon nanowires is circular, laterally track shape or vertical track shape based on grid type SiNWFET preparation method after the vertical stack formula of body silicon.
10. as claimed in claim 1ly it is characterized in that, before forming virtual separator on the body silicon substrate between the said source-drain area, also comprise based on grid type SiNWFET preparation method after the vertical stack formula of body silicon:
Said silicon nanowires is carried out thermal oxidation;
Etch away the silicon dioxide that said thermal oxidation forms.
11. as claimed in claim 1 based on grid type SiNWFET preparation method after the vertical stack formula of body silicon, it is characterized in that the material of said virtual separator is an amorphous carbon.
12. as claimed in claim 1ly it is characterized in that, on said silicon nanowires, form in the grid oxic horizon step and adopt technique for atomic layer deposition based on grid type SiNWFET preparation method after the vertical stack formula of body silicon.
13. as claimed in claim 1ly it is characterized in that based on grid type SiNWFET preparation method after the vertical stack formula of body silicon the material of said grid oxic horizon is silicon dioxide, silicon oxynitride or high K dielectric layer.
14. as claimed in claim 13ly it is characterized in that based on grid type SiNWFET preparation method after the vertical stack formula of body silicon said high K dielectric layer is a kind of or its combination in any among HfO2, Al2O3, the ZrO2.
15. as claimed in claim 1ly it is characterized in that based on grid type SiNWFET preparation method after the vertical stack formula of body silicon the material of said grid is a kind of or its combination in any in polysilicon, amorphous silicon, the metal.
16. as claimed in claim 1ly it is characterized in that, before removing virtual separator, the upper surface of said source-drain area and said grid carried out autoregistration silicon, germanium silicon metal alloy technology based on grid type SiNWFET preparation method after the vertical stack formula of body silicon.
17. as claimed in claim 1 based on grid type SiNWFET preparation method after the vertical stack formula of body silicon, it is characterized in that the material of said spacer medium layer is a silicon dioxide.
18. as claimed in claim 1ly it is characterized in that based on grid type SiNWFET preparation method after the vertical stack formula of body silicon, in said isolated groove, form in the spacer medium layer step, form interlayer dielectric layer simultaneously.
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