CN102623451A - Pixel Array Substrate - Google Patents

Abstract

The invention discloses a pixel array substrate, which comprises a substrate, a plurality of scanning lines, a plurality of data lines, a plurality of common lines, a plurality of capacitors, a plurality of active elements and a plurality of pixel electrodes. The substrate has a surface. The plurality of scanning lines, the plurality of data lines and the plurality of common lines are arranged on the substrate. The capacitors are arranged on the substrate and coupled to the common line, wherein the opposite surfaces of the upper electrodes of the capacitors have undulation. The active elements are disposed on the substrate. The pixel electrodes are disposed on the substrate, wherein each pixel electrode is electrically connected to the corresponding scan line and data line through different active devices.

Description

Pixel Array Substrate

technical field

The present invention relates to a substrate, and in particular to a pixel array substrate.

Background technique

Multimedia technology in today's society is quite developed, mostly benefiting from the progress of semiconductor components and displays. As far as displays are concerned, thin film transistor liquid crystal displays with superior characteristics such as high image quality, low power consumption, and no radiation have gradually become the mainstream of the market.

With people's demand for high resolution of the display, the area of each pixel (pixel) in the display must be reduced, and the area of the components of the display must also be reduced. However, as shown in FIG. 1 , most capacitor designs currently on the market are planar structures. Specifically, by forming a first electrode 112 and a second electrode 116 on the substrate 110, and disposing an insulating layer 114 between the first electrode 112 and the second electrode 116, a capacitor structure is formed, wherein the capacitor structure The charge storage capacity of the capacitor depends on the area occupied by the capacitor relative to the surface of the substrate 110 .

Therefore, like organic light emitting diode (Organic Light Emitting Diode, OLED) display, when the number of thin film transistors corresponding to each pixel is required more, in order to obtain high resolution, it is bound to become very difficult to increase the capacitance plane area, and in If the plane area of the capacitor cannot be reduced, it will be difficult to increase the screen resolution in order to obtain a charge storage capacity that can maintain a normal display screen. On the other hand, displays such as electronic paper (Electronic paper) require a larger capacitance design to maintain the gray scale of the display screen. At this time, due to the requirement of charge storage capacity, the pixel area of the display cannot be reduced. Resolution is limited.

Contents of the invention

The object of the present invention is to provide a pixel array substrate with excellent charge storage capacity.

An embodiment of the present invention provides a pixel array substrate, which includes a substrate, a plurality of scan lines, a plurality of data lines, a plurality of common lines, a plurality of capacitors, a plurality of active elements and a plurality of pixel electrodes. The substrate has a surface. A plurality of scanning lines, a plurality of data lines and a plurality of common lines are arranged on the substrate. A plurality of capacitors are arranged on the substrate and coupled to the common line, wherein the opposite surface of the upper electrode of each capacitor has undulations. Multiple active elements are arranged on the substrate. A plurality of pixel electrodes are disposed on the substrate, and each pixel electrode is electrically connected to corresponding scanning lines and data lines through different active elements.

In an embodiment of the present invention, the maximum height difference between the surfaces of the upper electrodes of the aforementioned capacitors is 50 nanometers to 2000 nanometers.

In an embodiment of the present invention, the cross section of the upper electrodes of the aforementioned capacitors perpendicular to the surface is wavy.

In an embodiment of the present invention, in the aforementioned pixel array substrate, viewed from a direction perpendicular to the surface, the upper electrodes of each capacitor have a plurality of recessed regions parallel to each other.

In an embodiment of the present invention, in the aforementioned pixel array substrate, viewed from a direction perpendicular to the surface, the upper electrodes of each capacitor have a plurality of dot-shaped recessed regions.

In an embodiment of the present invention, the channel of the aforementioned active device is made of low temperature polysilicon or amorphous silicon.

Another embodiment of the present invention provides a pixel array substrate, which includes a substrate, a first insulating layer, a plurality of active elements, a plurality of first signal lines, a plurality of lower electrodes, a plurality of common lines, a first Two insulating layers, a plurality of second signal lines, a plurality of upper electrodes, a third insulating layer and a plurality of pixel electrodes. The first insulating layer is configured on the substrate and has a plurality of grooves. A part of each active element is buried in the first insulating layer or all of them are arranged on the first insulating layer. A plurality of first signal lines, a plurality of lower electrodes and a plurality of common lines are disposed on the first insulating layer. A part of each lower electrode is located in at least one groove, and each common line connects the lower electrodes. The second insulating layer covers the first insulating layer, the first signal line, the lower electrode and the common line, and is located between the gate, the source and the drain of each active element. A plurality of second signal lines and a plurality of upper electrodes are disposed on the second insulating layer, wherein the upper electrodes and the lower electrodes are correspondingly coupled to form a plurality of capacitors. The third insulating layer covers the second insulating layer, the second signal line and the upper electrode, and has a plurality of contact window openings. A plurality of pixel electrodes are arranged on the third insulating layer, and each pixel electrode is electrically connected to the drain of the corresponding active element through a contact window opening.

In an embodiment of the present invention, the depth of each of the aforementioned grooves is 50 nm to 2000 nm.

In an embodiment of the present invention, the section of the aforementioned first insulating layer at the portion having the groove is wavy.

In an embodiment of the present invention, in the aforementioned pixel array substrate, the grooves covered by the respective lower electrodes are strip-shaped grooves parallel to each other.

In an embodiment of the present invention, in the aforementioned pixel array substrate, the grooves covered by each lower electrode are a plurality of dot-shaped grooves.

In an embodiment of the present invention, the channel of the aforementioned active device is made of low temperature polysilicon or amorphous silicon.

In an embodiment of the present invention, each of the aforementioned upper electrodes is electrically connected to the drain of the corresponding active element.

In an embodiment of the present invention, the aforementioned first insulating layer is a single-layer or multi-layer structure.

Based on the above, in the pixel array substrate of the present invention, the area of the capacitor in the direction perpendicular to the substrate is increased, thereby increasing the charge storage capacity. Therefore, when the demand for high resolution makes the pixel size shrink, the area occupied by the capacitor on the substrate can be reduced to achieve the same aperture ratio. That is to say, the charge storage capacity can be increased without sacrificing the aperture ratio. In other words, under the same pixel size, the aperture ratio can be increased to increase the brightness of the display. Or under the same brightness, the brightness of the backlight can be reduced due to the increase of the aperture ratio. On the other hand, while maintaining the same charge storage capacity, the area occupied by the capacitor on the substrate can be reduced, the pixel size can be miniaturized, and the resolution of the display can be improved.

In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail together with the accompanying drawings.

Description of drawings

FIG. 1 is a schematic diagram of a planar capacitor structure in the prior art;

2A to 2G are schematic top views of the manufacturing process of a pixel array substrate according to an embodiment of the present invention;

3 is a schematic top view of a pixel array substrate according to an embodiment of the present invention;

4 is a schematic top view of a pixel array substrate according to another embodiment of the present invention;

5A to 5F are schematic top views of the manufacturing process of a pixel array substrate according to another embodiment of the present invention;

6 is a schematic top view of a pixel array substrate according to an embodiment of the present invention;

FIG. 7 is a schematic top view of a pixel array substrate according to another embodiment of the present invention.

Description of main component symbols

110, 210, 510: substrate

112: first electrode

116: second electrode

114: insulation layer

200, 400, 500, 700: pixel array substrate

212: The first sub-insulation layer

214: second sub-insulation layer

216a, 516: channel

216b: source doped region

216c: Drain doped region

218: The third sub-insulation layer

220, 520: the first insulating layer

222, 522: grid

224, 524: lower electrode

226, 526: scan lines

228, 528: shared line

230, 530: second insulating layer

240, 540: active components

242b, 542b: source

242c, 542c: drain

244, 244’, 544, 544’: upper electrode

246, 546: data line

250, 550: the third insulation layer

260, 560: pixel electrode

518: Ohmic contact pattern

S, S': surface

U, U': Groove

D _U , D _U' : Depth

W1, W2, W3: opening

C1, C2, C3, C4: capacitance

D, D': maximum height difference

A-A': section line

A1, A2, A3, A4: Depressed area

Detailed ways

2A to 2G are schematic cross-sectional views of the manufacturing process of the pixel array substrate according to an embodiment of the present invention.

Referring to FIG. 2A , a first sub-insulation layer 212 and a second sub-insulation layer 214 are sequentially formed on a surface S of a substrate 210 . In this embodiment, the substrate 210 is, for example, a glass substrate, the material of the first sub-insulation layer 212 is, for example, silicon nitride (SiN _x ), and the material of the second sub-insulation layer 214 is, for example, silicon oxide (SiO _x ). But the present invention is not limited thereto.

Referring to FIG. 2B , a channel material layer (not shown) is formed on the second sub-insulation layer 214 . The material of the channel material layer can be low temperature polysilicon or amorphous silicon. In this embodiment, the material of the channel layer is low-temperature polysilicon, wherein the polysilicon may be a material that transforms amorphous silicon into polysilicon by thermal annealing.

Then, the channel material layer is patterned while leaving the portion where the channel is to be laid out. And doping (doping) N-type or P-type dopants to form a source doped region 216b, a drain doped region 216c and a channel 216a not doped with dopants, wherein the channel 216a is configured at the source Between the doped region 216b and the drain doped region 216c. Specifically, if the source doped region 216b and the drain doped region 216c on both sides of the channel 216a are doped with N-type dopants, it is defined as an N-type metal oxide semiconductor (NMOS) transistor. On the contrary, it is defined as a P-type metal oxide semiconductor (PMOS) transistor.

Referring to FIG. 2C , a third sub-insulation layer 218 is formed on the second sub-insulation layer 214 , and the third sub-insulation layer 218 covers the channel 216 , the source doped region 216 b and the drain doped region 216 c. In addition, the first insulating sub-layer 212 , the second insulating sub-layer 214 and the third insulating sub-layer 218 form a first insulating layer 220 of a multi-layer structure.

Next, the second sub-insulation layer 214 and the third sub-insulation layer 218 are etched to form a groove U, and part of the first sub-insulation layer 212 is exposed, wherein the depth _DU of the groove is 50 nm to 2000 nm. In this embodiment, the groove U is formed by, for example, etching a wavy pattern by dry etching or wet etching. Of course, the number and shape of the grooves are not particularly limited. In this embodiment, the first sub-insulation layer 212 is reserved between the region where capacitors are to be laid out and the substrate 210 , so as to prevent materials above and below the first sub-insulation layer 212 from interfering with each other. Specifically, for the convenience of the manufacturing process, the material of the first sub-insulation layer 212 in this embodiment can be selected from a material different from that of the second sub-insulation layer 214, and an appropriate etchant can be used to make the etching process of forming the groove U Among them, the first sub-insulation layer 212 can be used as an etch stop layer. However, the present invention is not limited thereto, and in other embodiments, the first sub-insulation layer 212 may not be configured.

Referring to FIG. 2D , a plurality of first signal lines (not shown), a plurality of lower electrodes 224 , a plurality of common lines (not shown) and a gate 222 are formed on the first insulating layer 220 . A portion of each lower electrode 224 is located in at least one groove U. In this embodiment, the material of the first signal line, the bottom electrode 224 , the common line and the gate 222 can be metal, alloy or metal stack, but the invention is not limited thereto.

Referring to FIG. 2E , a second insulating layer 230 is formed to cover the first insulating layer 220 , the first signal line, the lower electrode 224 , the common line and the gate 222 . Next, a contact window opening W1 is formed, and the contact window opening W1 penetrates the second insulating layer 230 and the third sub-insulating layer 218 and exposes part of the source doped region 216b and the drain doped region 216c. In this embodiment, the method of forming the contact opening W1 is, for example, etching, but the invention is not limited thereto.

2F, a plurality of second signal lines (not shown), a plurality of upper electrodes 244, source electrodes 242b and drain electrodes 242c are formed on the second insulating layer 230, wherein the source electrodes 242b and the drain electrodes 242c are respectively contacted The window opening W1 is electrically connected to the source doped region 216b and the drain doped region 216c. At this point, the fabrication of the plurality of active elements 240 is completed. In this embodiment, the active device 240 is partially embedded in the first insulating layer 220 , and the second insulating layer 230 is located between the gate 222 and the source 242 b and drain 242 c of the active device 240 . Here, the source 242b and the drain 242c are collectively defined as source and drain. In addition, the upper electrode 244 and the lower electrode 224 are correspondingly coupled into a plurality of capacitors C1 through the second insulating layer 230 . The upper electrode 244 of the capacitor C1 has undulations relative to the surface S of the substrate 210 . In this embodiment, the cross section of the upper electrode 244 of the capacitor C1 perpendicular to the surface S is wavy. In addition, the maximum height difference D of the upper electrode 244 of the capacitor C1 relative to the surface S is 50 nm to 2000 nm.

Next, a third insulating layer 250 is formed to cover the second insulating layer 230 , the second signal line and the upper electrode 244 , and optionally fills up the wave-like structure of the capacitor C1 . In this embodiment, the material of the third insulating layer 250 is, for example, organic photoresist. In addition, the third insulating layer 250 has a contact opening W2. In this embodiment, the method of forming the contact opening W2 is, for example, etching, but the invention is not limited thereto.

Referring to FIG. 2G , a plurality of pixel electrodes 260 are formed on the third insulating layer 250 , and the pixel electrodes 260 are electrically connected to the drain electrodes 242c of the corresponding active elements 240 through the contact openings W2 . So far, the pixel array substrate 200 is completed.

Next, the top view of the pixel array substrate 200 will be further described. FIG. 3 is a schematic top view of the pixel array substrate in FIG. 2G , and the cross section along line A-A' in FIG. 3 is FIG. 2G .

3 and 2G, the pixel array substrate 200 of this embodiment includes a substrate 210 with a surface S and a plurality of scanning lines 226, a plurality of data lines 246, a plurality of common lines 228, a plurality of Capacitor C1 , a plurality of active elements 240 and a plurality of pixel electrodes 260 . Each common line 228 is coupled to a plurality of capacitors C1 , and each common line 228 is connected to a plurality of lower electrodes 224 . In addition, the orthographic projection (not shown) of the gate 222 on the substrate 210 overlaps with the orthographic projection (not shown) of the channel 216 a on the substrate 210 . In addition, each pixel electrode 260 is electrically connected to the corresponding scan line 226 and data line 246 through a different active element 240 . In this embodiment, viewed from a direction perpendicular to the surface S, the upper electrode 244 of each capacitor C1 has a plurality of parallel recessed regions A1.

It is worth noting that the pixel array substrate 200 of this embodiment utilizes a plurality of parallel recessed regions A1 to increase the surface area of the capacitor C1 in a direction perpendicular to the substrate 210 , thereby increasing the charge storage capacity. Therefore, the pixel array substrate 200 of this embodiment can increase the charge storage capacity at the same aperture ratio. In addition, the pixel array substrate 200 of this embodiment can also reduce the area occupied by the capacitor C1 on the substrate 210 under the same charge storage capacity, so as to shrink the pixel size and improve the resolution of the display.

In addition, the upper electrode 244 of the capacitor C1 may not only have the above-mentioned plurality of parallel recessed regions A1, but in other embodiments, a plurality of dot-shaped recessed regions may also be used instead of the strip-shaped recessed regions A1. FIG. 4 is a schematic top view of a pixel array substrate according to another embodiment of the present invention. Please refer to FIG. 4 , the pixel array substrate 400 of this embodiment has a similar structure to the pixel array substrate 300 in FIG. 3 , and similar symbols represent similar components and have similar functions, so details are not repeated here. The difference between the two lies in that the upper electrode 244' of the capacitor C2 of the pixel array substrate 400 in this embodiment has a plurality of dot-shaped recessed regions A2. In addition, the plurality of dot-shaped recessed regions A2 also have the function of the plurality of parallel recessed regions A1 described above. For example, a plurality of dot-shaped recessed regions A2 can increase the surface area of the capacitor C2 in a direction perpendicular to the substrate 210 , thereby increasing the charge storage capacity. In addition, the multiple dot-shaped recessed regions A2 can also reduce the area occupied by the capacitor C2 on the substrate 210 under the same charge storage capacity, so as to shrink the pixel size and improve the resolution of the display.

In addition, the pixel array substrate of the present invention may have active elements of low-temperature polysilicon, and in other embodiments, the pixel array substrate of the present invention may also have active elements of amorphous silicon. 5A to 5F , FIG. 6 and FIG. 7 will be described in detail below.

5A to 5F are schematic cross-sectional views of the fabrication process of a pixel array substrate according to another embodiment of the present invention.

Referring to FIG. 5A , a first insulating layer 520 is formed on a surface S′ of a substrate 510 . Next, the first insulating layer 520 is etched to form a groove U′, and part of the substrate 510 is exposed, wherein the depth DU _′ of the groove is 50 nm to 2000 nm. In this embodiment, the groove U is formed by, for example, etching a wavy pattern by dry etching or wet etching. Of course, the number and shape of the grooves are not particularly limited.

Referring to FIG. 5B , a plurality of first signal lines (not shown), a plurality of lower electrodes 524 , a plurality of common lines (not shown) and a gate 522 are formed on the first insulating layer 520 . A portion of each lower electrode 524 is located in at least one groove U'. In this embodiment, the material of the first signal line, the bottom electrode 524 , the common line and the gate 522 can be metal, alloy or metal stack, but the invention is not limited thereto.

Referring to FIG. 5C , a second insulating layer 530 , a channel 516 and an ohmic contact pattern 518 are sequentially formed on the first insulating layer 520 and located above the gate 522 .

Referring to FIG. 5D , a plurality of second signal lines (not shown), a plurality of upper electrodes 544 , a source 542 b and a drain 542 c are sequentially formed on the second insulating layer 530 and the ohmic contact pattern 518 . At this point, the fabrication of the plurality of active elements 540 is completed. In this embodiment, the active device 540 is a bottom gate structure, but the invention is not limited thereto. In other embodiments, the active element can also be a top gate structure, or anyone skilled in the art can slightly change this structure, so the present invention does not limit the structure of the active element. In this embodiment, all the active elements 540 are disposed on the first insulating layer 520 , and the second insulating layer 530 is located between the gate 522 , the source 542 b and the drain 542 c of the active elements 540 . Here, the source 542b and the drain 542c are collectively defined as source and drain. In addition, the upper electrode 544 and the lower electrode 524 are correspondingly coupled to form a plurality of capacitors C3 through the second insulating layer 530, wherein the upper electrode 544 of the capacitor C3 has undulations relative to the surface S' of the substrate 510. In this embodiment, the cross section of the upper electrode 544 of the capacitor C3 perpendicular to the surface S' is wavy. In addition, the maximum height difference D' of the upper electrode 544 of the capacitor C3 relative to the surface S' is 50 nm to 2000 nm.

Referring to FIG. 5E , a third insulating layer 550 is formed to cover the second insulating layer 530 , the second signal line and the upper electrode 544 , and can optionally fill up the wave-like structure of the capacitor C3 . In this embodiment, the material of the third insulating layer 550 is, for example, organic photoresist. In addition, the third insulating layer 550 has a plurality of contact openings W3. In this embodiment, the method of forming the contact opening W3 is, for example, etching or laser lift-off, but the invention is not limited thereto.

Referring to FIG. 5F , a plurality of pixel electrodes 560 are formed on the third insulating layer 550 , and the pixel electrodes 560 are electrically connected to the drain electrodes 542 c of the corresponding active elements 540 through the contact window openings W3 . So far, the pixel array substrate 500 is completed.

Next, the top view of the pixel array substrate 500 will be further described. FIG. 6 is a schematic top view of the pixel array substrate in FIG. 5F , and the section along line A-A' in FIG. 6 is FIG. 5F .

Please refer to FIG. 6 and FIG. 5F, the pixel array substrate 500 of this embodiment includes a substrate 510 having a surface S' and a plurality of scanning lines 526, a plurality of data lines 546, a plurality of common lines 528, a plurality of A capacitor C3, a plurality of active elements 540 and a plurality of pixel electrodes 560. Each common line 528 is coupled to a plurality of capacitors C3 , and each common line 528 is connected to a plurality of lower electrodes 524 . In addition, the orthographic projection (not shown) of the gate 522 on the substrate 510 overlaps with the orthographic projection (not shown) of the channel 516 on the substrate 510 . In addition, each pixel electrode 560 is electrically connected to the corresponding scan line 526 and data line 546 through a different active element 540 . In this embodiment, viewed from the direction perpendicular to the surface S', the upper electrode 544 of each capacitor C3 has a plurality of parallel recessed regions A3.

It should be noted that the pixel array substrate 500 of this embodiment has similar functions to the pixel array substrate 200 in FIG. 3 . For example, the pixel array substrate 500 uses a plurality of parallel recessed regions A3 to increase the surface area of the capacitor C3 in a direction perpendicular to the substrate 510 , thereby increasing the charge storage capacity. Therefore, the pixel array substrate 500 of this embodiment can increase the charge storage capacity under the same aperture ratio, or reduce the area occupied by the capacitor C3 on the substrate 510 under the same charge storage capacity. In other words, the pixel array substrate 500 of this embodiment can reduce the area occupied by the capacitor C3 on the substrate 510 while maintaining the same charge storage capacity, thereby shrinking the size of the pixels and improving the resolution of the display.

In addition, the upper electrode 544 of the capacitor C3 may not only have the above-mentioned plurality of parallel recessed regions A3, but in other embodiments, a plurality of dot-shaped recessed regions may also be used instead of the strip-shaped recessed regions A3. FIG. 7 is a schematic top view of a pixel array substrate according to another embodiment of the present invention. Please refer to FIG. 7 , the pixel array substrate 700 of this embodiment has a similar structure to the pixel array substrate 500 in FIG. 6 , and similar symbols represent similar components and have similar functions, so details are not repeated here. The difference between the two lies in that the upper electrode 544' of the capacitor C4 of the pixel array substrate 700 of this embodiment has a plurality of dot-shaped recessed regions A4. In addition, the plurality of dot-shaped recessed regions A4 also have the function of the plurality of parallel recessed regions A3 described above. For example, a plurality of dot-shaped recessed regions A2 can increase the surface area of the capacitor C2 in a direction perpendicular to the substrate 210 , thereby increasing the charge storage capacity. In addition, the multiple dot-shaped recessed regions A2 can also reduce the area occupied by the capacitor C2 on the substrate 210 under the same charge storage capacity, so as to shrink the pixel size and improve the resolution of the display.

To sum up, in the pixel array substrate of the present invention, the area of the capacitor in the direction perpendicular to the substrate is increased, thereby increasing the charge storage capacity. Therefore, when the pixel size is miniaturized due to the requirement of high resolution, the aperture ratio of the pixel array substrate can be reduced without sacrificing the area occupied by the capacitor on the substrate to achieve excellent charge storage capacity. In other words, under the same pixel size, the pixel array substrate of the embodiment of the present invention can increase the aperture ratio, thereby improving the brightness of the display. Or under the same brightness of the display, the brightness of the backlight can be reduced due to the increase of the aperture ratio. On the other hand, while maintaining the same charge storage capacity, the area occupied by the capacitor on the substrate can be reduced, the pixel size can be miniaturized, and the resolution of the display can be improved. A display with multiple active elements, such as an electronic paper or an OLED display.

Although the present invention has been disclosed in combination with the above embodiments, it is not intended to limit the present invention. Anyone skilled in the art can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention should be defined by the appended claims.

Claims (14)

1. image element array substrates comprises:

Substrate has a surface;

Multi-strip scanning line, many data wires and many shared lines are disposed on this substrate;

A plurality of electric capacity are disposed on this substrate and are coupled to those bridging lines, and wherein respectively the top electrode of this electric capacity has fluctuating in this surface relatively;

A plurality of active elements are disposed on this substrate; And

A plurality of pixel electrodes are disposed on this substrate, and each pixel electrode is electrically connected with corresponding scanning line and data wire through different active elements respectively.

2. image element array substrates as claimed in claim 1, the maximum difference of height that wherein respectively the top electrode of this electric capacity relatively should the surface is 50 nanometer to 2000 nanometers.

3. image element array substrates as claimed in claim 1, wherein respectively the top electrode of this electric capacity is wavy perpendicular to this surperficial section.

4. image element array substrates as claimed in claim 1, wherein from direction sight that vertically should the surface, respectively the top electrode of this electric capacity has many depressed areas parallel to each other.

5. image element array substrates as claimed in claim 1, wherein from direction sight that vertically should the surface, respectively the top electrode of this electric capacity has a plurality of pittings district.

6. image element array substrates as claimed in claim 1, wherein the material of the passage of those active elements is low temperature polycrystalline silicon or amorphous silicon.

7. image element array substrates comprises:

Substrate;

First insulating barrier is disposed on this substrate, and has a plurality of grooves;

A plurality of active elements, respectively the part of this active element is embedded in this first insulating barrier or all is disposed on this first insulating barrier;

Many first holding wires, a plurality of bottom electrode and many shared lines are disposed on this first insulating barrier, and wherein respectively the part of this bottom electrode is arranged at least one those groove, and respectively this bridging line connects those bottom electrodes;

Second insulating barrier covers this first insulating barrier, those first holding wires, those bottom electrodes and those bridging lines, and between the grid and source-drain electrode of this active element respectively;

Many secondary signal lines and a plurality of top electrode are disposed on this second insulating barrier, and wherein those top electrodes and those bottom electrodes are coupled as a plurality of electric capacity accordingly;

The 3rd insulating barrier covers this second insulating barrier, those secondary signal lines and those top electrodes, and has a plurality of contact windows; And

A plurality of pixel electrodes are disposed on the 3rd insulating barrier, and respectively this pixel electrode is electrically connected the source-drain electrode of this corresponding active element through those contact window.

8. image element array substrates as claimed in claim 7, wherein respectively the degree of depth of this groove is 50 nanometer to 2000 nanometers.

9. image element array substrates as claimed in claim 7, wherein this first insulating barrier is wavy at the section of the part with those grooves.

10. image element array substrates as claimed in claim 7, wherein respectively those grooves of this bottom electrode covering are strip groove parallel to each other.

11. image element array substrates as claimed in claim 7, wherein respectively those grooves of this bottom electrode covering are a plurality of point-like grooves.

12. image element array substrates as claimed in claim 7, wherein the material of the passage of those active elements is low temperature polycrystalline silicon or amorphous silicon.

13. image element array substrates as claimed in claim 7, wherein respectively this top electrode is electrically connected the source-drain electrode of this corresponding active element.

14. image element array substrates as claimed in claim 7, wherein this first insulating barrier is a sandwich construction.

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