CN102646792B - Organic film transistor array substrate and preparation method thereof - Google Patents

Abstract

The embodiment of the invention discloses an organic thin film transistor array substrate and a preparation method thereof, relates to the technical field of liquid crystal display, and is used for improving the preparation efficiency of the organic thin film transistor array substrate. In the present invention, the pattern layer of the pixel electrode, the pattern layer of the source electrode and the pattern layer of the data line and the pattern layer of the drain electrode located on the pattern layer of the pixel electrode are formed on the insulating substrate through a patterning process; The organic semiconductor layer on the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode, and the gate insulating layer covering the organic semiconductor layer; passivation is formed on the insulating substrate formed with the gate insulating layer through a patterning process layer; the pattern layer of the gate electrode and the gate line on the passivation layer is formed through a patterning process. By adopting the invention, the preparation efficiency of the organic thin film transistor array substrate is improved.

Description

Organic thin film transistor array substrate and preparation method thereof

technical field

The invention relates to the technical field of liquid crystal display, in particular to an organic thin film transistor array substrate and a preparation method thereof.

Background technique

Organic thin film transistor (OTFT) is a logic unit device using organic semiconductor as the active layer. It has the advantages of being suitable for large-area processing, flexible substrates, and low process cost. It is used in flat panel displays, sensors, memory cards, and radio frequency identification tags. Show application prospects. Therefore, the research and development of organic thin film transistors has received extensive attention in the world.

The organic thin film transistor array substrate includes source electrodes, drain electrodes, data lines, pixel electrodes, gate electrodes and gate lines, organic semiconductor layers, gate insulating layers, passivation layers and the like.

In the process of preparing the organic thin film transistor array substrate, it is necessary to form the pattern layer of the source electrode and the data line, the pattern layer of the drain electrode, the pattern layer of the pixel electrode, the pattern layer of the gate electrode and the gate line, the organic semiconductor layer, and the gate insulating layer. and passivation layer. The formation of each layer needs to go through a patterning process, and a mask plate is required in the patterning process. For example, when forming the pattern layer of source electrodes and data lines, first deposit a layer of metal film on the array substrate, spin coat a layer of photoresist on the metal film, and then use a mask to expose and develop the photoresist, Then the array substrate is etched to etch away the metal thin film in the photoresist removal area, and finally the remaining photoresist is stripped off. So far, through operations such as exposure and development, etching, and stripping, a pattern layer of source electrodes and data lines has been formed on the array substrate. The formation processes of other graphics layers are similar.

In the prior art, the formation of each layer on the organic thin film transistor array substrate needs to go through a patterning process, because each patterning process needs to transfer the mask pattern to the thin film pattern, and each layer pattern requires precise Covered on another layer of thin film pattern, therefore, in the manufacturing process of the organic thin film transistor array substrate, the number of masks used is large, resulting in low production efficiency and high production cost.

Contents of the invention

Embodiments of the present invention provide an organic thin film transistor array substrate and a preparation method thereof, which are used to improve the preparation efficiency of the organic thin film transistor array substrate.

A method for manufacturing an organic thin film transistor OTFT array substrate, the method comprising:

Forming the patterned layer of the pixel electrode, the patterned layer of the source electrode and the patterned layer of the data line and the patterned layer of the drain electrode located on the patterned layer of the pixel electrode on the insulating substrate through a patterning process;

forming an organic semiconductor layer covering the pattern layer of the source electrode and the data line and a pattern layer of the drain electrode, and a gate insulating layer covering the organic semiconductor layer through a patterning process;

forming a passivation layer on the insulating substrate formed with the gate insulating layer through a patterning process;

The pattern layer of the gate electrode and the gate line on the passivation layer is formed by one patterning process.

An organic thin film transistor OTFT array substrate prepared according to the above method, the pattern layer of the pixel electrode and the OTFT are formed in the pixel area defined by the gate line and the data line on the OTFT array substrate, and the OTFT includes a pattern on the pixel electrode The pattern layer of the source electrode and the data line and the pattern layer of the drain electrode above the layer, the organic semiconductor layer covering the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode, and the gate insulating layer covering the organic semiconductor layer layer, a passivation layer covering the gate insulating layer and the pattern layer of the pixel electrode, and a pattern layer of the gate electrode and the gate line on the passivation layer.

A method for manufacturing an organic thin film transistor OTFT array substrate, the method comprising:

Forming the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode on the insulating substrate through a patterning process;

The organic semiconductor layer covering the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode, the gate insulating layer covering the organic semiconductor layer, and the gate electrode and the gate electrode covering the gate insulating layer are formed by one patterning process. Graphics layer for lines;

A passivation layer is formed on the insulating substrate on which the pattern layer of the gate electrode and the gate line is formed through a patterning process;

A pattern layer covering the pixel electrode on the passivation layer is formed by one patterning process.

An organic thin film transistor OTFT array substrate prepared according to the above method, a pattern layer of a pixel electrode and an OTFT are formed in the pixel area defined by the gate line and the data line on the OTFT array substrate, and the OTFT includes a source on an insulating substrate The pattern layer of the electrode and the data line and the pattern layer of the drain electrode, the organic semiconductor layer covering the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode, the gate insulating layer covering the organic semiconductor layer, covering the gate The pattern layer of the gate electrode and the gate line on the insulating layer, and the passivation layer covering the pattern layer of the drain electrode, and the pattern layer of the pixel electrode covering the passivation layer.

In the present invention, the organic thin film transistor array substrate is prepared by adopting four patterning processes, which simplifies the manufacturing process, reduces the manufacturing cost, shortens the manufacturing time, and improves the manufacturing efficiency.

Description of drawings

Figure 1a is a schematic flow chart of the method provided by Embodiment 1 of the present invention;

FIG. 1b is a schematic diagram of a specific implementation process of Embodiment 1 of the present invention;

2a is a cross-sectional view after forming a transparent conductive film and a metal film in Embodiment 1 of the present invention;

2b is a cross-sectional view of the OTFT after exposure and development through a halftone or gray tone mask in the first patterning process in Embodiment 1 of the present invention;

2c is a cross-sectional view of the OTFT after the first etching in the first patterning process in Embodiment 1 of the present invention;

2d is a cross-sectional view of the OTFT after ashing the photoresist in the second patterning process in Embodiment 1 of the present invention;

2e is a cross-sectional view of the OTFT after the second etching in the first patterning process in Embodiment 1 of the present invention;

FIG. 2f is an interface diagram of the OTFT after stripping off the photoresist in the first patterning process in Embodiment 1 of the present invention;

2g is a plan view of the OTFT after stripping off the photoresist in the first patterning process in Embodiment 1 of the present invention;

3a is a cross-sectional view after preparing an organic semiconductor layer and a gate insulating layer film in Example 1 of the present invention;

3b is a cross-sectional view of the OTFT after the second patterning process mask exposure and development in Embodiment 1 of the present invention;

3c is a cross-sectional view of the OTFT after the second patterning process etching in Embodiment 1 of the present invention;

Figure 3d is a cross-sectional view of Figure 3c in the direction of A-A in Embodiment 1 of the present invention;

4 is a cross-sectional view of the OTFT after the third patterning process in Embodiment 1 of the present invention;

Figure 5a is a cross-sectional view of the OTFT after the fourth patterning process in Embodiment 1 of the present invention;

5b is a plan view of the OTFT after the fourth patterning process in Embodiment 1 of the present invention;

Fig. 6a is a schematic flow chart of the method provided by Embodiment 2 of the present invention;

FIG. 6b is a schematic diagram of a specific implementation process of Embodiment 2 of the present invention;

Fig. 7a is a plan view after the first patterning process in Embodiment 2 of the present invention;

Fig. 7b is a cross-sectional view of Fig. 7a in the direction of A-A in the second embodiment of the present invention;

Fig. 8a is a cross-sectional view after preparing an organic semiconductor layer, a gate insulating layer and a gate electrode film in Example 2 of the present invention;

Figure 8b is a cross-sectional view of the OTFT after exposure and development in the second patterning process in Embodiment 2 of the present invention;

8c is a cross-sectional view of the OTFT after etching in the second patterning process in Embodiment 2 of the present invention;

Fig. 8d is a cross-sectional view of the OTFT after stripping the photoresist in the second patterning process in Embodiment 2 of the present invention;

Figure 8e is a plan view of the OTFT after the second patterning process in Embodiment 2 of the present invention;

9 is a cross-sectional view of the OTFT after the third patterning process in Embodiment 2 of the present invention;

Figure 10a is a cross-sectional view of the OTFT after the fourth patterning process in Embodiment 2 of the present invention;

FIG. 10b is a plan view of the OTFT after the fourth patterning process in Embodiment 2 of the present invention.

Detailed ways

In order to improve the preparation efficiency of the organic thin film transistor array substrate, the embodiment of the present invention provides two methods for manufacturing the organic thin film transistor array substrate and the corresponding organic thin film transistor array substrate. The present invention completes the preparation of the array substrate through four patterning processes.

Embodiment one:

Referring to Figure 1a, the method for manufacturing an organic thin film transistor array substrate provided by an embodiment of the present invention includes:

Step 101: forming a pattern layer of the pixel electrode, a pattern layer of the source electrode, a pattern layer of the data line, and a pattern layer of the drain electrode on the insulating substrate through a patterning process;

Step 102: forming an organic semiconductor layer covering the pattern layer of the source electrode and data line and the pattern layer of the drain electrode, and a gate insulating layer covering the organic semiconductor layer through a patterning process;

Step 103: forming a passivation layer on the insulating substrate formed with the gate insulating layer through a patterning process;

Step 104: forming a pattern layer of gate electrodes and gate lines on the passivation layer through a patterning process.

In step 101, the pattern layer of the pixel electrode, the pattern layer of the source electrode and the pattern layer of the data line and the pattern layer of the drain electrode located on the pattern layer of the pixel electrode are formed on the insulating substrate through a patterning process, and its specific implementation is as follows:

Deposit a transparent conductive film on an insulating substrate, and form a metal film on the transparent conductive film;

The photoresist is spin-coated on the metal film, and the photoresist is exposed and developed using a mask to obtain a photoresist removal area, a photoresist partial retention area and a photoresist complete retention area; the mask can be a halftone Mask plate or gray tone mask plate, etc.; here, there can be two completely reserved areas of photoresist, one completely reserved area of photoresist corresponds to the pattern layer of the source electrode and data line, and the other completely reserved area of photoresist corresponds to the drain electrode graphics layer. A channel region is left between the two photoresist fully-retained regions. The partially reserved region of photoresist is located on one side of the completely reserved region of photoresist of the pattern layer corresponding to the drain electrode, and is connected with the completely reserved region of photoresist.

Etching the insulating substrate to etch away the transparent conductive film and metal film in the area where the photoresist is completely removed;

Ashing the photoresist on the insulating substrate to remove the photoresist in the partially reserved photoresist area;

Etching the insulating substrate to etch away the metal film in the part of the photoresist reserved area to obtain the pattern layer of the pixel electrode;

The photoresist in the photoresist completely reserved area is stripped to obtain the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode.

In step 102, the organic semiconductor layer covering the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode and the gate insulating layer covering the organic semiconductor layer are formed through a patterning process, and its specific implementation is as follows:

Form the organic semiconductor layer thin film on the insulating substrate forming the pattern layer of the source electrode and the data line, the pattern layer of the drain electrode and the pattern layer of the pixel electrode; , forming a gate insulating layer thin film on the insulating substrate of the pattern layer of the pixel electrode and the organic semiconductor layer thin film;

The photoresist is spin-coated on the gate insulating layer film, and the photoresist is exposed and developed using a mask to obtain the photoresist removal area and the photoresist completely reserved area, and the photoresist completely reserved area is connected to the source electrode and the data line. The graphic layer and the graphic layer of the drain electrode are opposite;

Etching the insulating substrate to etch away the gate insulating layer film and the organic semiconductor layer film in the region where the photoresist is completely removed;

The photoresist in the region where the photoresist is completely reserved is stripped to obtain a patterned layer of the organic semiconductor layer and the gate insulating layer.

Preferably, after the gate insulating layer film is formed and before the photoresist is spin-coated on the gate insulating layer film, the insulating substrate can be dried at the first set temperature for a set time, and at the second set temperature The insulating substrate is dried for a set time, and the second set temperature is higher than the first set temperature. For example, the first set temperature is less than 100 degrees Celsius, and the second set temperature is greater than 130 degrees Celsius.

In step 103, a passivation layer is formed on the insulating substrate on which the gate insulating layer is formed through a patterning process, and its specific implementation is as follows:

forming a passivation layer film on the insulating substrate formed with the gate insulating layer;

Spin-coat photoresist on the passivation layer film, and use a mask to expose and develop the photoresist to obtain a completely removed area of photoresist and a completely retained area of photoresist, and the completely removed area of photoresist is located at the data line pad PAD area and pixel area, or the area where the photoresist is completely removed is located in the data line pad PAD area;

Etching the insulating substrate to etch away the passivation layer film in the area where the photoresist is completely removed;

The photoresist in the region where the photoresist is completely reserved is stripped to obtain a passivation layer.

In step 104, the pattern layer of the gate electrode and the gate line on the passivation layer is formed through a patterning process, and its specific implementation is as follows:

forming a gate metal thin film on an insulating substrate formed with a passivation layer;

Spin-coat photoresist on the gate metal film, use a mask to expose and develop the photoresist, and obtain the photoresist completely removed area and the photoresist completely reserved area, and the photoresist completely reserved area is connected with the source electrode and the data line The graphic layer of the drain electrode is opposite to the graphic layer of the drain electrode;

Etching the insulating substrate to etch away the passivation layer film in the area where the photoresist is completely removed;

The photoresist in the photoresist completely reserved area is stripped to obtain the pattern layer of the gate electrode and the gate line.

As shown in Figure 5a, an embodiment of the present invention provides an organic thin film transistor OTFT array substrate prepared according to the above method, and a pattern layer 3 of a pixel electrode is formed in a pixel area defined by gate lines and data lines on the OTFT array substrate and OTFT, the OTFT includes the pattern layer 2a of the source electrode and the pattern layer 2a of the data line and the pattern layer 2b of the drain electrode on the pattern layer 3 of the pixel electrode, and the pattern layer 2a of the pattern layer covering the source electrode and the data line and the pattern layer of the drain electrode The organic semiconductor layer 4 on 2b, the gate insulating layer 5 covering the organic semiconductor layer 4, the passivation layer 6 covering the gate insulating layer 5 and the pattern layer 3 of the pixel electrode, and the passivation layer 6 located on the passivation layer 6 Pattern layer 7 for gate electrodes and gate lines.

In this embodiment, the material of the organic semiconductor layer is one of: pentacene, tetracene, copper phthalocyanine, vanadyl phthalocyanine, fluorocopper phthalocyanine, and poly(3-hexylthiophene).

The material of the pattern layer of the gate electrode and grid line is: gold (Au), silver (Ag), copper (Cu), molybdenum (Mo), aluminum (Al), cadmium (Gr), Au paste, Ag paste, One of Cu slurry, poly(3,4-ethylenedioxythiophene)/polystyrene sulfonate (PEDOT/PSS).

The material of the gate insulating layer is: tantalum pentoxide (Ta ₂ O ₅ ), titanium dioxide (T _i O ₂ ), zirconium dioxide ( _Zr O ₂ ), aluminum oxide (Al ₂ O ₃ ), silicon nitride (S _i N _X ), silicon oxide (S _i O ₂ ), polymethyl methacrylate, polyimide, polyvinyl alcohol, polyvinyl phenol, polyurethane, phenolic resin, polyvinylidene fluoride or two.

The material of the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode is: one of Au, Ag, Cu, Mo, Gr, Al, Au paste, Ag paste, Cu paste, PEDOT/PSS.

The material of the insulating substrate is: glass or plastic.

The method for forming the thin film of the organic semiconductor layer includes thermal deposition, spin coating, printing and the like.

The way of forming the gate electrode film includes any one of sputtering, electron beam evaporation, thermal deposition, inkjet printing, screen printing, gravure printing, nanoimprinting and microcontact printing.

The method for forming the source-drain electrode thin film includes any one of sputtering, electron beam evaporation, thermal deposition, inkjet printing, screen printing, gravure printing, nanoimprinting and microcontact printing.

The purpose of this embodiment is to provide an organic thin film transistor array substrate and a manufacturing method thereof. Four patterning processes are adopted, so that the pattern layer of the source electrode and the data line and the pattern layer of the pixel electrode, the organic semiconductor layer and the gate insulating layer are formed once. Realized in the composition, the production cost is reduced, and the production efficiency is improved.

In order to achieve the above purpose, this embodiment provides an organic thin film transistor array substrate, including gate lines and data lines, pixel electrodes and organic thin film transistors are formed in the pixel area defined by the gate lines and data lines, and the organic thin film transistors are top The gate bottom contact configuration, the pattern layer of the source electrode and the data line, the pattern layer of the drain electrode and the pattern layer of the pixel electrode are on the insulating substrate, and the organic semiconductor layer is on the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode The gate insulating layer is on the organic semiconductor layer, the passivation layer is on the gate insulating layer, and finally the gate electrode is on the passivation layer.

Referring to Figure 1b, the specific implementation method of Embodiment 1 is as follows:

Step 111, deposit a layer of transparent conductive film on the insulating substrate first, and then deposit a layer of metal film, and form the pattern layer of the source electrode and the data line, the pattern layer of the drain electrode, and the pattern of the pixel electrode through the first patterning process layer;

Step 112, preparing an organic semiconductor layer and a gate insulating layer on the insulating substrate that completed step 111, and forming an organic semiconductor layer and a gate insulating layer through a second patterning process;

Step 113, preparing a passivation layer on the insulating substrate after step 112, and forming gate line interface areas, data line interface areas, and pixel via holes through a third patterning process;

Step 114 , depositing a gate metal thin film on the insulating substrate completed in step 113 , and forming a pattern layer of gate electrodes and gate lines through a fourth patterning process.

Specifically, in step 111, first, a layer of transparent conductive film 2 is deposited on the glass substrate 1 by sputtering, and then a metal film 3 is formed on the transparent conductive film. Figure 2a shows the formation of the transparent conductive film and the metal film in this embodiment Later sectional view. Then spin-coat a layer of photoresist 8, and use a halftone or gray tone mask to expose and develop the photoresist 8, as shown in Figure 2b. Cross-sectional view of the OTFT after exposure and development. In FIG. 2b, region A is the region where the photoresist is removed, region B is the region where the photoresist is partially retained, and region C is the region where the photoresist is completely retained. The photoresist completely reserved area corresponds to the pattern area for forming the source electrode and the data line and the drain electrode, the photoresist partly reserved area corresponds to the pattern area for forming the pixel electrode, and the photoresist completely removed area corresponds to the photoresist completely reserved area The area other than the partially reserved area with photoresist is used to form the channel area. The first etching is performed on the array substrate shown in FIG. 2 b , to etch away the transparent conductive film and the metal film in the area where the photoresist is completely removed. FIG. 2c is a cross-sectional view of the OTFT after the first etching in the first patterning process of this embodiment. Next, the photoresist on the array substrate shown in FIG. 2c is ashed, and the photoresist in the partially reserved photoresist area is removed. FIG. 2d is a cross-sectional view of the OTFT after ashing the photoresist in the second patterning process of this embodiment. Then, the array substrate shown in Figure 2d is etched for the second time, and the metal film in the photoresist part of the reserved area is etched away to obtain the pattern layer of the pixel electrode, as shown in Figure 2e, which is the first patterning process of this embodiment Cross-sectional view of the OTFT after the second etch in . After the photoresist is stripped off, the patterned layer 2a of the source electrode and the data line, the patterned layer 2b of the drain electrode, and the patterned layer 3 of the pixel electrode are obtained, as shown in FIG. The interface diagram of OTFT after etching. FIG. 2g is a plan view of the OTFT after stripping off the photoresist in the first patterning process of this embodiment.

In step 112, on the glass substrate completed in step 111, vacuum evaporation is used to prepare vanadyl phthalocyanine organic semiconductor layer film 4 with a film thickness of 50nm; then spin coating is used to prepare a polyvinyl phenol (PVP) gate insulating layer Film 5 is dried at a temperature lower than 100°C for 20 minutes, and at a temperature higher than 130°C for 20 minutes, and the thickness of the film is 550nm. FIG. 3 a is a cross-sectional view of an organic semiconductor layer and a thin film of a gate insulating layer prepared in this embodiment. Then, a layer of photoresist 8 is spin-coated, and the photoresist 8 is exposed and developed using a mask, as shown in FIG. 3 b , which is a cross-sectional view of the OTFT after the mask is exposed and developed in the second patterning process of this embodiment. In FIG. 3b, region A is the region where the photoresist is completely preserved, and region B is the region where the photoresist is removed. The photoresist completely reserved area corresponds to the pattern area where the organic semiconductor and the gate insulating layer are formed. The glass substrate shown in FIG. 3b is etched to etch away the insulating layer thin film and the organic semiconductor layer thin film in the photoresist completely removed region. FIG. 3c is a cross-sectional view of the OTFT after the second patterning process of this embodiment, and FIG. 3d is a plan view of the OTFT after the second patterning process of this embodiment.

In step 113, a layer of passivation layer film is deposited on the glass substrate completed in step 112. After the passivation layer film is deposited, the data line pad PAD area and the passivation layer of the pixel area are fully formed by the third patterning process. Remove and expose the metal layer of the data line pad PAD area and the pixel area (or the passivation layer of the pixel area is not etched), and form the pattern 6 of the passivation layer. FIG. 4 is a cross-sectional view of the OTFT after the third patterning process of this embodiment.

In step 114, a gate metal thin film is deposited on the substrate completed in step 113. After depositing the gate metal thin film, a pattern layer 7 of gate electrodes and gate lines is formed through a fourth patterning process. FIG. 5a is a cross-sectional view of the OTFT after the fourth patterning process of this embodiment, and FIG. 5b is a corresponding plan view.

This embodiment adopts four patterning processes, by forming the pattern layer of the source electrode and the data line and the pattern layer of the pixel electrode in one patterning, and forming the organic semiconductor layer and the gate insulating layer in one patterning, which simplifies the manufacturing process and reduces the The production cost is reduced, the production time is shortened, and the production efficiency is improved.

Embodiment two:

Referring to FIG. 6a, an embodiment of the present invention provides another method for manufacturing an organic thin film transistor array substrate, which includes:

Step 601: forming a pattern layer of source electrodes and data lines and a pattern layer of drain electrodes on an insulating substrate through a patterning process;

Step 602: Form an organic semiconductor layer covering the pattern layer of the source electrode and data line and a pattern layer of the drain electrode, a gate insulating layer covering the organic semiconductor layer, and a gate insulating layer covering the gate insulating layer through a patterning process. The pattern layer of electrodes and grid lines;

Step 603: forming a passivation layer on the insulating substrate on which the pattern layer of the gate electrode and the gate line is formed through a patterning process;

Step 604: Form a pattern layer covering the pixel electrode on the passivation layer through a patterning process.

In step 601, the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode are formed on the insulating substrate through a patterning process, and its specific implementation is as follows:

Depositing metal thin films on insulating substrates;

The photoresist is spin-coated on the metal film, and the photoresist is exposed and developed using a mask to obtain a completely removed photoresist area and a completely photoresist reserved area; here, there can be two photoresist completely reserved areas, one The completely reserved area of photoresist corresponds to the pattern layer of the source electrode and the data line, and the other completely reserved area of photoresist corresponds to the pattern layer of the drain electrode. A channel region is left between the two photoresist fully-retained regions.

Etching the insulating substrate to etch away the metal film in the area where the photoresist is completely removed;

The photoresist in the photoresist completely reserved area is stripped to obtain the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode.

In step 602, the organic semiconductor layer covering the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode, the gate insulating layer covering the organic semiconductor layer, and the pattern layer covering the gate insulating layer are formed by one patterning process. The pattern layer of the gate electrode and the gate line is specifically realized as follows:

Form the organic semiconductor layer film on the insulating substrate that forms the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode, and form the pattern layer of the source electrode and the data line, the pattern layer of the drain electrode and the organic semiconductor layer film. Forming a gate insulating layer thin film on the insulating substrate, forming a gate metal thin film on the insulating substrate forming the pattern layer of the active electrode and the data line, the pattern layer of the drain electrode, the organic semiconductor layer film, and the gate insulating layer film;

Spin-coat photoresist on the gate metal film, expose and develop the photoresist, and obtain the photoresist completely removed area and the photoresist completely reserved area; the photoresist completely reserved area and the pattern layer of the source electrode and the data line , the pattern layer of the drain electrode is opposite;

Etching the insulating substrate to etch away the gate metal thin film, gate insulating layer thin film and organic semiconductor layer thin film in the region where the photoresist is completely removed;

The photoresist in the photoresist completely reserved area is peeled off to obtain the patterned layer of the organic semiconductor layer, the patterned layer of the gate insulating layer, the patterned layer of the gate electrode and the gate line, and part of the patterned layer of the drain electrode is exposed.

Preferably, after forming the gate insulating layer film and before forming the gate metal film, the insulating substrate can be dried for a set time at the first set temperature, and dried at the second set temperature. For a certain period of time, the second set temperature is greater than the first set temperature. For example, the first set temperature is less than 100 degrees Celsius, and the second set temperature is greater than 130 degrees Celsius.

In step 603, a passivation layer is formed on the insulating substrate on which the pattern layer of the gate electrode and the gate line is formed through a patterning process, and its specific implementation is as follows:

forming a passivation layer film on the insulating substrate with the pattern layer of the gate electrode and the gate line;

Spin-coat photoresist on the passivation layer film, and use a mask to expose and develop the photoresist to obtain a completely removed area of photoresist and a completely retained area of photoresist, and the completely removed area of photoresist is located at the data line pad PAD region, the gate line pad PAD region and the exposed pattern layer region of the drain electrode;

Etching the insulating substrate to etch away the passivation layer film in the area where the photoresist is completely removed;

The photoresist in the region where the photoresist is completely reserved is stripped to obtain a passivation layer.

In step 604, a pattern layer covering the pixel electrode on the passivation layer is formed through a patterning process, and its specific implementation is as follows:

Depositing a transparent conductive film on an insulating substrate formed with a passivation layer;

The photoresist is spin-coated on the transparent conductive film, and the photoresist is exposed and developed using a mask to obtain a completely removed region of the photoresist and a completely retained region of the photoresist, and the completely retained region of the photoresist is located at the exposed area of the drain electrode. a patterned layer region and a passivation layer region covering the patterned layer of the drain electrode;

Etching the insulating substrate to etch away the passivation layer film in the area where the photoresist is completely removed;

The photoresist in the region where the photoresist is completely reserved is stripped to obtain the pattern layer of the pixel electrode.

As shown in Figure 10a, the embodiment of the present invention provides another organic thin film transistor OTFT array substrate prepared according to the above method, and a pattern layer 7 of a pixel electrode is formed in the pixel area defined by the gate line and the data line on the OTFT array substrate And OTFT, described OTFT comprises the pattern layer 2a of pattern layer 2a of source electrode and data line and the pattern layer 2b of drain electrode on the insulating substrate, covers on the pattern layer 2a of source electrode and data line and pattern layer 2b of drain electrode. The semiconductor layer 3, the gate insulating layer 4 covering the organic semiconductor layer 3, the pattern layer 5 covering the gate electrode and the gate line on the gate insulating layer 4, and the passivation layer 6 covering the pattern layer 2b of the drain electrode , the pattern layer 7 of the pixel electrode covers the passivation layer 6 .

Preferably, part of the patterned layer of the pixel electrode is connected to the patterned layer of the drain electrode through a via hole. A passivation layer 6 is also covered on the pattern layer 5 of the gate electrodes and gate lines.

The purpose of this embodiment is to provide an organic thin film transistor array substrate and a manufacturing method thereof. Four patterning processes are adopted, so that the organic semiconductor layer, the gate insulating layer, the pattern layer of the gate electrode and the gate line are realized in one patterning, reducing the The production cost is reduced, and the production efficiency is improved.

In order to achieve the above object, the present invention provides an organic thin film transistor array substrate, including a gate line and a data line, a pixel electrode and an organic thin film transistor are formed in the pixel area defined by the gate line and the data line, and the organic thin film transistor is a top gate The bottom contact configuration, the pattern layer of the source electrode and the data line, the pattern layer of the drain electrode are on the insulating substrate, the organic semiconductor layer is on the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode, the gate insulating layer is on the organic On the semiconductor layer, the pattern layer of the gate electrode and the gate line is on the gate insulating layer, the passivation layer is on the pattern layer of the gate electrode and the gate line, and the pattern layer of the pixel electrode is on the passivation layer, through the via hole and the drain electrode The graphics layer is connected.

Referring to Figure 6b, the specific implementation method of Embodiment 2 is as follows:

Step 611, deposit a layer of metal thin film on the insulating substrate, and form the pattern layer of the source electrode and the data line, and the pattern layer of the drain electrode through the first patterning process;

Step 612, prepare an organic semiconductor layer film, a gate insulating layer film, and a gate metal film on the insulating substrate that completed step 611, and form a pattern layer of the organic semiconductor layer, a pattern layer of the gate insulating layer, and a gate electrode through a second patterning process. The pattern layer of electrodes and grid lines;

Step 613, preparing a passivation layer film on the insulating substrate that completed step 612, and forming gate line interface areas, data line interface areas, and pixel via holes through the third patterning;

Step 614: Deposit a transparent conductive layer on the substrate after step 613, and form a pattern layer of the pixel electrode through a fourth patterning process.

Specifically, in step 611, a Mo metal film with a thickness of 200 nm is deposited on the glass substrate 1 by sputtering, and the Mo metal film is etched through the first patterning process to form a source in the display area on the substrate 1. The pattern layer 2a of electrodes and data lines, and the pattern layer 2b of drain electrodes, as shown in FIG. 7a, is a plan view after the first patterning process in this embodiment, and FIG. 7b is a cross-sectional view of FIG. 1a along the direction A-A.

In step 612, on the substrate completed in step 611, vacuum evaporation is used to prepare vanadyl phthalocyanine organic semiconductor layer film 3 with a film thickness of 50 nm; then spin coating is used to prepare a polyvinyl phenol (PVP) gate insulating layer film 4. Dry at a temperature lower than 100°C for 20 minutes, and at a temperature higher than 130°C for 20 minutes, with a film thickness of 550nm; then deposit a Mo metal film 5 as a gate metal film by sputtering. Fig. 8a is a cross-sectional view of an organic semiconductor layer, a gate insulating layer and a gate electrode film prepared in this embodiment. A layer of photoresist 8 is spin-coated, and then the photoresist 8 is exposed and developed, as shown in FIG. 8 b , which is a cross-sectional view of the OTFT after exposure and development in the second patterning process in this embodiment. The array substrate shown in FIG. 8b is etched to etch away the gate metal thin film, the insulating layer thin film and the organic semiconductor layer thin film in the region where the photoresist is completely removed. FIG. 8c is a cross-sectional view of the OTFT after etching in the second patterning process in this embodiment. Next, the photoresist on the array substrate shown in FIG. 8c is stripped, and FIG. 8d is a cross-sectional view of the OTFT after stripping the photoresist in the second patterning process in this embodiment. Fig. 8e is a plan view of the OTFT after the second patterning process in this embodiment.

In step 613, a layer of passivation layer film is deposited on the substrate completed in step 612. After the passivation layer is deposited, the data line pad PAD area and the gate line pad PAD area and part of the leakage The passivation layer in the electrode region is completely removed, exposing the data line pad PAD area, the gate line pad PAD area and the metal layer in part of the drain electrode area to form a pattern 6 of the passivation layer. FIG. 9 is a cross-sectional view of the OTFT after the third patterning process in this embodiment.

In step 614, a layer of transparent conductive film is deposited on the substrate completed in step 613. After the transparent conductive film is deposited, the pattern layer 7 of the pixel electrode is formed through a fourth patterning process. FIG. 10a is a cross-sectional view of the OTFT after the fourth patterning process in this embodiment, and FIG. 10b is a corresponding plan view.

In this embodiment, four patterning processes are adopted, and the organic semiconductor layer, the gate insulating layer, the gate electrode and the pattern layer of the gate line are formed in one patterning process, which simplifies the manufacturing process, reduces the manufacturing cost, shortens the manufacturing time, and improves production efficiency.

The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It should be understood that each procedure and/or block in the flowchart and/or block diagram, and a combination of procedures and/or blocks in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions may be provided to a general purpose computer, special purpose computer, embedded processor, or processor of other programmable data processing equipment to produce a machine such that the instructions executed by the processor of the computer or other programmable data processing equipment produce a An apparatus for realizing the functions specified in one or more procedures of the flowchart and/or one or more blocks of the block diagram.

While preferred embodiments of the invention have been described, additional changes and modifications to these embodiments can be made by those skilled in the art once the basic inventive concept is appreciated. Therefore, it is intended that the appended claims be construed to cover the preferred embodiment as well as all changes and modifications which fall within the scope of the invention.

Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention also intends to include these modifications and variations.

Claims (10)

1. A method for manufacturing an organic thin film transistor array substrate, characterized in that the method comprises: Forming the patterned layer of the pixel electrode, the patterned layer of the source electrode and the patterned layer of the data line and the patterned layer of the drain electrode located on the patterned layer of the pixel electrode on the insulating substrate through a patterning process; forming an organic semiconductor layer covering the pattern layer of the source electrode and the data line and a pattern layer of the drain electrode, and a gate insulating layer covering the organic semiconductor layer through a patterning process; forming a passivation layer on the insulating substrate formed with the gate insulating layer through a patterning process; Forming the pattern layer of the gate electrode and the gate line on the passivation layer through a patterning process; The patterning layer of the pixel electrode formed on the insulating substrate through a patterning process, and the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode located on the pattern layer of the pixel electrode include: Deposit a transparent conductive film on an insulating substrate, and form a metal film on the transparent conductive film; The photoresist is spin-coated on the metal film, and the photoresist is exposed and developed using a mask to obtain a photoresist removal area, a photoresist partial retention area and a photoresist complete retention area; Etching the insulating substrate to etch away the transparent conductive film and metal film in the area where the photoresist is completely removed; Ashing the photoresist on the insulating substrate to remove the photoresist in the partially reserved photoresist area; Etching the insulating substrate to etch away the metal film in the part of the photoresist reserved area to obtain the pattern layer of the pixel electrode; Stripping the photoresist in the photoresist completely reserved area to obtain the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode; The formation of the organic semiconductor layer covering the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode and the gate insulating layer covering the organic semiconductor layer through a patterning process includes: Forming an organic semiconductor layer film covering the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode; forming a gate insulating layer film covering the organic semiconductor layer film; Spin-coat photoresist on the gate insulating film, and use a mask to expose and develop the photoresist to obtain photoresist-removed regions and photoresist-completely retained regions; Etching the insulating substrate to etch away the gate insulating layer film and the organic semiconductor layer film in the region where the photoresist is completely removed; The photoresist in the region where the photoresist is completely reserved is stripped to obtain the patterned layer of the organic semiconductor layer and the patterned layer of the gate insulating layer. 2. The method according to claim 1, wherein the mask is a halftone mask or a gray tone mask. 3. The method according to claim 2, characterized in that, after forming the gate insulating layer film and before spin-coating photoresist on the gate insulating layer film, the method further comprises: The insulating substrate is dried for a set time at a first set temperature, and the insulating substrate is dried for a set time at a second set temperature, and the second set temperature is greater than the first set temperature. 4. The method according to claim 1, wherein said forming a passivation layer on the insulating substrate formed with a gate insulating layer through a patterning process comprises: forming a passivation layer film on the insulating substrate formed with the gate insulating layer; Spin-coat the photoresist on the passivation layer film, use the mask to expose and develop the photoresist, and obtain the photoresist completely removed area and the photoresist completely reserved area, and the photoresist completely removed area is located in the data line PAD area and The pixel area, or the photoresist completely removed area is located in the data line PAD area; Etching the insulating substrate to etch away the passivation layer film in the area where the photoresist is completely removed; The photoresist in the region where the photoresist is completely reserved is stripped to obtain a passivation layer. 5. The method according to claim 1, wherein forming the pattern layer of the gate electrode and the gate line on the passivation layer through a patterning process comprises: forming a gate metal film on the passivation layer; The photoresist is spin-coated on the gate metal film, and the photoresist is exposed and developed using a mask to obtain a completely removed photoresist area and a completely photoresist reserved area; Etching the insulating substrate to etch away the passivation layer film in the area where the photoresist is completely removed; The photoresist in the photoresist completely reserved area is stripped to obtain the pattern layer of the gate electrode and the gate line. 6. A method for manufacturing an organic thin film transistor array substrate, characterized in that the method comprises: Forming the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode on the insulating substrate through a patterning process; The organic semiconductor layer covering the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode, the gate insulating layer covering the organic semiconductor layer, and the gate electrode and the gate electrode covering the gate insulating layer are formed by one patterning process. Graphics layer for lines; A passivation layer is formed on the insulating substrate on which the pattern layer of the gate electrode and the gate line is formed through a patterning process; The pattern layer covering the pixel electrode on the passivation layer is formed by a patterning process; the organic semiconductor layer covering the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode are formed by a patterning process, covering the organic layer. The gate insulating layer on the semiconductor layer, and the pattern layer covering the gate electrode and the gate line on the gate insulating layer include: Form the organic semiconductor layer film covering the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode; form the gate insulating layer film covering the organic semiconductor layer film; form the gate metal film covering the gate insulating layer film film; Spin-coat the photoresist on the gate metal film, expose and develop the photoresist, and obtain the photoresist completely removed area and the photoresist completely reserved area; Etching the insulating substrate to etch away the gate metal thin film, gate insulating layer thin film and organic semiconductor layer thin film in the region where the photoresist is completely removed; The photoresist in the photoresist completely reserved area is peeled off to obtain the patterned layer of the organic semiconductor layer, the patterned layer of the gate insulating layer, the patterned layer of the gate electrode and the gate line, and part of the patterned layer of the drain electrode is exposed. 7. The method according to claim 6, characterized in that, forming the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode on the insulating substrate through a patterning process comprises: Depositing metal thin films on insulating substrates; Spin-coat photoresist on the metal film, use a mask to expose and develop the photoresist, and obtain the photoresist completely removed area and the photoresist completely reserved area; Etching the insulating substrate to etch away the metal film in the area where the photoresist is completely removed; The photoresist in the photoresist completely reserved area is stripped to obtain the pattern layer of the source electrode and the data line and the pattern layer of the drain electrode. 8. The method according to claim 6, characterized in that, after forming the gate insulating film and before forming the gate metal film, the method further comprises: The insulating substrate is dried for a set time at a first set temperature, and the insulating substrate is dried for a set time at a second set temperature, and the second set temperature is greater than the first set temperature. 9. The method according to claim 6, wherein forming a passivation layer on the insulating substrate with a pattern layer of a gate electrode and a gate line through a patterning process comprises: forming a passivation layer film on the insulating substrate with the pattern layer of the gate electrode and the gate line; The photoresist is spin-coated on the passivation layer film, and the photoresist is exposed and developed using a mask to obtain a completely removed area of the photoresist and a completely retained area of the photoresist. The completely removed area of the photoresist is located in the data line PAD area, The exposed pattern layer area of the gate line PAD area and the drain electrode; Etching the insulating substrate to etch away the passivation layer film in the area where the photoresist is completely removed; The photoresist in the region where the photoresist is completely reserved is stripped to obtain a passivation layer. 10. The method according to claim 6, wherein the formation of the pattern layer covering the pixel electrode on the passivation layer through a patterning process comprises: Depositing a transparent conductive film on an insulating substrate; The photoresist is spin-coated on the transparent conductive film, and the photoresist is exposed and developed using a mask to obtain a completely removed region of the photoresist and a completely retained region of the photoresist, and the completely retained region of the photoresist is located at the exposed area of the drain electrode. a patterned layer region and a passivation layer region covering the patterned layer of the drain electrode; Etching the insulating substrate to etch away the passivation layer film in the area where the photoresist is completely removed; The photoresist in the region where the photoresist is completely reserved is stripped to obtain the pattern layer of the pixel electrode.