CN102683278A - Chip separation method - Google Patents
Chip separation method Download PDFInfo
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- CN102683278A CN102683278A CN2011100543432A CN201110054343A CN102683278A CN 102683278 A CN102683278 A CN 102683278A CN 2011100543432 A CN2011100543432 A CN 2011100543432A CN 201110054343 A CN201110054343 A CN 201110054343A CN 102683278 A CN102683278 A CN 102683278A
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- 238000000926 separation method Methods 0.000 title claims abstract description 26
- 238000012360 testing method Methods 0.000 claims abstract description 50
- 238000012544 monitoring process Methods 0.000 claims abstract description 47
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 239000002184 metal Substances 0.000 claims abstract description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 30
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 12
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 238000005516 engineering process Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000000227 grinding Methods 0.000 claims description 7
- 150000004767 nitrides Chemical class 0.000 claims description 6
- 229910052757 nitrogen Inorganic materials 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000005192 partition Methods 0.000 claims description 5
- 230000004224 protection Effects 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000005530 etching Methods 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 6
- 238000009826 distribution Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052681 coesite Inorganic materials 0.000 description 2
- 229910052906 cristobalite Inorganic materials 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 229910052682 stishovite Inorganic materials 0.000 description 2
- 229910052905 tridymite Inorganic materials 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
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Abstract
The invention discloses a chip separation method which comprises the following steps: setting positions of a plurality of testing and monitoring pattern structures formed on a wafer, wherein the width of separation trenches among all chips is less than 20 microns at least in one direction; forming a separation trench etching mask; using the separation trench etching mask to etch dielectric films of the separation trenches or the dielectric films and metal films, as well as a substrate below the separation trenches; and separating one chip from another through back thinning and pressure application. According to the method, the width of the separation trenches among all chips can be reduced, and the separation stability and chip reliability can be improved.
Description
Technical field
The present invention relates to a kind of semiconductor integrated circuit method of manufacturing technology, particularly relate to the separation method of a kind of chip and chip.
Background technology
As shown in Figure 1, be the distribution schematic diagram of prior art chips on wafer.On wafer, form a plurality of chips 2 and a plurality of test and monitoring pattern structure 3A and 3B, each said chip chamber is formed with separating tank; Wherein, said test and monitoring pattern structure 3A are parallel to Y axle, said test and monitoring pattern structure 3B and are parallel to the X axle.The formation of said chip 2 and test and monitoring pattern structure 3A and 3B will be passed through multiexposure, multiple exposure, includes a plurality of said chips 2 and a plurality of test and monitoring pattern structure 3A and 3B in each exposure field 1.Test and monitoring pattern structure 3A are positioned among the separating tank 4B that is parallel to the Y axle in the exposure field 1, and test and monitoring pattern structure 3B are positioned among the separating tank 4A that is parallel to the X axle in the exposure field 1.The separating tank 4C that is parallel to the Y axle between said exposure field 1 does not place test and monitoring pattern structure with being parallel among the separating tank 4D of X axle.
The preceding end production process that the said chip of formation need pass through on said wafer is for forming active device, passive device, metal interconnection, surface passivation, lead wire outlet.After end production process is accomplished before said, usually will be through grinding back surface with said wafer, with said wafer grinding to for example 150 microns～300 microns of the thickness that needs; Utilize saw blade that the separating tank between chip and the chip is severed afterwards, thereby realize the separation between chip and the chip.The chip of separating through packaging and testing, has just been obtained final product.
The width of separating tank 4A, 4B, 4C and 4D is generally all at 60 microns～100 microns in the prior art; Bigger at chip area; For example greater than under 100 square millimeters the situation, the width of said separating tank can be ignored to the influence of the chip count on the unit wafer.But one side is along with chip integration improves constantly, and the size of chip constantly promptly reduces; The area of some application chips is very little on the other hand, and the little area that arrives is under 1 square millimeter, and at this moment the width of said separating tank just has very large influence to the chip count on the unit wafer.For example, for the chip of size at 1 millimeter * 1 millimeter, when the size of separating tank when 60 microns are reduced to 10 microns, chip-count total on the unit wafer of 200 mm sizes can have the increase greater than 8%.
Under prior art; The width of separating tank is mainly by the decision of two factors, the one, the width of saw blade and corresponding scribing technology, when separating tank less than certain width for example 60 microns the time; Need special blade and technology; In this technology, be coarse through the edge of chip after the scribing, in some cases even have a quality that small slight crack has influence on chip.The width that test that another factor is in separating tank to be placed and monitoring pattern structure need; The test structure here comprises key size measuring figure, thickness resolution chart, gash depth resolution chart, process control monitoring test structure (PCM), wafer grade reliability test structure etc.; The monitoring pattern structure is alignment patterns mask aligner the is arranged alignment mark that uses, a test structure of alignment precision etc.; In the time of need the width of separating tank being reduced, solve the correlation technique problem of above-mentioned two factors simultaneously with regard to needs.
Summary of the invention
Technical problem to be solved by this invention provides the separation method of a kind of chip and chip, can the width of the separating tank of chip and chip chamber be reduced to below 20 microns, can improve stability and the chip reliability cut apart.
For solving the problems of the technologies described above, the separation method of chip provided by the invention and chip comprises the steps:
Step 3, utilize said separating tank etch mask version on said wafer, to form litho pattern; Said litho pattern is made up of the photoresist groove that photoresist is etched; Said photoresist channel shaped is formed in each said separating tank top, and the perimeter of said photoresist groove is all by the photoresist covering protection.
Step 4, utilize said photoresist, adopt dry method or wet-etching technology, the deielectric-coating of said photoresist beneath trenches or deielectric-coating and metal film are etched away as mask.
Step 5, utilize said photoresist, utilize dry etching or wet method to add dry etch process, the segment thickness of the substrate of said wafer is etched away, on the said wafer of said photoresist beneath trenches, form said groove figure at last as mask.
Step 6, said front wafer surface is protected; Through said chip back surface is ground; To the thickness that needs, this thickness guarantees that each groove of the said groove figure that the front of said wafer forms does not expose and each said chip chamber does not separate with said wafer grinding.
The cylinder that step 7, utilization are evenly rotated exerts pressure for said wafer, and each said chip is separated from each other.
Further improve is that the zone of test and monitoring pattern structure described in the step 1 is length and width and the equal zone of one or more chip area; Comprise step during formation: when mask designs, on mask, separate said test and monitoring pattern structural region through photo-shield strip with said chip area; In exposure, said chip area and said test and monitoring pattern structural region made public respectively realize; Said groove width between all chips and the chip is 2 microns～20 microns.Perhaps, said test in the step 1 and monitoring pattern structure are positioned in the said chip of part and the said separating tank between the chip in the same exposure field, and other width of not placing the separating tank of said test and monitoring pattern structure is 2 microns～20 microns.Perhaps; Said test in the step 1 and monitoring pattern structure are positioned over the outside of outermost chip of outside or adjacent exposure field of the outermost chip of same exposure field, and other width of not placing the separating tank of said test and monitoring pattern structure is 2 microns～20 microns.Perhaps, in the zone that equates with one or more said chip areas that said test in the step 1 and monitoring pattern structure are positioned over same exposure field, the said groove width between all chips and the chip is 2 microns～20 microns.
Further improving is that the width of each said photoresist groove is 1 micron～10 microns in the step 3.
Further improve and be, deielectric-coating described in the step 4 is combination or the combination of oxide-film and nitrogen oxidation film and nitride film of combination, oxide-film and the nitrogen oxidation film of oxide-film, oxide-film and nitride film.
Further improving is that the thickness that is etched away of the substrate of wafer described in the step 5 is 20 microns～200 microns.
Further improve is that the thickness of the substrate of the said wafer after grinding in the step 6 is 50 microns～300 microns.
Further improve and be, each said chip and the groove between adjacent chips that the graphic structure of the etch mask of separating tank described in step 2 version satisfies the said groove figure that forms be link together fully or each said chip and adjacent chips between groove between have 1 micron～10 microns long partition district that does not form groove.
The present invention is provided with through the position that said a plurality of tests and monitoring pattern structure is formed at said wafer, can reduce the width of the separating tank of each chip chamber, and can the width of the separating tank of chip and chip chamber be reduced to below 20 microns.The present invention is through adopting a said separating tank etch mask version; Can in said separating tank, form groove figure; And can chip be separated with chip; Avoid like this in the prior art owing to the technological problem of bringing that influences product quality of the scribing of adopting blade, so the present invention can also improve stability and the chip reliability of cutting apart.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is done further detailed explanation:
Fig. 1 is the distribution schematic diagram of prior art chips on wafer;
Fig. 2 is the flow chart of the embodiment of the invention;
Fig. 3 is the distribution schematic diagram of first kind of chip on wafer of the embodiment of the invention;
Fig. 4 is the distribution schematic diagram of second kind of chip on wafer of the embodiment of the invention;
Fig. 5 is the third distribution schematic diagram on wafer of the embodiment of the invention;
Fig. 6 is the 4th kind of distribution schematic diagram on wafer of the embodiment of the invention;
Fig. 7 A-7D is the profile of wafer in the separation process of the embodiment of the invention;
Fig. 8 A is first kind of structural representation of the separating tank etch mask version of the embodiment of the invention;
Fig. 8 B is second kind of structural representation of the separating tank etch mask version of the embodiment of the invention.
Embodiment
As shown in Figure 2, the separation method of embodiment of the invention chip and chip comprises the steps:
Said a plurality of test and the formation position of monitoring pattern structure 3A on wafer comprise following several kinds of structures:
As shown in Figure 3, the zone of said test and monitoring pattern structure 3A is length and width and the equal zone of one or more chip area; Comprise step during formation: when mask designs, on mask, separate said test and monitoring pattern structure 3A zone with said chip 2 zone passage photo-shield strips; In exposure, said chip 2 regional exposures respectively with said test and monitoring pattern structure 3A zone are realized; The width of said separating tank 4A, 4B, 4C and 4D between all chips and the chip is 1 micron～20 microns.
As shown in Figure 4; Said test and monitoring pattern structure 3A are positioned in the said chip 2 of part and the said separating tank 4B1 between the chip 2 in the same exposure field 1, and other width of not placing separating tank 4A, 4B, 4C and the 4D of said test and monitoring pattern structure 3A is 1 micron～20 microns.The width of said separating tank 4B1 is greater than said test and monitoring pattern structure 3A and by the width decision of said test and monitoring pattern structure 3A.The direction of the said separating tank 4B1 of said test of placement shown in Fig. 4 and monitoring pattern structure 3A is a direction and along the Y axle; Said separating tank 4B1 also can be for a direction and along the X axle, and the quantity on its direction of said separating tank 4B1 is 1 or the least possible many; Said separating tank 4B1's also can be for also being parallel to many of Y axle along being parallel to the X axle, and the quantity of the said separating tank 4B1 of each direction is 1 or the least possible many.
As shown in Figure 5; Said test and monitoring pattern structure 3A are positioned among the separating tank 4C1 of outside of outermost chip 2 of same exposure field 1 or among the separating tank 4C1 of the outside of the outermost chip 2 of adjacent exposure field 1, other width of not placing separating tank 4A, 4B, 4C and the 4D of said test and monitoring pattern structure 3A is 1 micron～20 microns.The width of said separating tank 4C1 is greater than said test and monitoring pattern structure 3A and by the width decision of said test and monitoring pattern structure 3A.The 4C1's of separating tank described in Fig. 5 is a direction and along the Y axle, and the direction of said separating tank 4C1 also can be for being a direction and along the X axle, the quantity on its direction of said separating tank 4C1 is 1 or 2; Said separating tank 4C1's also can be for also being parallel to many of Y axle along being parallel to the X axle, and the quantity of the said separating tank 4C1 of each direction is 1 or 2.
As shown in Figure 6; In the zone that equates with one or more said chip 2 areas that said test and monitoring pattern structure 3A are positioned over same exposure field 1, the width of said separating tank 4A, 4B, 4C and 4D between all chips 2 and the chip 2 is 1 micron～20 microns.
Shown in Fig. 7 A, the formation of the embodiment of the invention profile of the said wafer behind said chip 2 and said test and monitoring pattern structure 3A and the said separating tank.On the P of said wafer type substrate, be formed with trap, in trap, be formed with active device, said active device is some metal-oxide-semiconductors, includes grid 721 and source-drain area, isolates through an oxygen 723 between active device.On substrate, be formed with passive device such as resistance, electric capacity, inductance etc. (not shown); Most peripheral at said chip 2 has shading ring 731A, 731B.Be formed with the multiple layer metal layer on the device, like ground floor metal 724, top-level metallic 727; And multilayer dielectricity layer; Dielectric layer 722, the dielectric layer 725 of metal interlevel and the dielectric layer 728 and 729 on the top-level metallic 727 like 724 on device and ground floor metal; Wherein dielectric layer 728 is HDP-SiO2 or PECVD SiO2, and said dielectric layer 729 is P-SiON or SiN.
Step 3, shown in Fig. 7 A; Utilize said separating tank etch mask version on said wafer, to form litho pattern; Said litho pattern is made up of the photoresist groove that photoresist 740 is etched; Said photoresist channel shaped is formed in each said separating tank top, and the width of each said photoresist groove is 1 micron～10 microns.The perimeter of said photoresist groove is all by photoresist 740 covering protections.
Step 4, shown in Fig. 7 B, utilize said photoresist 740 as mask, adopt dry method or wet-etching technology, the deielectric-coating of said photoresist beneath trenches or deielectric-coating and metal film are etched away.Said deielectric-coating is combination or the combination of oxide-film and nitrogen oxidation film and nitride film of combination, oxide-film and the nitrogen oxidation film of oxide-film, oxide-film and nitride film.
Step 5, shown in Fig. 7 C; Utilize said photoresist 740 as mask; Utilize dry etching or wet method to add dry etch process; With 20 microns～200 microns the thickness of etching away of the substrate of said wafer, on the said wafer of said photoresist beneath trenches, form said groove figure at last.Corresponding to the said separating tank etch mask version shown in Fig. 8 A and 8B, between the groove between that the groove of said groove figure is respectively connection or adjacent chips 1 micron～10 microns long partition district that does not form groove is arranged.
Step 6, shown in Fig. 7 D, said front wafer surface is protected, through said chip back surface is ground, be 50 microns～300 microns to thickness with said wafer grinding.This thickness guarantees that each groove of the said groove figure that the front of said wafer forms does not expose and 2 of each said chips do not separate.
The cylinder that step 7, utilization are evenly rotated exerts pressure for said wafer, and each said chip 2 is separated from each other.
More than through specific embodiment the present invention has been carried out detailed explanation, but these are not to be construed as limiting the invention.Under the situation that does not break away from the principle of the invention, those skilled in the art also can make many distortion and improvement, and these also should be regarded as protection scope of the present invention.
Claims (10)
1. the separation method of chip and chip is characterized in that, comprises the steps:
Step 1, on wafer, form a plurality of chips and a plurality of test and monitoring pattern structure; Each said chip chamber is formed with separating tank; Each said chip is isolated mutually through separating tank, and the width of the separating tank between each said chip and adjacent chips is at least in one direction less than 20 microns;
Step 2, the separating tank etch mask version that in the separating tank of each said chip chamber, forms groove figure that forms, the graphic structure of said separating tank etch mask version satisfy the width of the width of identical and each the said groove figure of the graphic structure of separating tank of the said groove figure that forms and each said chip chamber less than the said separating tank of correspondence;
Step 3, utilize said separating tank etch mask version on said wafer, to form litho pattern; Said litho pattern is made up of the photoresist groove that photoresist is etched; Said photoresist channel shaped is formed in each said separating tank top, and the perimeter of said photoresist groove is all by the photoresist covering protection;
Step 4, utilize said photoresist, adopt dry method or wet-etching technology, the deielectric-coating of said photoresist beneath trenches or deielectric-coating and metal film are etched away as mask;
Step 5, utilize said photoresist, utilize dry etching or wet method to add dry etch process, the segment thickness of the substrate of said wafer is etched away, on the said wafer of said photoresist beneath trenches, form said groove figure at last as mask;
Step 6, said front wafer surface is protected; Through said chip back surface is ground; To the thickness that needs, this thickness guarantees that each groove of the said groove figure that the front of said wafer forms does not expose and each said chip chamber does not separate with said wafer grinding;
The cylinder that step 7, utilization are evenly rotated exerts pressure for said wafer, and each said chip is separated from each other.
2. the separation method of chip and chip according to claim 1, it is characterized in that: the zone of test described in the step 1 and monitoring pattern structure is length and width and the equal zone of one or more chip area; Comprise step during formation: when mask designs, on mask, separate said test and monitoring pattern structural region through photo-shield strip with said chip area; In exposure, said chip area and said test and monitoring pattern structural region made public respectively realize; Said groove width between all chips and the chip is 2 microns～20 microns.
3. the separation method of chip and chip according to claim 1; It is characterized in that: said test in the step 1 and monitoring pattern structure are positioned in the said chip of part and the said separating tank between the chip in the same exposure field, and other width of not placing the separating tank of said test and monitoring pattern structure is 2 microns～20 microns.
4. the separation method of chip and chip according to claim 1; It is characterized in that: said test in the step 1 and monitoring pattern structure are positioned in the said separating tank of outside of outermost chip of same exposure field or in the said separating tank of the outside of the outermost chip of adjacent exposure field, other width of not placing the separating tank of said test and monitoring pattern structure is 2 microns～20 microns.
5. the separation method of chip and chip according to claim 1; It is characterized in that: in the zone that equates with one or more said chip areas that said test in the step 1 and monitoring pattern structure are positioned over same exposure field, the said groove width between all chips and the chip is 2 microns～20 microns.
6. the separation method of chip and chip according to claim 1, it is characterized in that: the width of each said photoresist groove is 1 micron～10 microns in the step 3.
7. the separation method of chip and chip according to claim 1 is characterized in that: deielectric-coating described in the step 4 is combination or the combination of oxide-film and nitrogen oxidation film and nitride film of combination, oxide-film and the nitrogen oxidation film of oxide-film, oxide-film and nitride film.
8. the separation method of chip and chip according to claim 1, it is characterized in that: the thickness that is etched away of the substrate of wafer described in the step 5 is 20 microns～200 microns.
9. the separation method of chip and chip according to claim 1, it is characterized in that: the thickness of the substrate of the said wafer after grinding in the step 6 is 50 microns～300 microns.
10. the separation method of chip and chip according to claim 1 is characterized in that: each said chip and the groove between adjacent chips that the graphic structure of the etch mask of separating tank described in step 2 version satisfies the said groove figure that forms be link together fully or each said chip and adjacent chips between groove between have 1 micron～10 microns long partition district that does not form groove.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2011100543432A CN102683278A (en) | 2011-03-08 | 2011-03-08 | Chip separation method |
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| CN2011100543432A CN102683278A (en) | 2011-03-08 | 2011-03-08 | Chip separation method |
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| CN102683278A true CN102683278A (en) | 2012-09-19 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105810576A (en) * | 2015-01-20 | 2016-07-27 | 英飞凌科技股份有限公司 | Wafer cutting method and semiconductor chip |
| CN107733389A (en) * | 2017-11-01 | 2018-02-23 | 应达利电子股份有限公司 | A kind of quartz crystal is large stretch of and manufactures the method for small chips using it |
| CN115206961A (en) * | 2022-07-29 | 2022-10-18 | 上海华力微电子有限公司 | Chip layout structure and wafer cutting method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105810576A (en) * | 2015-01-20 | 2016-07-27 | 英飞凌科技股份有限公司 | Wafer cutting method and semiconductor chip |
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| CN115206961A (en) * | 2022-07-29 | 2022-10-18 | 上海华力微电子有限公司 | Chip layout structure and wafer cutting method |
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Effective date of registration: 20140103 Address after: 201203 Shanghai city Zuchongzhi road Pudong New Area Zhangjiang hi tech Park No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201206, Shanghai, Pudong New Area, Sichuan Road, No. 1188 Bridge Applicant before: Shanghai Huahong NEC Electronics Co., Ltd. |
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Application publication date: 20120919 |