CN102683338A - Low-temperature polycrystalline silicon TFT (Thin Film Transistor) array substrate and manufacturing method thereof - Google Patents

Abstract

Embodiments of the present invention provide a low-temperature polysilicon TFT array substrate and a manufacturing method thereof, which relate to the field of manufacturing liquid crystal displays and AMOLED displays, and reduce the number of patterning processes, thereby simplifying the manufacturing process and reducing manufacturing costs. The method is as follows: forming a buffer layer on the substrate; forming a polysilicon layer on the buffer layer; forming a first metal layer on the polysilicon layer; A metal layer and a polysilicon layer are subjected to a patterning process, and patterns of data lines, source electrodes, drain electrodes and polysilicon semiconductor parts are obtained through one patterning process. The embodiment of the present invention is used in the manufacture of a low-temperature polysilicon TFT array substrate.

Description

A low-temperature polysilicon TFT array substrate and its manufacturing method

technical field

The invention relates to the field of manufacturing liquid crystal displays and AMOLED displays, in particular to a low-temperature polysilicon TFT (Thin Film Transistor, Thin Film Field Effect Transistor) array substrate and a manufacturing method thereof.

Background technique

Due to the defects of amorphous silicon itself, such as low on-state current, low mobility, and poor stability caused by too many defects, it has been restricted in many fields. Field of application, LTPS (Low Temperature Poly-Silicon, low temperature polysilicon) technology came into being.

As shown in Fig. 1 and Fig. 2, the manufacturing method of the low-temperature polysilicon TFT array substrate in the prior art includes:

S101 , forming a buffer layer 12 on a substrate 11 .

S102 , forming a polysilicon active layer pattern on the buffer layer through the first patterning process.

S103 , depositing an inorganic material on the entire surface of the polysilicon active layer pattern to form a first insulating layer 14 .

S104 , through the second patterning process, form a gate line and a gate 15 on the insulating layer, and then perform doping and activation on the polysilicon to form a polysilicon semiconductor active layer 13 .

S105 , forming a second insulating layer 16 on the gate line and the gate 15 .

S106 , through the third patterning process, form source via holes 17 a and drain via holes 17 b on the first insulating layer 14 and the second insulating layer 16 , exposing the active layer 13 .

S107. Through the fourth patterning process, a data line, a source electrode 18a and a drain electrode 18b are formed, wherein the source electrode 18a is connected to the active layer 13 through the source via hole 17a, and the drain electrode 18b is connected to the active layer 13 through the drain via hole 17b. Active layer connection 13 .

S108 , forming a protection layer 19 on the data line, the source electrode 18 a and the drain electrode 18 b, and forming a via hole above the drain electrode 18 b through a fifth patterning process to expose the drain electrode 18 b.

S109 , forming an ITO pixel electrode 20 through the sixth patterning process, and the ITO pixel electrode 20 is connected to the drain electrode 18 b through a via hole.

S110 , forming a planarization layer 21 on the substrate through a seventh patterning process.

It can be seen from the above that in the prior art, in the manufacturing process of the low-temperature polysilicon TFT array substrate, a total of at least 7 patterning processes are required, the manufacturing process is complicated, the manufacturing process is numerous, the material consumption is high, and the processing time and processing time are increased cost.

Contents of the invention

Embodiments of the present invention provide a low-temperature polysilicon TFT array substrate and a manufacturing method thereof, which reduce the number of patterning processes, thereby simplifying the manufacturing process and reducing manufacturing costs.

In order to achieve the above object, embodiments of the present invention adopt the following technical solutions:

On the one hand, a low-temperature polysilicon TFT array substrate is provided, including:

Substrate;

forming a polysilicon semiconductor active layer on the buffer layer;

A source and a drain are formed on the polysilicon semiconductor active layer; the source, drain and the polysilicon semiconductor active layer form a TFT region;

A gate insulating layer is formed on the source and the drain;

A gate and a gate line are formed on the gate insulating layer;

A protection layer is formed on the gate and the gate line;

A pixel electrode layer is formed on the protection layer, and the pixel electrode layer is connected to the drain through a via hole on the protection layer and the gate insulating layer.

Also includes:

Before forming the polysilicon semiconductor active layer, a buffer layer is formed on the substrate.

On the other hand, a method for manufacturing a low-temperature polysilicon TFT array substrate is provided, including:

forming a polysilicon layer on the substrate;

A first metal layer is formed on the polysilicon layer, and a patterning process is performed on the first metal layer and the polysilicon layer by using a gray tone mask or a semi-transparent mask, and the data lines, the polysilicon layer are obtained through the first patterning process, Patterning of source, drain and polysilicon semiconductor parts;

forming gate lines and gates on the gate insulating layer through a second patterning process;

forming a gate insulating layer on the pattern of the source electrode, the drain electrode, and the polysilicon semiconductor portion;

Doping the portion between the source and the drain of the polysilicon layer to form a channel region with the source and the drain;

forming a protective layer on the gate line and the gate, and forming a via hole at the drain through a third patterning process to expose the drain;

forming a pixel electrode layer on the protection layer, the pixel electrode layer is connected to the drain through the via hole;

Forming the pixel electrode pattern through the fourth patterning process;

A planarization layer pattern is formed on the pixel electrode through a fifth patterning process.

In the low-temperature polysilicon TFT array substrate and its manufacturing method provided by the embodiments of the present invention, after a buffer layer is formed on the substrate, and a polysilicon layer and a metal layer are coated, the metal layer and the polysilicon layer are patterned by HTM or GTM. The process obtains a pattern including data lines, source electrodes, drain electrodes, and polysilicon semiconductor parts. Compared with the prior art, a patterning process is first performed to obtain the polysilicon active layer pattern, and then a patterning process is performed to obtain the connection part between the source and drain electrodes and the active layer, and then a patterning process is performed to obtain the source and drain. The process of exposure is reduced, thereby reducing the complexity of the process, and a layer of protective layer is reduced, thereby reducing the complexity of the process, saving materials, and reducing the processing cost while shortening the processing time.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. Those skilled in the art can also obtain other drawings based on these drawings without creative work.

Fig. 1 is the schematic flow chart of the manufacturing method of existing low-temperature polysilicon TFT array substrate;

FIG. 2 is a schematic structural view of an existing low-temperature polysilicon TFT array substrate;

Figure 3a is a schematic diagram of photoresist exposure using a gray tone mask;

Figure 3b is a schematic diagram of photoresist exposure using a semi-transparent mask;

4 is a schematic flowchart of a method for manufacturing a polysilicon TFT array substrate provided in Embodiment 1 of the present invention;

FIG. 5A is a first schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

FIG. 5B is a second schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

5C is a third schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

FIG. 5D is a fourth schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

FIG. 5E is a fifth schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

FIG. 5F is a sixth schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

FIG. 5G is a seventh schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

FIG. 5H is an eighth schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

5I is a ninth schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

5G is a tenth schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

FIG. 5K is an eleventh schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

FIG. 5L is a twelfth schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

FIG. 5M is a thirteenth schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

FIG. 5N is a fourteenth schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

FIG. 50 is a fifteenth schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

FIG. 5P is a sixteenth schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

FIG. 5Q is a seventeenth schematic diagram of manufacturing a polysilicon TFT array substrate provided by an embodiment of the present invention;

6 is a schematic flowchart of a method for manufacturing a polysilicon TFT array substrate provided by Embodiment 2 of the present invention;

FIG. 7 is a schematic flowchart of a method for manufacturing a polysilicon TFT array substrate according to Embodiment 4 of the present invention.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

Embodiment one

The method for manufacturing a low-temperature polysilicon TFT array substrate provided in Embodiment 1 of the present invention is described by taking the manufacture of a low-temperature polysilicon TFT array substrate by using a gray tone mask (GTM) as an example.

First, the main principle of the GTM process will be described with reference to FIG. 3a. The GTM mask plate uses the grating effect to make the intensity of the transmitted light different in different areas, so that the photoresist can be selectively exposed and developed. FIG. 3 a shows the process of exposing the photoresist by using the GTM mask 21 . In the GTM mask 21 , a transparent area 211 , an opaque area 212 and a translucent area 213 are included. The photoresist 22 is in a state after exposure, wherein the region 221 corresponds to the transparent region 211 of the GTM mask 21, the region 222 corresponds to the opaque region 212 of the GTM mask 21, and the region 223 corresponds to the translucent region of the GTM mask 21 213. The photoresist 23 is in a state after development, wherein the region 231 corresponds to the transparent region 211 of the GTM mask 21, the region 232 corresponds to the opaque region 212 of the GTM mask 21, and the region 233 corresponds to the translucent region of the GTM mask 21 213.

The manufacturing method of the low-temperature polysilicon TFT array substrate using GTM provided by Embodiment 1 of the present invention will be described below with reference to FIG. 4 and FIGS. 5A to 5Q .

S401, forming a buffer layer on the substrate.

In order to prevent harmful substances in the glass substrate, such as alkali metal ions, from affecting the performance of the polysilicon layer, pre-cleaning (Pre-clean) is performed before depositing the buffer layer. Specifically, firstly, the glass substrate is cleaned through the initial clean process, and the cleanliness must meet the requirements of particles ≤ 300ea (particle size ≥ 1um). Then, as shown in FIG. 5A , a buffer layer 52 is deposited on the glass substrate 51 by PECVD.

S402, forming a polysilicon layer on the buffer layer.

As shown in FIG. 5B , a layer of amorphous silicon layer is deposited on the buffer layer 52 by PECVD method, and a high-temperature oven is used to dehydrogenate the amorphous silicon layer to prevent hydrogen explosion during the crystallization process and reduce crystallization. The effect of the density of defect states in the thin film. After the dehydrogenation process is completed, the LTPS process is carried out, and the amorphous silicon layer is crystallized by laser annealing (ELA), metal-induced crystallization (MIC), solid-phase crystallization (SPC) and other crystallization methods. Polysilicon layer 53 is formed on layer 52 .

S403 , forming a first metal layer for data lines, source electrodes, and drain electrodes on the polysilicon layer.

As shown in FIG. 5C , a first metal layer 54 is deposited on the polysilicon layer by a sputtering process.

S404 , using a gray tone mask to perform a patterning process on the first metal layer and the polysilicon layer, and obtain patterns of data lines, source electrodes, drain electrodes, and polysilicon semiconductor parts through one patterning process.

As shown in FIG. 5D , a layer of photoresist 55 is coated on the substrate with the above structure, and then the photoresist 55 is exposed by GTM process. On the GTM mask plate 70, for the TFT region, the part corresponding to the data line (not shown in the figure), the source electrode and the drain region is an opaque region 702, and the part corresponding to the region between the source and drain regions is a translucent region 703 .

As shown in Figure 5F, it is a schematic diagram of the state of the above-mentioned photoresist 55 after exposure, wherein the region 551 of the photoresist 55 corresponds to the opaque region 702 of the GTM mask 70, and the region 552 of the photoresist 55 corresponds to the GTM mask The translucent area 703 of 70.

As shown in Figure 5G, it is a schematic diagram of the state of the photoresist 55 after development, wherein the region 551 of the photoresist 55 is a completely reserved region of photoresist, the region 552 of the photoresist 55 is a semi-retained region of photoresist, and others The regions are photoresist completely removed regions.

Then, as shown in FIG. 5H, the first metal layer 54 in the photoresist completely removed region is etched using a wet etching (Wet Etch) process, and then the polysilicon layer 53 is etched using a dry etching (Dry Etch) process. Etching is performed.

Then, as shown in FIG. 5I, after plasma ashing treatment, the photoresist in the photoresist semi-retained region 552 of the photoresist 55 is etched away, leaving the photoresist in the photoresist completely reserved region 551. The photoresist completely reserved region 551 corresponds to the source and drain regions.

Then, as shown in FIG. 5J , the first metal layer 54 in the photoresist semi-retained region 552 is etched a second time through a wet etching process.

Then, as shown in FIG. 5K , the source electrode 542 and the drain electrode 541 are obtained after stripping off the photoresist in the photoresist completely reserved region 551 .

So far, in this embodiment, a pattern including the data line, the source electrode, the drain electrode, and the polysilicon active layer is obtained through one GTM patterning process. Compared with the prior art, the first patterning process is used to obtain the polysilicon active layer pattern, and then a patterning process is performed to obtain the connecting part of the source, drain and active layer, and then a patterning process is performed to obtain the source, drain and active layer. As far as the drain electrode is concerned, the process of exposure is reduced, thereby reducing the complexity of the process, shortening the processing time and reducing the processing cost.

S405 , forming a gate insulating layer on the pattern of the source, the drain and the polysilicon semiconductor part, and then performing channel region doping treatment, so as to form a channel region with the source and the drain.

As shown in FIG. 5L, on the source electrode 541 and the drain electrode layer 542, the gate insulating layer 56 is deposited by the PECVD method, and then the channel is formed by using an ion bath or ion implantation method through a self-alignment process (Self Align) method. The doping treatment of the region 531 is to make the channel region 531 form a P-N junction with the source and drain regions, so that the TFT forms a MOS switch structure.

S406, forming a gate line and a gate on the gate insulating layer.

As shown in FIG. 5M , on the gate insulating layer 56 , a second metal layer of the gate is formed by sputtering, and then processed by a second patterning process to form a gate line (not shown in the figure) and a gate 57 .

S407 , forming a protective layer (PVX) on the gate line and the gate.

As shown in FIG. 5N , on the gate 57 , a protective layer 58 is deposited by PECVD to protect the gate.

S408, forming connection via holes on the gate insulating layer and the protection layer.

As shown in FIG. 5O, through the third patterning process, a connection via hole 59' penetrating through the gate insulating layer 56 and the protective layer 58 is formed on the gate insulating layer 56 and the protective layer 58, exposing the drain electrode 542 for making The drain is connected to the pixel electrode.

S409 , forming a pixel electrode layer on the protection layer, and connecting the pixel electrode layer to the drain through a via hole.

As shown in FIG. 5P, a layer of ITO (Indium TinOxide, indium tin oxide semiconductor) is deposited on the protective layer 58 by using the PECVD method, and then processed by the fourth patterning process to obtain the pixel electrode 59, and the pixel electrode 59 is connected through the via hole. 59 ′ is connected to the drain 542 .

S410, forming a planarization layer on the pixel electrode.

As shown in FIG. 5Q, deposit a layer of protection layer 90 on the pixel electrode 59 to planarize and protect the edge of the ITO pixel electrode. Materials such as synthetic resin (Resin) or an insulating layer can be used, and then the fifth patterning process is used to form the corresponding graph.

In the manufacturing method of the low-temperature polysilicon TFT array substrate provided by the embodiment of the present invention, after forming a buffer layer on the substrate, coating the polysilicon layer and the metal layer, the metal layer and the polysilicon layer are patterned by GTM. Patterns of data lines, source electrodes, drain electrodes, and polysilicon semiconductor parts. Compared with the prior art, a patterning process is first performed to obtain the polysilicon active layer pattern, and then a patterning process is performed to obtain the connection part between the source and drain electrodes and the active layer, and then a patterning process is performed to obtain the source and drain. The process of exposure is reduced, and a layer of protective layer is reduced, thereby reducing the complexity of the process, saving materials, and reducing the processing cost while shortening the processing time.

Embodiment two

The method for manufacturing a low-temperature polysilicon TFT array substrate provided in Embodiment 2 of the present invention is described by taking the manufacture of a low-temperature polysilicon TFT array substrate by using a semi-transparent mask (HTM) as an example.

First, the main principle of the HTM process will be described with reference to FIG. 3b. The HTM mask plate is used to selectively expose and develop the photoresist through the different intensity of light transmitted in different regions. FIG. 3 b shows the process of exposing the photoresist by using the HTM mask 31 . In the HTM mask 31 , a transparent area 311 , an opaque area 312 and a translucent area 313 are included. The photoresist 32 is the state after exposure, wherein, the region 321 corresponds to the transparent region 311 of the HTM mask 31, the region 322 corresponds to the opaque region 312 of the HTM mask 31, and the region 323 corresponds to the translucent region of the HTM mask 31 313. The photoresist 33 is in the state after development, wherein the region 331 corresponds to the transparent region 311 of the HTM mask 31, the region 332 corresponds to the opaque region 312 of the HTM mask 31, and the region 333 corresponds to the translucent region of the HTM mask 31 313.

As shown in Figure 6, compared with Embodiment 1, the second embodiment is different from the step (S604) of patterning process using HTM and the step (S604) of patterning process using GTM in Embodiment 1. The remaining steps It is exactly the same as Example 1.

include:

S601, forming a buffer layer on the substrate.

S602, forming a polysilicon layer on the buffer layer.

S603 , forming a first metal layer used for source and drain electrodes on the polysilicon active layer.

S604. Using a semi-transparent mask, perform a patterning process on the first metal layer and the polysilicon layer, and obtain patterns of data lines, source electrodes, drain electrodes, and polysilicon semiconductor parts through one patterning process.

As shown in Figure 5E (since it is the same as Figure 5E of Embodiment 1, refer to the relevant drawings of Embodiment 1), a layer of photoresist 55 is coated on the substrate of the above structure, and then photoetched by HTM process The glue 55 is exposed to light. For the TFT region on the HTM mask 80 , the part corresponding to the source and drain regions is an opaque region 802 , and the part corresponding to the gate region is a translucent region 803 .

As shown in Figure 5F (since it is the same as Figure 5F of Embodiment 1, please refer to the relevant drawings of Embodiment 1), it is a schematic diagram of the state of the photoresist 55 after the above exposure, wherein the region 551 of the photoresist 55 Corresponding to the opaque region 802 of the HTM mask 80 , the region 552 of the photoresist 55 corresponds to the translucent region 803 of the HTM mask 80 .

As shown in Figure 5G (since it is the same as Figure 5G of Embodiment 1, refer to the relevant drawings of Embodiment 1), it is a schematic diagram of the state of the photoresist 55 after development, wherein the region 551 of the photoresist 55 is In the region where the photoresist is completely reserved, the region 552 of the photoresist 55 is a region where the photoresist is half-retained, and other regions are where the photoresist is completely removed.

Then, as shown in Figure 5H (since it is the same as Figure 5H of Embodiment 1, just refer to the relevant drawings of Embodiment 1), the source and drain of the region where the photoresist is completely removed is adopted wet etching (Wet Etch) process The electrode metal layer is etched, and then the polysilicon layer is etched using a dry etching (Dry Etch) process to obtain the polysilicon active layer 53 .

Then, as shown in Figure 5I (since it is the same as Figure 5I of Embodiment 1, refer to the relevant drawings of Embodiment 1), after plasma ashing treatment, the photoresist semi-retained region 552 of the photoresist 55 The photoresist is etched away, and the photoresist in the photoresist completely reserved region 551 is left, and the photoresist completely reserved region 551 corresponds to the source and drain regions.

Then, as shown in FIG. 5J (since it is the same as FIG. 5J of Embodiment 1, refer to the relevant drawings of Embodiment 1), the source and drain metal of the photoresist semi-reserved region 552 is then processed by wet etching. layer is etched a second time.

Finally, as shown in Figure 5K (since it is the same as Figure 5K of Embodiment 1, refer to the relevant drawings of Embodiment 1), after peeling off the photoresist in the photoresist completely reserved region 551, the source, drain Pole 54.

So far, in this embodiment, a pattern including the data line, the source electrode, the drain electrode, and the polysilicon active layer is obtained through one HTM patterning process. Compared with the prior art, the first patterning process is used to obtain the polysilicon active layer pattern, and then a patterning process is performed to obtain the connecting part of the source, drain and active layer, and then a patterning process is performed to obtain the source, drain and active layer. As far as the drain electrode is concerned, the process of exposure is reduced, thereby reducing the complexity of the process, shortening the processing time and reducing the processing cost.

S605 , forming a gate insulating layer on the pattern of the source, the drain and the polysilicon semiconductor part, and then performing channel region doping treatment, so as to form a channel region with the source and the drain.

S606 , forming a gate line and a gate on the gate insulating layer.

S607, forming a protective layer (PVX) on the gate.

S608, forming connection via holes on the gate insulating layer and the protection layer.

S609, forming an ITO pixel electrode on the connection via hole.

S610, forming a planarization layer on the pixel electrode.

In the manufacturing method of the low-temperature polysilicon TFT array substrate provided by the embodiment of the present invention, after forming a buffer layer on the substrate, coating the polysilicon layer and the metal layer, the metal layer and the polysilicon layer are patterned by HTM, and the components including Patterns of data lines, source electrodes, drain electrodes, and polysilicon semiconductor parts. Compared with the prior art, a patterning process is first performed to obtain the polysilicon active layer pattern, and then a patterning process is performed to obtain the connection part between the source and drain electrodes and the active layer, and then a patterning process is performed to obtain the source and drain. The process of exposure is reduced, and a layer of protective layer is reduced, thereby reducing the complexity of the process, saving materials, and reducing the processing cost while shortening the processing time.

Embodiment three

The low-temperature polysilicon TFT array substrate provided by the embodiment of the present invention, as shown in FIG. 5Q, includes:

Substrate 51;

A buffer layer 52 is formed on the substrate 51;

A polysilicon semiconductor active layer 53 is formed on the buffer layer 52;

A source 541 and a drain 542 are formed on the polysilicon semiconductor active layer 53; the source 541, the drain 542 and the polysilicon semiconductor active layer 53 form a TFT region;

A gate insulating layer 56 is formed on the source 541 and the drain 542;

A gate 57 and a gate line (not shown in the figure) are formed on the gate insulating layer 56;

A protective layer 58 is formed on the gate 57 and the gate line;

A pixel electrode layer 59 is formed on the protective layer 58, and the pixel electrode layer 59 is connected to the drain electrode 542 through a via hole 59' located on the protective layer 58 and the gate insulating layer 56.

For the low-temperature polysilicon TFT array substrate provided by the embodiment of the present invention, after forming a buffer layer on the substrate, coating the polysilicon layer and the metal layer, the metal layer and the polysilicon layer are patterned by HTM or GTM, and the data including the Patterns of lines, sources, drains, polysilicon semiconductor parts. Compared with the prior art, a patterning process is first performed to obtain the polysilicon active layer pattern, and then a patterning process is performed to obtain the connection part between the source and drain electrodes and the active layer, and then a patterning process is performed to obtain the source and drain. The process of exposure is reduced, and a layer of protective layer is reduced, thereby reducing the complexity of the process, saving materials, and reducing the processing cost while shortening the processing time.

Embodiment Four

The method for manufacturing a low-temperature polysilicon TFT array substrate provided by an embodiment of the present invention, as shown in FIG. 7 , includes:

S701, forming a buffer layer on the substrate.

S702, forming a polysilicon layer on the buffer layer.

S703 , performing low-concentration doping on the polysilicon layer.

After the polysilicon layer is formed, the polysilicon layer is doped at a low concentration, and the doping type is opposite to the doping type of the channel region to be performed, so as to form a reverse PN between the source, drain and channel after the channel doping process. Junction, which can reduce the contact resistance between the polysilicon layer and the source and drain at the source and drain.

S704, forming a first metal layer used for source and drain electrodes on the polysilicon active layer.

S705. Using a gray mask or a semi-transparent mask, perform a patterning process on the first metal layer and the polysilicon layer, and obtain patterns of data lines, source electrodes, drain electrodes, and polysilicon semiconductor parts through one patterning process.

In this embodiment, except for the above steps, the other steps are exactly the same as those in Embodiment 1 or Embodiment 2. For details, please refer to Embodiment 1 or Embodiment 2.

For the low-temperature polysilicon TFT array substrate provided by the embodiment of the present invention, after forming a buffer layer on the substrate, coating the polysilicon layer and the metal layer, the metal layer and the polysilicon layer are patterned by HTM or GTM, and the data including the Patterns of lines, sources, drains, polysilicon semiconductor parts. Compared with the prior art, a patterning process is first performed to obtain the polysilicon active layer pattern, and then a patterning process is performed to obtain the connection part between the source and drain electrodes and the active layer, and then a patterning process is performed to obtain the source and drain. The process of exposure is reduced, and a layer of protective layer is reduced, thereby reducing the complexity of the process, saving materials, and reducing the processing cost while shortening the processing time.

The above is only a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Anyone skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present invention. All should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be determined by the protection scope of the claims.

Claims (5)

1. a low temperature polycrystalline silicon tft array substrate is characterized in that, comprising:

Substrate;

Be formed with the polysilicon semiconductor active layer;

Be formed with source electrode, drain electrode on the said polysilicon semiconductor active layer; Said source electrode, drain electrode and said polysilicon semiconductor active layer constitute the TFT zone;

Be formed with gate insulation layer in said source electrode, the drain electrode;

Be formed with grid, grid line on the said gate insulation layer;

Be formed with protective layer on said grid, the grid line;

Be formed with pixel electrode layer on the said protective layer, said pixel electrode layer is connected with said drain electrode through the via hole that is positioned on said protective layer, the gate insulation layer.

2. low temperature polycrystalline silicon tft array substrate according to claim 4 is characterized in that, also comprises:

Before being formed with the polysilicon semiconductor active layer, on said substrate, be formed with resilient coating.

3. the manufacturing approach of a low temperature polycrystalline silicon tft array substrate is characterized in that, comprising:

On substrate, form polysilicon layer;

On said polysilicon layer, form the first metal layer; Utilize gray tone mask plate or half-penetration type mask plate that said the first metal layer, polysilicon layer are carried out the composition PROCESS FOR TREATMENT, through the first time composition technology obtain the pattern of data wire, source electrode, drain electrode and polysilicon semiconductor part;

Through the second time composition technology on said gate insulation layer, form grid line, grid;

On the pattern of said source electrode, drain electrode and polysilicon semiconductor part, form gate insulation layer;

The source of said polysilicon layer, the part between the drain electrode are carried out doping treatment, so that form channel region with said source, drain electrode;

On said grid line, grid, form protective layer, form via hole in said drain electrode place, expose said drain electrode through composition technology for the third time;

On said protective layer, form pixel electrode layer, said pixel electrode layer is connected with said drain electrode through said via hole;

Form the pixel electrode figure through the 4th composition technology;

On pixel electrode, form the planarization layer figure through the 5th composition technology.

4. the manufacturing approach of low temperature polycrystalline silicon tft array substrate according to claim 3; It is characterized in that; Said gray tone mask plate or the half-penetration type mask plate of utilizing carries out the composition PROCESS FOR TREATMENT to said the first metal layer; Obtain data wire, source electrode, drain electrode and polysilicon semiconductor pattern partly through a composition technology, comprising:

On said the first metal layer, be coated with photoresist;

Utilize gray tone mask plate or half-penetration type mask plate that said photoresist is made public, the back of developing forms the complete reserve area of photoresist, photoresist half reserve area and photoresist and removes the zone fully; Wherein, the complete reserve area respective data lines of said photoresist zone, source region, drain region, the zone between the corresponding source of said photoresist half reserve area, the drain region;

Utilize etching technics to get rid of the first metal layer, polysilicon layer that said photoresist is removed the zone fully;

Utilize plasma ashing technology to get rid of the photoresist of said photoresist half reserve area;

Utilize etching technics to get rid of the first metal layer of said photoresist half reserve area;

Peel off the photoresist of the complete reserve area of said photoresist.

5. the manufacturing approach of low temperature polycrystalline silicon tft array substrate according to claim 3 is characterized in that, saidly comprises forming polysilicon layer on the substrate: on substrate, form resilient coating, on said resilient coating, form polysilicon layer.

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