CN102683412B - Preparation method of double-layer isolation mixed crystal orientation strain nanowire metal oxide semiconductor field effect transistor (MOSFET) - Google Patents
Preparation method of double-layer isolation mixed crystal orientation strain nanowire metal oxide semiconductor field effect transistor (MOSFET) Download PDFInfo
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Abstract
The invention provides a double-layer isolation mixed crystal orientation strain nanowire metal oxide semiconductor field effect transistor (MOSFET) which comprises a first MOSFET, an isolation medium layer and a second MOSFET which are sequentially formed on a semiconductor lining. A first source electrode liner, a first drain electrode liner, a second source electrode liner and a second drain electrode liner of the first MOSFET and the second MOSFET are germanium silicon layers. A germanium silicon layer grows on a first source electrode area and a first drain electrode area, and a carbon silicon layer grows on a second source electrode area and a second drain electrode area. A wet method is utilized to etch the SiGe layers, so that the manufacture process of a cavity layer under a silicon nanowire area can be well controlled. The MOSFET increases mobility ratio of carriers and electrons of an N-type metal oxide semiconductor field effect transistor (NMOSFET) and mobility ratio of carrier cavities of a power metal oxide semiconductor field effect transistor (PMOSFET) and increases current drive capability of a complementary metal oxide semiconductor (CMOS). The first MOSFET and the second MOSFET can be independently used for conducting process debugging.
Description
Technical field
The present invention relates to semiconductor field effect transistor technical field, particularly relate to the preparation method of a kind of bilayer isolation mixed crystal orientation strain nanowire MOS FET.
Background technology
The operating rate of chip is improved and integrated level, reduction chip power-consumption density are that microelectronics industry develops the target pursued always by the size reducing transistor.In in the past 40 years, microelectronics industry development follows Moore's Law always.Current, the physical gate of field-effect transistor is long close to 20nm, gate medium also only has several oxygen atom thickness, improve performance by the size reducing conventional field effect transistor and faced some difficulties, this is mainly because short-channel effect and grid leakage current make the switch performance of transistor degenerate under small size.
Nano-wire field effect transistor (NWFET, Nanowire MOSFET) is expected to address this problem.On the one hand, little channel thickness and width make the various piece of grid closer to raceway groove of NWFET, contribute to the enhancing of transistor gate modulation capability, and their most employings enclose grid structure, grid is modulated from multiple directions raceway groove, can enhanced modulation ability further, improve Sub-Threshold Characteristic.Therefore, NWFET can suppress short-channel effect well, and transistor size is reduced further.On the other hand, NWFET utilize self rill road and enclose grid structure improve grid modulation power and suppress short-channel effect, alleviate the requirement of thinning grid medium thickness, be expected to reduce grid leakage current.In addition, nanowire channel can undope, and decreases the discrete distribution of impurity in raceway groove and Coulomb scattering.For 1-dimention nano wire channel, due to quantum limitation effect, raceway groove carriers away from surface distributed, therefore carrier transport by surface scattering and channel laterally electric field influence little, higher mobility can be obtained.Based on above advantage, NWFET more and more receives the concern of scientific research personnel.Because Si materials and process occupies dominant position in the semiconductor industry, compared with other materials, the making of silicon nanowires field-effect transistor (SiNWFET) is easier and current process is compatible.
The critical process of NWFET is the making of nano wire, can be divided into from top to bottom and two kinds of process routes from bottom to top.For the making of Si nano wire, the former mainly utilizes photoetching (optical lithography or electron beam lithography) and etching (ICP, RIE etching or wet etching) technique, the latter mainly based on gas-liquid-solid (VLS) growth mechanism of metal catalytic, using catalyst granules as nucleating point in growth course.At present, silicon nanowires prepared by process route from bottom to top is not too applicable to the preparation of SiNWFET due to its randomness, the SiNW in therefore current silicon nanowires field-effect transistor is mainly prepared by top-down process route.Meanwhile, existing nano-wire field effect transistor also has the defect of himself.
US Patent No. 20112011/0254058 A1, US20112011/0254099 A1, US20112011/0254101A1, US20110254013A1 etc. disclose the structural representation of mixed CMOS field-effect transistor.But NMOS and PMOS of these patents shares same grid layer, the CMOS structure of clamping type can only be realized, NMOS and PMOS isolating construction cannot be realized, and there is in actual cmos circuit a large amount of NMOS and PMOS isolating construction; Gate work-function cannot be carried out respectively for NMOS and PMOS to regulate and the adjustment of resistance rate; Technique is difficult to realize carrying out source and drain ion implantation respectively for NMOS and PMOS.
For above-mentioned situation, relevant technologies personnel propose a kind of nano-wire field effect transistor of Dual-layer structure, but can not solve the problem completely.
Low-temperature bonding technology basic procedure comprises the cleaning of silicon chip routine, chemistry or plasma-activated process, hydrophilic treated, room temperature laminating and process annealing (≤500C).Most crucial problem is that after reducing annealing temperature, can bond strength be guaranteed.Always there is oxide layer in silicon chip surface, some is in silica covalent bond in the silicon dioxide molecules on surface and can ruptures, and makes silicon atom form dangling bonds.The silicon atom hung shows electropositive, can regard silicon face one deck charge layer as.Through hydrophilic treated, silicon face absorption OH-group forms silanol key.The silicon chip that two panels forms silanol key near time, silanol key, hydrogen bond can be formed between hydrone and silanol key attract each other.The laminating period of Here it is bonding.What silicon chip interface existed is (Si-OH) and hydrone.When temperature raises, silanol key transforms to silicon oxygen bond.This reaction is reversible reaction, and temperature is higher, and the Direction of Reaction more carries out to the right.Here it is, and why high annealing can strengthen bond strength.Process annealing requires at a lower temperature exactly, and reaction can be carried out to the right more fully.This just has following two requirements: (1) silicon chip surface multiform of will trying one's best becomes silanol key, makes silicon chip combine when fitting closely and have enough reactants; (2) the process annealing time will be grown, and is beneficial to hydrone and escapes and diffusion, reaction is constantly carried out to positive direction.For above second point, extend annealing time.And the first point, require that silicon chip has as far as possible many dangling bonds before hydrophilic treated, to adsorb a large amount of (OH) groups.For oxygen plasma Activiation method, it can have following reaction on oxide layer surface:
Si-O+O
+→(Si)
++O
2，
Thus reaching the object forming a large amount of silicon dangling bonds, this is the main cause that process annealing can strengthen bonded interface intensity.
Summary of the invention
In view of above-mentioned the problems of the prior art, technical problem to be solved by this invention is that existing technology lacks double-deck isolation mixed crystal orientation strain nanowire MOS FET safely and effectively.
Bilayer isolation mixed crystal orientation strain nanowire MOS FET provided by the invention, comprise the MOSFET formed successively on a semiconductor substrate, spacer medium layer and the 2nd MOSFET, a described MOSFET comprises the first source area, first drain region, be separately positioned on the first source pad and the first drain pad that the first source area is connected with under the first drain region and with the first source area and the first drain region, first grid polar region, laterally through described first grid polar region and the first semiconductor nanowires be arranged between described first source area and described first drain region and Huan Bao to be arranged on outside described first semiconductor nanowires and first grid oxide layer between the first semiconductor nanowires and first grid polar region, described 2nd MOSFET comprises the second source area, second drain region, be separately positioned on the second source pad and the second drain pad that the second source area is connected with under the second drain region and with the second source area and the second drain region, second gate polar region, laterally through described second gate polar region and the second semiconductor nanowires be arranged between described second source area and described second drain region and Huan Bao to be arranged on outside described second semiconductor nanowires and second gate oxide layer between described second semiconductor nanowires and described second gate polar region, described first source pad and the first drain pad, second source pad and the second drain pad are germanium silicon layer, described first source area and the first drain region growth germanium silicon layer, described second source area and the second drain region growth carbon silicon layer.
In a better embodiment of the present invention, also comprise oxygen buried layer, the first insulating medium layer and the second insulating medium layer, described oxygen buried layer is arranged between a described MOSFET and described Semiconductor substrate; Described first insulating medium layer be arranged on a described MOSFET the first source area, between the first drain region and first grid polar region; Described second insulating medium layer be arranged on described 2nd MOSFET the second source area, between the second drain region and second gate polar region.
In another better embodiment of the present invention, also comprise the 3rd insulating medium layer and the 4th insulating medium layer, described 3rd insulating medium layer is arranged on and is positioned at a described MOSFET side between described spacer medium layer with between described oxygen buried layer and is connected with described first source area, the first drain region and first grid polar region; Described 4th insulating medium layer and described 3rd insulating medium layer are towards arranging and being connected with described second source area, the second drain region and second gate polar region.
In another better embodiment of the present invention, also comprise the first conductive layer and the second conductive layer, described first conductive layer is arranged on described spacer medium layer and described first source area, between the first drain region and first grid polar region; Described second conductive layer be arranged on the second source area, the second drain region and second gate polar region differ from described spacer medium layer side.
In another better embodiment of the present invention, electrode is drawn from the first conductive layer by the 4th insulating medium layer by a described MOSFET, forms the first source electrode, the first drain electrode and first grid respectively.
In another better embodiment of the present invention, electrode is drawn by the second conductive layer be positioned on the second source area, the second drain region and second gate polar region by described 2nd MOSFET, forms the second source electrode, the second drain electrode and second grid respectively.
In another better embodiment of the present invention, a described MOSFET is PMOSFET, and is formed by following steps:
Step 1, forms oxygen buried layer, germanium silicon layer, silicon layer on a silicon substrate successively; And define silicon nanowires field-effect transistor region in a layer of silicon;
Step 2, etching removes the germanium silicon layer under the silicon nanowires region of described transistor area, in germanium silicon layer, form empty layer;
Step 3, silicon nanowires prepares silicon nanowires in region;
Step 4, deposits the first insulating medium layer and prepares first grid polar region in the area of grid etching deposition of described transistor area;
Step 5, etches the first source region of described transistor area and the first drain region until expose germanium silicon layer, and selective epitaxial growth germanium silicon layer;
Step 6, carries out autoregistration metal semiconductor alloy technique.
In another better embodiment of the present invention, described 2nd MOSFET adopts upper strata silicon layer and a MOSFET to be formed by low-temperature bonding technique.
In another better embodiment of the present invention, described 2nd MOSFET is NMOSFET, and is formed by the source drain region selective epitaxial growth carbon silicon layer in the silicon nanowires field-effect transistor region defined.
In another better embodiment of the present invention, described first semiconductor nanowires and described second semiconductor nanowires spatially stacked, and there is the cross section structure of circle, horizontal track type or longitudinal racetrack.
In another better embodiment of the present invention, described spacer medium layer is silicon dioxide layer or the low K silicon dioxide layer of the carbon containing with microcellular structure.
Of the present invention owing to adopting wet etching SiGe layer, the empty layer manufacture craft below silicon nanowires region can be controlled well.
Invention increases the current driving ability of CMOS, and make silicon nanowires channel region have the germanium silicon layer of compression as source-drain area owing to adopting in PMOSFET, increase the mobility of PMOSFET carrier hole; Make silicon nanowires channel region have the carbon silicon layer of tensile stress as source-drain area owing to adopting in NMOSFET, increase the mobility of NMOSFET carrier electrons, thus increase the current driving ability of CMOS.
The present invention adheres to the two-layer MOSFET layer of being isolated by spacer medium layer separately due to PMOSFET and NMOSFET, completely independently can carry out process debugging.
Accompanying drawing explanation
Fig. 1 (a) is the plan structure schematic diagram of the present invention's bilayer isolation crystallographic orientation semiconductor nanowire MOS FET;
Fig. 1 (b) is depicted as the sectional structure schematic diagram of Fig. 1 (a) along X-X ' direction;
Fig. 1 (c) is depicted as the sectional structure schematic diagram of Fig. 1 (a) along Y-Y ' direction;
Fig. 2 is the perspective view of the double-deck semiconductor nanowires MOSFET of the present invention;
The perspective view of the complete field-effect transistor that Fig. 3 is formed through Subsequent semiconductor preparation technology for the double-deck semiconductor nanowires MOSFET of the present invention;
Fig. 4 is the structural representation of the formation top layer silicon of embodiments of the invention;
Fig. 5 is the structural representation of the formation cavity layer of embodiments of the invention;
Fig. 6 is the structural representation of the formation gate regions of embodiments of the invention;
Fig. 7 is the structural representation of the formation source-drain electrode area of embodiments of the invention.
Embodiment
Below with reference to accompanying drawing, concrete explaination is done to the present invention.
Refer to Fig. 1 (a), Fig. 1 (b), Fig. 1 (c), and composition graphs 2, Fig. 1 (a) is depicted as the plan structure schematic diagram of the present invention's double-deck isolation of semiconductor nanowire MOS FET.Fig. 1 (b) is depicted as the sectional structure schematic diagram of Fig. 1 (a) along X-X ' direction.Fig. 1 (c) is depicted as the sectional structure schematic diagram of Fig. 1 (a) along Y-Y ' direction.Described bilayer isolation crystallographic orientation semiconductor nanowire MOS FET 1 comprises Semiconductor substrate 10, one MOSFET 11,2nd MOSFET 12, be arranged on the spacer medium layer 13 between a described MOSFET 11 and described 2nd MOSFET12, be arranged on the oxygen buried layer 14 between a described MOSFET 11 and described Semiconductor substrate 10, be arranged on first source area 110 of a described MOSFET 11, the first insulating medium layer 113 between first drain region 111 and first grid polar region 112, and be separately positioned on the first source pad 1101 and the first drain pad 1111 that the first source area 110 is connected with 111 times, the first drain region and with the first source area and the first drain region, be arranged on second source area 120 of described 2nd MOSFET 12, the second insulating medium layer 123 between second drain region 121 and second gate polar region 122, and be separately positioned on the second source pad 1201 and the second drain pad 1211 that the second source area 120 is connected with 121 times, the second drain region and with the second source area and the second drain region, to be arranged between described spacer medium layer 13 and described oxygen buried layer 14 and be positioned at described MOSFET 11 side and with described first source area 110, the 3rd insulating medium layer 114 that first drain region 111 and first grid polar region 112 are connected, with described 3rd insulating medium layer 114 in towards arrange and with described second source area 120, the 4th insulating medium layer 124 that second drain region 121 and second gate polar region 122 connect, and be separately positioned on described spacer medium layer 13 and described first source area 110, the first conductive layer 115 between first drain region 111 and first grid polar region 112 and be separately positioned on the second source area 120, second conductive layer 125 differing from described spacer medium layer 13 side of the second drain region 121 and second gate polar region 122.
Refer to Fig. 2, and Fig. 1 (a), Fig. 1 (b) and Fig. 1 (c) are consulted in combination, Figure 2 shows that the perspective view of the present invention's bilayer isolation crystallographic orientation semiconductor nanowire MOS FET 1.A described MOSFET 11 comprises further laterally through described first grid polar region 112 and the first semiconductor nanowires 116 be arranged between described first source area 110 and described first drain region 111, and ring bag to be arranged on outside described first semiconductor nanowires 116 and first grid oxide layer 117 between described first semiconductor nanowires 116 and described first grid polar region 112.
Please continue to refer to Fig. 2, and Fig. 1 (a), 1 (b), Fig. 1 (c) are consulted in combination, 2nd MOSFET 12 of the present invention's bilayer isolation crystallographic orientation semiconductor nanowire MOS FET 1 comprises further laterally through described second gate polar region 122 and the second semiconductor nanowires 126 be arranged between described second source area 120 and described second drain region 121, and ring bag to be arranged on outside described second semiconductor nanowires 126 and second gate oxide layer 127 between described second semiconductor nanowires 126 and described second gate polar region 122.Described first semiconductor nanowires 116 is spatially stacked with described second semiconductor nanowires 126, and has the cross section structure of circle, horizontal track type or longitudinal racetrack.
Wherein, the first source pad and the first drain pad, the second source pad and the second drain pad are germanium silicon layer, the first source area and the first drain region growth germanium silicon layer, the second source area and the second drain region growth carbon silicon layer.
Of the present invention owing to adopting wet etching SiGe layer, the empty layer manufacture craft below silicon nanowires region can be controlled well; In the raceway groove of lower floor PMOSFET, introduce compression along source and drain direction, thus increase the mobility of PMOSFET carrier hole.In the raceway groove of upper strata NMOSFET, introduce tensile stress along source and drain direction, thus increase the mobility of NMOSFET carrier electrons.By the introducing of stress mechanism, effectively increase the current driving ability of CMOS; Upper and lower two-layer semiconductor nanowires MOSFET is kept apart by insulating medium layer, completely independently can carry out process debugging.
Lower floor PMOSFET and upper strata NMOSFET pattern can be adopted in an embodiment of the present invention, realize to facilitate layer transfer process; Adopt the channel material using the silicon nanowires of (100) surface orientation as NMOSFET, and the channel direction of NMOSFET is <110>, using the silicon nanowires of (110) surface orientation as the channel material of PMOSFET, and the channel direction of PMOSFET is <110>, this crystallographic orientation method can effectively increase NMOSFET and PMOSFET current driving ability.
Please continue to refer to Fig. 2, the width perpendicular to described first semiconductor nanowires 116 of described first drain region 111, source area 110, first is greater than the diameter of the first semiconductor nanowires 116, the width perpendicular to the second semiconductor nanowires 126 of described second drain region 121, source area 120, second is greater than the diameter of the second semiconductor nanowires 126, so in the fin-shaped that middle thin two ends are roomy when the present invention's double-deck isolation of semiconductor nanowire MOS FET 1 overlooks.
First insulating medium layer 113 is set between the first drain region 111, source area 110, first and first grid polar region 112 to avoid the mutual interference between the first drain region 111, source area 110, first and first grid polar region 112.Second insulating medium layer 123 is set between the second drain region 121, source area 120, second and second gate polar region 122 to avoid the mutual interference between the second drain region 121, source area 120, second and second gate polar region 122.Oxygen buried layer 14 is set between the first semiconductor nanowires MOSFET 11 and Semiconductor substrate 10, described first semiconductor nanowires MOSFET 11 is isolated with described Semiconductor substrate 10, effectively reduces leakage current, thus improve device performance.
Refer to Fig. 2, and Fig. 3 is consulted in combination, Figure 3 shows that the perspective view of the complete field-effect transistor formed through Subsequent semiconductor preparation technology.Electrode can be drawn from the first conductive layer 115 by the 4th insulating medium layer 124 by described first semiconductor nanowires MOSFET 11, to form the first source electrode 118a, the first drain electrode 118b and first grid 119 respectively.Electrode can be drawn by the second conductive layer 125 be positioned on the second drain region 121, source area 120, second and second gate polar region 122 by described second semiconductor nanowires MOSFET 12, to form the second source electrode 128a, the second drain electrode 128b and second grid 129 respectively.Refer to Fig. 4, Fig. 5, Fig. 6, Fig. 7, a MOSFET of the present invention can be formed by following steps:
Step 1, as shown in Figure 4, silicon substrate 10 forms oxygen buried layer 14, the germanium silicon layer 15 of surface orientation 110, the silicon layer 16 of surface orientation 110 successively; And in silicon layer 16, define silicon nanowires field-effect transistor region;
In an embodiment of the present invention, by first forming the silicon layer of top layer silicon for (110) surface orientation on soi wafer.Preferably, oxygen buried layer thickness is 10 ~ 1000nm, and top silicon layer thickness is 10 ~ 500nm; After at SiGe or the Ge layer of top layer silicon surface extension one deck (110) surface orientation.Preferably, epitaxially grown SiGe or Ge layer thickness is 10 ~ 500nm; Recycling germanium oxidation concentration method, carry out oxidation processes on Wafer surface, at this moment, Ge can be concentrated to Si layer below downwards, makes Si layer become SiGe layer, and is SiO above
2layer; Wet method removes the SiO on surface
2layer, so just makes top silicon layer be converted into top layer (110) germanium silicon layer, and preferably, top layer (110) the germanium silicon layer thickness transforming gained is 10 ~ 500nm; Finally epitaxial growth again (110) silicon layer on top layer (110) germanium silicon layer, preferably, epitaxially grown (110) silicon layer thickness is 10 ~ 500nm, by ion implantation or carry out in-situ doped, as the channel doping ion of follow-up NWFET in epitaxially grown (110) silicon layer.When preparing inversion mode PMOSFET, then channel dopant ion is donor impurity, and when preparing accumulation pattern PMOSFET, then channel dopant ion is acceptor impurity.
Step 2, as shown in Figure 5, utilizes selective etch technology (such as to adopt the H of 600 ~ 800 DEG C
2with HCl mist, utilize time atmospheric chemical vapor etching method to carry out selective etch, wherein the dividing potential drop of HCl is greater than 300Torr) remove germanium silicon layer 15 under the silicon nanowires region of described transistor area, in germanium silicon layer, form empty layer; Left region is the first source pad 1101 and the first drain pad 1111.
Step 3, prepares silicon nanowires in silicon nanowires region; Wherein can pass through the oxide layer that thermal oxidation technology+wet method removes silicon surface, prepare silicon nanowires.
Step 4, as shown in Figure 6, deposits the first insulating medium layer 113 and prepares first grid polar region 112 in the area of grid etching deposition of described transistor area.
Wherein, the first insulating medium layer is deposited (as SiO
2layer) the empty layer below silicon layer 16 is filled completely, by cmp (CMP), the first insulating medium layer is polished, make the thickness of dielectric layers above the source and drain liner of NWFET be 20 ~ 200nm; Etch away the dielectric of area of grid again, expose SiNW, and till etching into oxygen buried layer always; Carry out grid oxygen technique subsequently, SiO2 or SiON or Si can be prepared by thermal oxidation or depositing operation
3n
4or the first grid oxygen layer of the hafnium prepared by depositing operation or its combination, wherein, hafnium can be HfO2, ZrO2, La2O3, Al2O3, TiO2, SrTiO3, LaAlO3, Y2O3, HfOxNy, ZrOxNy, La2OxNy, Al2OxNy, TiOxNy, the one of SrTiOxNy, LaAlOxNy, Y2OxNy or combination; Last deposition of gate material can be polysilicon, amorphous silicon, metal or its combination; CMP removes unnecessary grid material.
Because this its preparation process makes had dielectric to isolate between source-drain area and grid, and ultimate source drain region and top, gate regions are same planes, therefore do not need grid curb wall technique, simplify technological process.
Step 5, as shown in Figure 7, adopt photo-resistive mask or hard mask lithography and etch the first source region of described transistor area and the first drain region until expose germanium silicon layer, the germanium silicon layer retained can as the inculating crystal layer of subsequent epitaxial SiGe.
In the source drain region selective epitaxial growth etched (SEG, Selective EpitaxialGrowth) SiGe layer, wherein the chemical mol ratio of Ge is 1% ~ 100%, preferably, is 10% ~ 50%.Simultaneously, carry out source and drain in-situ doped, preferably, doping B, BF, BF2 ion (if grid material adopts polysilicon or amorphous silicon, then must adopt hard mask in this step and retain hard mask to avoid in area of grid generation epitaxial growth, if grid material adopts metal, then mask can be removed before this step).
Step 6, carries out autoregistration metal semiconductor alloy technique.
So, prepared by lower floor (110) surface orientation strained silicon nano wire PMOSFET, because source and drain areas adopts e-SiGe, they have action of compressive stress to channel region along channel direction, effectively can increase hole mobility, and then increase PMOSFET current driving ability.
Subsequently, upper strata (100) silicon layer can be prepared by adopting upper strata silicon layer and a MOSFET by low-temperature bonding technique, preparation upper strata strained silicon nano wire NMOSFET.Technological process and lower floor PMOSFET prepare substantially identical, do not repeat here.Wherein, at the source and drain cushion region selective epitaxial growth etched (SEG, Selective Epitaxial Growth) SiC, wherein the chemical mol ratio of C is 0.01% ~ 10%, preferably, is 0.1% ~ 5%.Meanwhile, it is in-situ doped to carry out source and drain, preferably, and doping P, As ion.
It is noted that for the heat treatment of source and drain impurity, due to the requirement to underlying components temperature control, preferably, adopt laser tempering (Laser Anneal) method, layer device local Anneal can be realized, and the performance of underlying components can not be had influence on.
In the preparation to upper strata (100) surface orientation strained silicon nano wire NMOSFET, because source and drain areas adopts e-SiC, they have tensile stress effect to channel region along channel direction, effectively can increase electron mobility, and then increase NMOSFET current driving ability.
Be described in detail specific embodiments of the invention above, but it is just as example, the present invention is not restricted to specific embodiment described above.To those skilled in the art, any equivalent modifications that the present invention is carried out and substituting also all among category of the present invention.Therefore, equalization conversion done without departing from the spirit and scope of the invention and amendment, all should contain within the scope of the invention.
Claims (8)
1. prepare the method for double-deck isolation mixed crystal orientation strain nanowire MOS FET for one kind, comprise the MOSFET formed successively on a semiconductor substrate, spacer medium layer and the 2nd MOSFET, a described MOSFET comprises the first source area, first drain region, be separately positioned on the first source pad and the first drain pad that the first source area is connected with under the first drain region and with the first source area and the first drain region, first grid polar region, laterally through described first grid polar region and the first semiconductor nanowires be arranged between described first source area and described first drain region and Huan Bao to be arranged on outside described first semiconductor nanowires and first grid oxide layer between the first semiconductor nanowires and first grid polar region, described 2nd MOSFET comprises the second source area, second drain region, be separately positioned on the second source pad and the second drain pad that the second source area is connected with under the second drain region and with the second source area and the second drain region, second gate polar region, laterally through described second gate polar region and the second semiconductor nanowires be arranged between described second source area and described second drain region and Huan Bao to be arranged on outside described second semiconductor nanowires and second gate oxide layer between described second semiconductor nanowires and described second gate polar region, it is characterized in that, described first source pad and the first drain pad, second source pad and the second drain pad are germanium silicon layer, described first source area and the first drain region growth germanium silicon layer, described second source area and the second drain region growth carbon silicon layer,
Wherein, a described MOSFET is PMOSFET, and is formed by following steps:
Step 1, forms oxygen buried layer, germanium silicon layer, silicon layer on a silicon substrate successively; And define silicon nanowires field-effect transistor region in a layer of silicon;
Step 2, etching removes the germanium silicon layer under the silicon nanowires region of described transistor area, in germanium silicon layer, form empty layer;
Step 3, prepares silicon nanowires in silicon nanowires region;
Step 4, deposits the first insulating medium layer and prepares first grid polar region in the area of grid etching deposition of described transistor area;
Step 5, etches the first source region of described transistor area and the first drain region until expose germanium silicon layer, and selective epitaxial growth germanium silicon layer;
Step 6, carries out autoregistration metal semiconductor alloy technique;
Described 2nd MOSFET is NMOSFET, described 2nd MOSFET adopts upper strata silicon layer and a MOSFET to be formed by low-temperature bonding technique, and is formed by the source drain region selective epitaxial growth carbon silicon layer in the silicon nanowires field-effect transistor region defined.
2. prepare the method for nanowire MOS FET as claimed in claim 1, it is characterized in that, also comprise oxygen buried layer, the first insulating medium layer and the second insulating medium layer, described oxygen buried layer is arranged between a described MOSFET and described Semiconductor substrate; Described first insulating medium layer be arranged on a described MOSFET the first source area, between the first drain region and first grid polar region; Described second insulating medium layer be arranged on described 2nd MOSFET the second source area, between the second drain region and second gate polar region.
3. prepare the method for nanowire MOS FET as claimed in claim 2, it is characterized in that, also comprise the 3rd insulating medium layer and the 4th insulating medium layer, described 3rd insulating medium layer is arranged on and is positioned at a described MOSFET side between described spacer medium layer with between described oxygen buried layer and is connected with described first source area, the first drain region and first grid polar region; Described 4th insulating medium layer and described 3rd insulating medium layer are towards arranging and being connected with described second source area, the second drain region and second gate polar region.
4. prepare the method for nanowire MOS FET as claimed in claim 3, it is characterized in that, also comprise the first conductive layer and the second conductive layer, described first conductive layer is arranged on described spacer medium layer and described first source area, between the first drain region and first grid polar region; Described second conductive layer be arranged on the second source area, the second drain region and second gate polar region differ from described spacer medium layer side.
5. prepare the method for nanowire MOS FET as claimed in claim 4, it is characterized in that, electrode is drawn from the first conductive layer by the 4th insulating medium layer by a described MOSFET, forms the first source electrode, the first drain electrode and first grid respectively.
6. prepare the method for nanowire MOS FET as claimed in claim 4, it is characterized in that, electrode is drawn by the second conductive layer be positioned on the second source area, the second drain region and second gate polar region by described 2nd MOSFET, forms the second source electrode, the second drain electrode and second grid respectively.
7. prepare the method for nanowire MOS FET as claimed in claim 1, it is characterized in that, described first semiconductor nanowires and described second semiconductor nanowires spatially stacked, and there is the cross section structure of circle, horizontal track type or longitudinal racetrack.
8. prepare the method for nanowire MOS FET as claimed in claim 1, it is characterized in that, described spacer medium layer is silicon dioxide layer or the low K silicon dioxide layer of the carbon containing with microcellular structure.
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