CN102707227A - Threshold voltage extracting method of FET - Google Patents

Abstract

The invention relates to a threshold voltage extracting method of an FET (field effect transistor), which is especially suitable for a nanometer FinFET. The threshold voltage extracting method comprises the following steps: selecting different drain-source voltages Vds at three points, scanning grid-source voltage Vgs from -0.5V to +1.5V, testing a transfer current characteristic curve Ids-Vgs of the FET, and determining a device to regularly work; selecting different Vgs at three points, scanning the Vds from 0V to +1.5V, and testing an output current characteristic curve Ids-Vds of the FET; carrying out derivation on the Vds by drain-source output current Ids to obtain an output electric conductivity characteristics curve Gout-Vds, and selecting two points in a linear region to obtain the intercept and gradient of a corresponding straight line; and extracting threshold voltage Vth of the FET. The threshold voltage extracting method disclosed by the invention is realized simply, is not sensitive to offset fluctuation under low Vds and can suppress a short-channel effect and an ultrathin body effect caused by small devices.

Description

A kind of field-effect transistor threshold voltage method for distilling

Technical field

The present invention relates to technical field of integrated circuits, be specifically related to a kind of field-effect transistor threshold voltage method for distilling, especially a kind of nanofin formula field-effect transistor (FinFET) field-effect transistor threshold voltage method for distilling.

Background technology

Along with integrated circuit technique develops nanoscale rapidly, the FinFET field effect transistor becomes one of candidate structure that has hope with the structure of its optimization and powerful grid-control ability.And, require the circuit design precision high along with the integration density and the complexity of integrated circuit are increasingly high, and the cycle is short, and cost is low, and design error is few as far as possible.Threshold voltage vt h successfully has decisive significance as the key parameter of semiconductor devices to the design that guarantees integrate circuit function.Threshold voltage had a lot of definition and method for distilling; But because FinFET tagma and extremely short channel length as thin as a wafer; Make threshold voltage receive the influence of short channel effect and ultra-thin body, it is very responsive to the fluctuation of bias voltage to cause extracting the result, and result's accuracy is extracted in influence.

Summary of the invention

The technical issues that need to address of the present invention are, how a kind of field-effect transistor threshold voltage method for distilling is provided, and can reduce or get rid of the influence of bias condition and small-size effect greatly.

Technical matters of the present invention solves like this: make up a kind of field-effect transistor threshold voltage method for distilling, may further comprise the steps:

101) select 3 different drain source voltage Vds, with gate source voltage Vgs from-0.5 volt scan+1.5 volts, test out the transfer current family curve Ids-Vgs of FinFET field effect transistor, confirm the device operate as normal;

102) select 3 different gate source voltage Vgs, with Vds from 0 volt scan+1.5 volts, test out the output current characteristic curve Ids-Vds of FinFET field effect transistor; To leak-source output current Ids is to the Vds differentiate, obtains output conductance family curve Gout-Vds; When Vds hour, Gout and Vds are linear; Utilize linear fit, in linear zone, obtain the intercept A2 and the slope B2 of straight line under intercept A1 and the slope B1 and the Vgs=Vgs2 condition of straight line under the Vgs=Vgs1 condition, wherein: Vgs1 ≠ Vgs2;

103) utilize formula III and formula VI to calculate the threshold voltage vt h of FinFET field effect transistor, the relation curve of

and the Vth-Vds that draws; Wherein:

η _AAnd η _BBe:

The intercept η of the linear zone extrapolation line of output conductance family curve Gout-Vds _ASlope η with the linear zone of output conductance family curve Gout-Vds extrapolation line _B

Formula III is:

${\mathrm{\η}}_A=\frac{{A_1|}_{V_{\mathrm{gs}1}}}{{A_2|}_{V_{\mathrm{gs}2}}}=\frac{1+\mathrm{\θ}(V_{\mathrm{gs}2}-V_{\mathrm{th}})}{1+\mathrm{\θ}(V_{\mathrm{gs}1}-V_{\mathrm{th}})}\·\frac{(V_{\mathrm{gs}1}-V_{\mathrm{th}})}{(V_{\mathrm{gs}2}-V_{\mathrm{th}})};$

Formula VI is:

${\mathrm{\η}}_B=\frac{B_1}{B_2}=\frac{{\mathrm{WC}}_{\mathrm{ox}}{\mathrm{\μ}}_{\mathrm{eff}1}/L}{{\mathrm{WC}}_{\mathrm{ox}}{\mathrm{\μ}}_{\mathrm{eff}2}/L}=\frac{1+\mathrm{\θ}(V_{{\mathrm{gs}}_2}-V_{\mathrm{th}})}{1+\mathrm{\θ}(V_{{\mathrm{gs}}_1}-V_{\mathrm{th}})}.$

According to method for distilling provided by the invention, said 3 different drain source voltage Vds are respectively 0.1V, 0.3V and 0.5V.

According to method for distilling provided by the invention, said 3 different gate source voltage Vgs are respectively 0.5V, 1V and 1.5V.

According to method for distilling provided by the invention, it is nanometer FinFET field effect transistor that said field effect transistor includes, but are not limited to.

Field-effect transistor threshold voltage method for distilling provided by the invention improves on FinFET field effect transistor output current model based, utilizes the extrapolation of output conductance characteristic to extract nanometer FinFET field-effect transistor threshold voltage exactly.This method accuracy is high, and simple to operate, it is little influenced by bias condition and small-size effect, is applicable to the extraction small size device, is particularly useful for the threshold voltage of FinFET field effect transistor.

Description of drawings

Further the present invention is elaborated below in conjunction with accompanying drawing and specific embodiment:

Fig. 1 is a nanometer FinFET field-effect transistor structure synoptic diagram;

Fig. 2 is the transfer current family curve Ids-Vgs under different grid-drain voltage Vds;

Fig. 3 is output current characteristic curve Ids-Vds and the output conductance family curve Gout-Vds under the different gate source voltage Vgs;

The result's that Fig. 4 extracts the FinFET field effect transistor for the output conductance extrapolation method threshold voltage and the threshold voltage method for distilling of having reported obtain comparison.

Embodiment

At first, starting point of the present invention and theoretical foundation are described:

201) obtain the linear zone current expression (formula I) of FinFET field effect transistor according to device physics

$I_{\mathrm{ds}}=\frac{{\mathrm{WC}}_{\mathrm{ox}}{\mathrm{\μ}}_{\mathrm{eff}}}{L}(V_{\mathrm{gs}}-V_{\mathrm{th}}-\frac{V_{\mathrm{ds}}}{2})V_{\mathrm{ds}}=\frac{{\mathrm{WC}}_{\mathrm{ox}}{\mathrm{\μ}}_0}{L[1+\mathrm{\θ}(V_{\mathrm{gs}}-V_{\mathrm{th}})]}(V_{\mathrm{gs}}-V_{\mathrm{th}}-\frac{V_{\mathrm{ds}}}{2})V_{\mathrm{ds}}---\left(I\right)$

Among the said formula I, W, L and Cox represent effective channel width respectively, length of effective channel and gate oxide electric capacity.For the FinFET device, channel width is W=2Hfin+Wfin (Hfin and Wfin are respectively the height and the width of Fin structure here).Vth is a threshold voltage, and Vgs is a gate source voltage, and Vds is a drain source voltage, and μ eff is an effective mobility, and μ 0 is a low mobility, and θ is the effective mobility degeneration factor.

202) basis is to formula I both sides differentiate, and we obtain output conductance (formula II)

$G_{\mathrm{out}}=\frac{{\mathrm{dI}}_{\mathrm{ds}}}{{\mathrm{dV}}_{\mathrm{ds}}}=\frac{{\mathrm{WC}}_{\mathrm{ox}}{\mathrm{\μ}}_{\mathrm{eff}}}{L}[(V_{\mathrm{gs}}-V_{\mathrm{th}})-V_{\mathrm{ds}}]=A-B{V}_{\mathrm{ds}}---\left(\mathrm{II}\right)$

The draw relation curve of output conductance Gout and Vds, intercept and slope are respectively A=WCox μ 0 (Vgs-Vth)/L and B=WCox μ eff/L can directly extract through experimental data curve.

203) measure down the output current curve at different gate source voltage (Vgs1 and Vgs2), obtain the ratio (A and B) of A and B among the formula II, shown in formula III and IV.

${\mathrm{\η}}_A=\frac{{A_1|}_{V_{\mathrm{gs}1}}}{{A_2|}_{V_{\mathrm{gs}2}}}=\frac{1+\mathrm{\θ}(V_{\mathrm{gs}2}-V_{\mathrm{th}})}{1+\mathrm{\θ}(V_{\mathrm{gs}1}-V_{\mathrm{th}})}\·\frac{(V_{\mathrm{gs}1}-V_{\mathrm{th}})}{(V_{\mathrm{gs}2}-V_{\mathrm{th}})}---\left(\mathrm{III}\right)$

${\mathrm{\η}}_B=\frac{B_1}{B_2}=\frac{{\mathrm{WC}}_{\mathrm{ox}}{\mathrm{\μ}}_{\mathrm{eff}1}/L}{{\mathrm{WC}}_{\mathrm{ox}}{\mathrm{\μ}}_{\mathrm{eff}2}/L}=\frac{1+\mathrm{\θ}(V_{{\mathrm{gs}}_2}-V_{\mathrm{th}})}{1+\mathrm{\θ}(V_{{\mathrm{gs}}_1}-V_{\mathrm{th}})}---\left(\mathrm{IV}\right)$

204) with formula IV substitution III, obtain formula V

η _A＝η _B(V _gs1-V _th)/(V _gs2-V _th) (V)

205) reorganize formula V, obtain threshold voltage (Vth) expression formula (formula VI)

$V_{\mathrm{th}}=\frac{V_{\mathrm{gs}1}-({\mathrm{\η}}_A/{\mathrm{\η}}_B)V_{\mathrm{gs}2}}{(1-{\mathrm{\η}}_A/{\mathrm{\η}}_B)}---\left(\mathrm{VI}\right)$

The second, in conjunction with specific embodiment the present invention is described further, be not limited to following examples but the present invention includes:

This specific embodiment uses the output conductance extrapolation method to extract nanometer FinFET field-effect transistor threshold voltage, and its detailed process comprises:

301) prepare nanometer FinFET field effect transistor to be measured, its concrete test structure is as shown in Figure 1, comprises gate voltage 1, underlayer voltage 2, source electrode 3, drain electrode 4, grid 5, oxide layer 6, substrate 7, source voltage 8 and drain voltage 9.

302) as shown in Figure 2, gate source voltage Vgs is scanned+1.5V from-0.5V, drain source voltage Vds is respectively 0.1V, 0.3V, 0.5V.Test out the transfer current family curve Ids-Vgs of FinFET field effect transistor, confirm the device operate as normal.

303) as shown in Figure 3, drain source voltage Vds is scanned+1.5V from 0V, gate source voltage Vgs is respectively 0.5V, 1V, 1.5V.Test out the output current characteristic curve Ids-Vds of FinFET field effect transistor.

Output current (Ids) to drain voltage (Vds) differentiate, is obtained the relation curve of output conductance Gout and drain source voltage Vds, shown in square among Fig. 3.When Vds hour, Gout and Vds are linear.Utilize linear fit, obtain the intercept and the slope of straight line under the different Vgs conditions, be i.e. A and B among the formula II.

204) utilize formula III to calculate the threshold voltage vt h of FinFET field effect transistor to VI, and the relation curve of draw Vth and Vds, as shown in Figure 4.Result through with previous " linear complementary divisor difference equation method " extraction threshold voltage of reporting compares; Can find out under low Vds situation; It is less to utilize extraction result of the present invention influenced by bias condition; With the deviate of average threshold voltage also about zero, be significantly less than the result's that the method for distilling reported obtains error.

The above is merely preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.

Claims (4)

1. a field-effect transistor threshold voltage method for distilling is characterized in that, may further comprise the steps:

101) select 3 different drain source voltage Vds, with gate source voltage Vgs from-0.5 volt scan+1.5 volts, test out the transfer current family curve Ids-Vgs of FinFET field effect transistor, confirm the device operate as normal;

102) select 3 different gate source voltage Vgs, with Vds from 0 volt scan+1.5 volts, test out the output current characteristic curve Ids-Vds of FinFET field effect transistor; To leak-source output current Ids is to the Vds differentiate, obtains output conductance family curve Gout-Vds; When Vds hour, Gout and Vds are linear; Utilize linear fit, in linear zone, obtain the intercept A2 and the slope B2 of straight line under intercept A1 and the slope B1 and the Vgs=Vgs2 condition of straight line under the Vgs=Vgs1 condition, wherein: Vgs1 ≠ Vgs2;

103) utilize formula III and formula VI to calculate the threshold voltage vt h of FinFET field effect transistor, the relation curve of

and the Vth-Vds that draws; Wherein:

η _AAnd η _BBe:

The intercept η of the linear zone extrapolation line of output conductance family curve Gout-Vds _ASlope η with the linear zone of output conductance family curve Gout-Vds extrapolation line _B

Formula III is:

${\mathrm{\η}}_A=\frac{{A_1|}_{V_{\mathrm{gs}1}}}{{A_2|}_{V_{\mathrm{gs}2}}}=\frac{1+\mathrm{\θ}(V_{\mathrm{gs}2}-V_{\mathrm{th}})}{1+\mathrm{\θ}(V_{\mathrm{gs}1}-V_{\mathrm{th}})}\·\frac{(V_{\mathrm{gs}1}-V_{\mathrm{th}})}{(V_{\mathrm{gs}2}-V_{\mathrm{th}})};$

Formula VI is:

${\mathrm{\η}}_B=\frac{B_1}{B_2}=\frac{{\mathrm{WC}}_{\mathrm{ox}}{\mathrm{\μ}}_{\mathrm{eff}1}/L}{{\mathrm{WC}}_{\mathrm{ox}}{\mathrm{\μ}}_{\mathrm{eff}2}/L}=\frac{1+\mathrm{\θ}(V_{{\mathrm{gs}}_2}-V_{\mathrm{th}})}{1+\mathrm{\θ}(V_{{\mathrm{gs}}_1}-V_{\mathrm{th}})}.$

2. according to the said field-effect transistor threshold voltage method for distilling of claim 1, it is characterized in that said 3 different drain source voltage Vds are respectively 0.1V, 0.3V and 0.5V.

3. according to the said field-effect transistor threshold voltage method for distilling of claim 1, it is characterized in that said 3 different gate source voltage Vgs are respectively 0.5V, 1V and 1.5V.

4. according to each said field-effect transistor threshold voltage method for distilling of claim 1-3, it is characterized in that said field effect transistor is a nanometer FinFET field effect transistor.