CN102709302B - Image sensor and manufacturing method of transistor - Google Patents

Abstract

The invention discloses an image sensor and a transistor manufacturing method. The image sensor includes a pixel array, and one or more pixel units of the pixel array include a source follower transistor. The source follower transistor is a junction field effect transistor, including: a substrate of the first conductivity type; a well of the second conductivity type located in the substrate of the first conductivity type; a deposited doped layer of the second conductivity type located in the substrate of the first conductivity type Outside the bottom surface and at least partially on the second conductivity type well; the first conductivity type source region is located in the second conductivity type well; the first conductivity type drain region is located in the first conductivity type substrate and/or the second conductivity type type well; the doped layer of the first conductivity type is at least partially located between the well of the second conductivity type and the deposited doped layer of the second conductivity type, so that the source region of the first conductivity type is electrically connected to the drain region of the first conductivity type , and respectively form PN junctions between it and the second conductivity type well and between it and the second conductivity type deposited doped layer.

Description

Image sensor and transistor manufacturing method

technical field

The present invention relates to the technical field of semiconductors, and more specifically, the present invention relates to an image sensor and a method for manufacturing a transistor.

Background technique

Traditional image sensors can generally be divided into two categories: Charge Coupled Device (CCD) image sensors and complementary metal oxide semiconductor (CMOS) image sensors. Among them, the CMOS image sensor has the advantages of small size, low power consumption, and low production cost. Therefore, the CMOS image sensor is easy to be integrated in portable electronic devices such as mobile phones, notebook computers, and tablet computers, as a camera module that provides digital imaging functions. use.

CMOS image sensors usually use a 3T or 4T pixel structure. FIG. 1 shows a 4T pixel structure of a traditional CMOS image sensor, including a photodiode 11 , a transfer transistor 12 , a reset transistor 13 , a source follower transistor 14 and a row selection transistor 15 . Wherein, the photodiode 11 is used to sense the change of light intensity to form a corresponding image charge signal. The transfer transistor 12 is used to receive the transfer control signal TX. Under the control of the transfer control signal TX, the transfer transistor 12 is turned on or off accordingly, so that the image charge signal induced by the photodiode 11 is read out to the transfer transistor 12. The drain is coupled to a floating diffusion region, and the floating diffusion region stores image charge signals. The reset transistor 13 is used to receive a reset control signal RST, under the control of the reset control signal RST, the reset transistor 13 is turned on or off accordingly, so as to provide a reset signal to the gate of the source follower transistor 14 . The source follower transistor 14 is used to convert the image charge signal obtained by the transfer transistor 12 into a voltage signal, and the voltage signal can be output to the bit line BL through the row selection transistor 15 .

However, the voltage signal output by the traditional CMOS image sensor often has large flicker noise, especially when the light is weak, the flicker noise is more obvious. Flicker noise in voltage signals can significantly degrade image quality.

Contents of the invention

Therefore, there is a need to provide an image sensor with lower flicker noise.

The inventors have found through research that traditional CMOS image sensors often use surface channel transistors as source follower transistors. In this source-follower transistor, the conduction channel is located at the surface of the substrate, close to the gate oxide layer on the substrate. However, the interface between the substrate and the gate oxide layer is prone to form an interface state, which will randomly capture or release carriers, thereby causing changes in the channel current, and then introducing flicker noise into the voltage signal output by the source follower transistor.

In order to solve the above problems, according to one aspect of the present invention, an image sensor is provided. The image sensor includes a pixel array, and one or more pixel units in the pixel array include a source-following transistor, and the source-following transistor is a junction field effect transistor, which includes: a first conductivity type substrate; a second conductivity type The well is located in the substrate of the first conductivity type; the doped layer of the second conductivity type is deposited outside the surface of the substrate of the first conductivity type and at least partially on the well of the second conductivity type; the first conductivity type Type source region, located in the second conductivity type well; first conductivity type drain region, located in the first conductivity type substrate and/or in the second conductivity type well; first conductivity type doping layer at least partially between the well of the second conductivity type and the deposited doped layer of the second conductivity type, so that the source region of the first conductivity type is electrically connected to the drain region of the first conductivity type, and PN junctions are respectively formed between it and the well of the second conductivity type and between it and the deposited doped layer of the second conductivity type.

Compared with the image sensor in the prior art, since the junction field effect transistor is used to replace the surface channel MOS transistor as the source follower transistor, this avoids the carrier in the conductive channel due to the interface state at the oxide layer-semiconductor substrate interface. It is randomly captured or released, thereby effectively reducing the flicker noise in the output voltage signal, thereby improving the imaging quality of the image sensor. In addition, in the junction field effect transistor, the PN junction on one side of the conduction channel is formed by depositing the doped layer of the second conduction type outside the surface of the substrate of the first conduction type and the doped layer of the first conduction type in contact with it. Formed by layers. Since the edge of the deposited doped layer of the second conductivity type can be formed by, for example, dry etching, its profile is easy to control, so the image sensor using the junction field effect transistor has high reliability, and the connection between different pixel units The difference in performance is minor.

In one embodiment, the deposited doped layer of the second conductivity type includes a doped polysilicon layer or an amorphous silicon layer. The doped polysilicon or amorphous silicon can be formed outside the surface of the substrate of the first conductivity type by chemical vapor deposition or other suitable deposition methods, instead of being formed in the substrate of the first conductivity type by ion implantation. This can reduce the ion implantation once, thereby reducing the manufacturing cost of the image sensor. In addition, due to the reduction of one ion implantation, the profile of the conductive channel in the source follower transistor is easy to control, and its performance will not be affected by the deep junction depth caused by too many annealing times. Therefore, the source-follower transistor does not need to form a deep isolation groove in the substrate of the first conductivity type outside its conduction channel to isolate adjacent regions, which can reduce the difficulty of manufacturing process and reduce the area of the image sensor.

In one embodiment, the well of the second conductivity type and the deposited doped layer of the second conductivity type at least partially overlap each other outside the doped layer of the first conductivity type, so that the well of the second conductivity type and the doped layer deposited with the second conductivity type are electrically connected to each other.

In one embodiment, the drain region of the first conductivity type and/or the doped layer of the first conductivity type are at least partially located outside the well of the second conductivity type, so that the drain region of the first conductivity type and the second conductivity type A conductive type substrate is electrically connected.

In one embodiment, the edge of the deposited doped layer of the second conductivity type is located on the dielectric layer on the surface of the substrate of the first conductivity type or on the isolation trench in the substrate of the first conductivity type. In the process of etching the doped layer of the second conductivity type, the dielectric layer between its edge and the substrate of the first conductivity type can stop the etching of the doped layer of the second conductivity type on the dielectric layer or the isolation trench groove, thereby avoiding damage to the substrate of the first conductivity type and the resulting damage to the transistor.

According to another aspect of the present invention, there is also provided a method for manufacturing a transistor, including the following steps: providing a substrate of a first conductivity type, and a well of a second conductivity type is formed in the substrate of the first conductivity type; Doping in the first conductivity type substrate and/or the second conductivity type well to form a first conductivity type doped layer; forming a second conductivity type deposited doped layer, which is located in the first conductivity type outside the surface of the substrate and at least partially on the doped layer of the first conductivity type, so that a PN junction is formed between the deposited doped layer of the second conductivity type and the doped layer of the first conductivity type; A first conductivity type source region is formed in the second conductivity type well, and a first conductivity type drain region is formed in the second conductivity type well and/or in the first conductivity type substrate, so that the first conductivity type A source region of a conductivity type is electrically connected to the drain region of the first conductivity type.

In one embodiment, the edge of the deposited doped layer of the second conductivity type is located on the dielectric layer on the surface of the substrate of the first conductivity type or on the isolation trench in the substrate of the first conductivity type.

In one embodiment, before the step of forming the deposited doped layer of the second conductivity type, it further includes: forming the dielectric layer on the surface of the substrate of the first conductivity type and/or forming the dielectric layer on the first conductivity type substrate An isolation trench is formed in the conductivity type substrate; and the step of forming the deposited doped layer of the second conductivity type further includes: partially etching the dielectric layer, so that the doped layer of the first conductivity type is at least partially exposing; depositing doped polysilicon or amorphous silicon on the exposed doped layer of the first conductivity type to form the deposited doped layer of the second conductivity type; and partially etching the deposited doped layer of the second conductivity type depositing the doped layer so that the edge of the etched second conductive type deposited doping layer is located on the dielectric layer and/or on the isolation trench.

In one embodiment, the step of partially etching the dielectric layer further includes: partially etching the dielectric layer, so that the doped layer of the first conductivity type and the well of the second conductivity type are at least partially exposed. .

In one embodiment, the step of depositing doped polysilicon or amorphous silicon further comprises: doping the deposited polysilicon or amorphous silicon while depositing the polysilicon or amorphous silicon, or After the polysilicon or amorphous silicon is deposited, the deposited polysilicon or amorphous silicon is doped.

The above and other characteristics of the present invention will be clearly illustrated in the Examples section hereinafter.

Description of drawings

The characteristics, objects and advantages of the present invention can be more readily understood by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein, the same or similar reference numerals represent the same or similar devices.

Fig. 1 shows a 4T pixel structure of a traditional CMOS image sensor;

FIG. 2 shows an image sensor 200 according to one embodiment of the present invention;

Figure 3a shows an example 300 of a source follower transistor of the image sensor 200 in Figure 2;

FIG. 3b shows another example of the source follower transistor of the image sensor 200 in FIG. 2;

FIG. 4a shows another example 400 of the source follower transistor of the image sensor 200 in FIG. 2;

Figure 4b shows a schematic cross-sectional view of the source-following transistor of Figure 4a along the direction AA';

FIG. 5a shows a fabrication method 500 of a transistor according to an embodiment of the present invention;

5b to 5e show schematic cross-sectional views of the manufacturing method 500 in FIG. 5a.

Detailed ways

The making and using of the embodiments are discussed in detail below. It should be understood, however, that the specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

Referring to FIG. 2 , an image sensor 200 according to one embodiment of the present invention is shown. The image sensor 200 includes a pixel array, and each pixel unit in the pixel array includes: a photodiode 201 for sensing changes in light intensity to generate corresponding the image charge signal; the transfer transistor 202 for transferring the image charge signal; and the source follower transistor 204 for generating a voltage signal based on the transferred image charge signal, wherein the source follower transistor 204 is a junction field effect transistor.

It should be noted that, in some examples, multiple pixel units in the pixel array may have one source follower transistor 204, for example, two, four or more adjacent pixel units may share one source follower transistor 204 to output voltage signal. In addition, in this embodiment, the source follower transistor 204 is a P-type field effect transistor. Those skilled in the art can understand that in other embodiments, the source follower transistor 204 can also be an N-type field effect transistor.

Specifically, the photodiode 201 is coupled between a reference potential line VSS, such as ground or a negative power supply potential, and the source of the transfer transistor 202 for sensing light intensity changes to form corresponding image charge signals. The drain of the transfer transistor 202 is connected to the gate of the source follower transistor 204. The gate of the transfer transistor 202 is used to receive the transfer control signal TX. Under the control of the transfer control signal TX, the transfer transistor 202 is turned on or off accordingly. Thus, the image charge signal induced by the photodiode 201 is read out to the floating diffusion region coupled to the drain of the transfer transistor 202 , and the image charge signal is stored by the floating diffusion region.

The source follower transistor 204 is coupled between the reference potential line VSS and the bias current source 205, its drain is coupled to the reference potential line VSS, its source is coupled to the bias current source 205 and used to output a voltage signal, which The gate is coupled to the drain of the transfer transistor 202 , that is, to the floating diffusion region, so as to obtain the image charge signal transferred by the transfer transistor 202 . Under the bias of the bias current source 205 , the voltage at the source of the source follower transistor 204 changes with the change of the image charge signal obtained by its gate, and its voltage gain is close to 1. In one embodiment, the source of the source follower transistor 204 is further coupled to a bit line (not shown in the figure) through a row selection transistor (not shown in the figure), and provides the voltage signal to the signal processing circuit of the image sensor .

In one embodiment, the image sensor further includes a reset transistor 203 , the drain of the reset transistor 203 is used to receive the reset signal RSG, and the source of the reset transistor 203 is coupled to the drain of the transfer transistor 202 and the gate of the source follower transistor 204 . The gate of the reset transistor 203 is used to receive a reset control signal RST. Under the control of the reset control signal RST, the reset transistor 203 is turned on or off accordingly, so as to provide a reset signal to the gate of the source follower transistor 204 . In this embodiment, both the transfer transistor 202 and the reset transistor 203 are NMOS transistors. It can be understood that in other embodiments, the transfer transistor 202 and the reset transistor 203 can also use other types of transistors, such as PMOS transistors or junction field transistors. effect tube.

Since the junction field effect transistor is used to replace the surface channel MOS transistor as the source follower transistor 204, this avoids the random capture or release of carriers in the conduction channel due to the interface state at the oxide layer-semiconductor substrate interface, thereby effectively The flicker noise in the output voltage signal is reduced, thereby improving the imaging quality of the image sensor 200 .

After the reset capacitor 213 and the image capacitor 211 respectively store charges corresponding to the reset signal and the image charge signal, the amplifying unit 215 amplifies the voltage difference between the two capacitors, and provides the amplified output voltage to the subsequent processing circuit .

FIG. 3 a shows an example 300 of a source follower transistor of the image sensor 200 in FIG. 2 , wherein the source follower transistor is a P-type field effect transistor. Those skilled in the art should understand that the working principle is also applicable to the case where the source follower transistor is an N-type field effect transistor.

As shown in Figure 3a, this source follower transistor consists of:

P-type substrate 301;

N-type well 303, which is located in the P-type substrate 301;

N-type deposited doped layer 305, which is located outside the surface of the P-type substrate 301 and at least partially located on the N-type well 303;

P-type source region 307, which is located in N-type well 303;

P-type drain region 309, which is located in the P-type substrate 301 and/or in the N-type well 303;

P-type doped layer 311, which is at least partially located between N-type well 303 and N-type deposited doped layer 305, so that P-type source region 307 is electrically connected to P-type drain region 309, and makes P-type source region 307 It is electrically connected to the P-type drain region 309 and forms PN junctions between the P-type doped layer 311 and the N-type well 303 and between the P-type doped layer 311 and the N-type deposited doped layer 305 .

Specifically, the P-type substrate 301 may be a P-type doped semiconductor wafer, or a P-type doped silicon-on-insulator (SOI), or a P-type well region in an N-type doped semiconductor wafer, or other Like a substrate or a well region.

All of the P-type source regions 307 are located in the N-type well 303 . The N-type well 303 isolates the P-type source region 307 from the P-type substrate 301 . Since the source region 307 is used to output a voltage signal, it may have a higher potential, and the P-type substrate 301 is usually coupled to a reference potential line, such as ground. Therefore, the source region 307 is isolated from the P-type substrate 301 to avoid substrate punch-through, so as to ensure the normal operation of the source follower transistor.

According to different specific embodiments, the P-type drain region 309 may be entirely located in the P-type substrate 301 outside the N-type well 303; or all be located in the N-type well 303; Located in the P-type substrate 301 outside the N-type well 303 . In the example 300 shown in FIG. 3 a , the P-type drain region 309 is entirely located in the N-type well 303 , so it is electrically connected to the P-type source region 307 through the P-type doped layer 311 in the N-type well 303 . In practical applications, the P-type source region 307 and the P-type drain region 309 partially overlap with the P-type doped layer 311 to realize electrical connection therebetween. Corresponding to the P-type doped layer 311 , the N-type deposited doped layer 305 may also be wholly or partially located on the N-type well 303 and located between the source region 307 and the drain region 309 . In the example 300 of FIG. 3 a , the layout of the N-type deposited doped layer 305 is entirely within the layout of the N-type well 303 .

The P-type doped layer 311 is located between the N-type well 303 and the N-type deposited doped layer 305 , and is electrically connected to the P-type source region 307 and the P-type drain region 309 . Since the P-type doped layer 311 is at least partly located in the N-type well 303 , the P-type doped layer 311 is in contact with the N-type well 303 , thereby forming a PN junction of the JFET near the contact interface. In addition, the P-type doped layer 311 is at least partially in contact with the N-type deposited doped layer 305 thereon, thereby forming another PN junction of the junction field effect transistor near its contact interface. This makes the N-type well 303 and the N-type deposited doped layer 305 function as the gate of the source-follower transistor, and the region between the two PN junctions is the conduction channel region of the source-follower transistor 300 . When the source follower transistor works, the difference in the voltage difference between the N-type deposited doped layer 305 (and the N-type well 303) and the source region 307 and the drain region 309 will cause the junction space charge region of these two PN junctions Width changes, that is, changing the thickness of the conductive channel of the junction field effect transistor, thereby changing the magnitude of the channel current. It should be noted that since the P-type doped layer 311 and the N-type deposited doped layer 305 are made of the same material, that is, silicon, the interface state defects at the contact surface are far less than those at the oxide layer-substrate interface. interface defects. Since the channel current is in the P-type doped layer 311 away from the surface of the P-type substrate 301, it is basically not affected by the interface state of the P-type substrate 301 surface oxide layer-substrate interface, thereby greatly reducing the interface state. The probability of defects randomly trapping or releasing carriers effectively reduces the flicker noise in the output voltage signal of the source follower transistor.

In some embodiments, the electrical contact between the N-type deposited doped layer 305 and the P-type doped layer 311 can be achieved by removing the dielectric layer 304 on the surface of the P-type substrate 301, such as an oxide layer, that is: A layer of oxide layer is usually formed on the surface of the P-type substrate 301, and the oxide layer above the P-type doped layer 311 can be partially removed to expose the P-type doped layer 311 from the surface of the P-type substrate 301; For example, doped polysilicon or amorphous silicon is deposited on the P-type substrate 301 to form the N-type deposited doped layer 305 . The dielectric layer 304 may be pre-formed on the surface of the P-type substrate 301 . Due to the isolation of the dielectric layer 304 , the N-type deposited doped layer 305 only contacts the P-type doped layer 311 to form a PN junction, but does not electrically contact the P-type source region 307 and the P-type drain region 309 . In some examples, the doped polysilicon layer or amorphous silicon layer can be doped together with the polysilicon or amorphous silicon layer when it is deposited, that is, a gas with dopant ions is added to the deposition reaction chamber . This eliminates the need to form the N-type deposited doped layer 305 by ion implantation, which can reduce one ion implantation, thereby reducing the manufacturing cost of the image sensor. It can be understood that, in some other examples, the N-type doped layer 305 can also be formed by depositing polysilicon or amorphous silicon first, and then doping the deposited polysilicon or amorphous silicon, For example, doping by ion implantation or diffusion.

In addition, the N-type deposited doped layer 305 can be controlled by, for example, dry etching, and its profile is easy to control, so the image sensor 300 using the junction field effect transistor has high reliability. Preferably, in the embodiment shown in FIG. 3 a , the edge of the N-type deposited doped layer 305 is located on the dielectric layer 304 . The dielectric layer 304 isolates the edge of the N-type deposited doped layer 305 from the P-type substrate 301 . In the process of etching the N-type deposited doped layer 305, the dielectric layer 304 between its edge and the P-type substrate 301 can make the etching of the N-type deposited doped layer 305 stop on the dielectric layer 304 , so as to avoid the damage of the P-type substrate 301 and the transistor damage caused thereby. In some examples, the part where the N-type deposited doped layer 305 is in contact with the P-type substrate 301 is located in the window of the dielectric layer 304, and its edge exceeds the edge of the window of the dielectric layer 304 by a certain length, such as 5 nanometers, 10 nanometers , 50nm, and so on.

In some examples, the N-type well 303 and the N-type deposited doped layer 305 may partially overlap each other outside the P-type doped layer 311 , so that the N-type well 303 and the N-type deposited doped layer 305 are electrically connected to each other. This eliminates the need to make additional via holes or other structures in the N-type well 303 to lead out the N-type well 303 , thereby reducing the manufacturing cost. It can be understood that, in some other examples, the N-type well 303 and the N-type deposited doped layer 305 may not be in direct contact with each other, but are electrically connected through holes in the dielectric layer 304 .

FIG. 3b shows another example of a source follower transistor of the image sensor 200 in FIG. 2 . In FIG. 3 b , a photodiode of the image sensor 200 is also shown, which is composed of a P-type substrate 301 and an N-type doped region 321 located outside the N-type well 303 .

As shown in FIG. 3 b , the P-type substrate 301 further includes an isolation trench 323 outside the N-type well 303 , that is, between the N-type doped region 321 and the N-type well 303 . The isolation trench 323 is formed by insulating materials such as silicon oxide and silicon nitride, so it has better electrical isolation effect. The isolation trench 323 in the P-type substrate 301 isolates the N-type doped region 321 and the N-type well 303 from each other, which can effectively prevent the negative electrode of the photodiode and the gate of the source follower transistor from being short-circuited (that is, punch-through) affect the operation of the image sensor. It can be seen that due to the reduction of one ion implantation, the profile of the conductive channel is easy to control, and no deep junction depth will be caused by too many annealing times. Therefore, the image sensor does not need to make a deep isolation trench in the P-type substrate 301 outside the conductive channel to isolate adjacent areas, that is, the isolation trench 323 can adopt a shallow trench isolation structure (Shallow Trench Isolation), and the chip it occupies The area is relatively small, so the area of the image sensor can be effectively reduced.

In a preferred embodiment, the isolation trench 323 can be adjacent to the P-type source region 307 and/or the N-type doped region 321 , which can further reduce the area of the image sensor, thereby improving chip integration. In particular, in the example shown in FIG. 3b, the isolation trench 323 is adjacent to the N-type well 303 and the P-type source region 307, which reduces the contact area between the N-type well 303 and the P-type substrate 301, thereby effectively The parasitic capacitance between the N-type well 303 and the P-type substrate 301 is reduced. In an image sensor, the N-type well 303 will be coupled to the floating diffusion region of the image sensor. It can be understood that the smaller the parasitic capacitance between the N-type well 303 and the P-type substrate 301, the higher the sensitivity of the image sensor. Therefore, the isolation trench 323 adjacent to the N-type well 303 and the P-type source region 307 can further improve the sensitivity of the image sensor.

In addition, in some embodiments, the edge of the N-type deposited doped layer 305 may also be located on the isolation trench 323 . The isolation trench 323 isolates the edge of the N-type deposited doped layer 305 from the P-type substrate 301 . In the process of etching the N-type deposited doped layer 305, the isolation trench 323 between its edge and the P-type substrate 301 can make the etching of the N-type deposited doped layer 305 stop on the isolation trench 323 , so as to avoid the damage of the P-type substrate 301 and the transistor damage caused thereby.

4a and 4b show another example 400 of the source follower transistor of the image sensor 200 in FIG. 2 . Wherein, FIG. 4b is a schematic cross-sectional view of the source follower transistor in FIG. 4a along the direction AA'.

As shown in FIG. 4a and FIG. 4b, the source-follower transistor has a structure similar to that of the source-follower transistor in FIG. 3a. However, the drain region 409 of the source follower transistor is located in the P-type substrate 401 outside the N-type well 403 , which makes the P-type doped drain region 409 electrically connected to the P-type substrate 401 . In practical applications, both the drain region 409 and the P-type substrate 401 are coupled to a reference potential line, such as ground, so there is no voltage difference between them, so that no current will form between the drain region 409 and the P-type substrate 401 .

Correspondingly, the P-type doped layer 411 at least partially extends from the N-type well 403 into the P-type substrate 401, so that the P-type substrate 401 and the P-type doped layer 411 are electrically connected to the source region 407 and the drain region 409. In this way, when the source follower transistor is turned on, the channel current can flow from the drain region 409 to the source region 407 through the P-type substrate 401 and the P-type doped layer 411 .

In particular, the image sensor 200 usually has a plurality of pixel units, and each pixel unit has a source follower transistor. For the drain regions 409 of these source follower transistors, some or all of the drain regions 409 may be at least partially located in the P-type substrate 401 outside the N-type well 403 . In this way, these drain regions 409 located outside the N-type well 403 can have the same potential as the P-type substrate 401 , so that they have the same potential with each other. Therefore, this can improve the effect of grounding without increasing the chip area. For example, the grounding can be shared through the P-type substrate 401, which avoids inconsistent grounding potentials of different pixel units, thereby further improving the performance of the image sensor.

Referring to FIG. 4 a , the N-type well 403 and the N-type deposited doped layer 405 at least partially overlap each other outside the P-type doped layer 411 , so that the N-type well 403 and the N-type deposited doped layer 405 are electrically connected to each other. This eliminates the need to make additional via holes in the N-type well 403 to lead out the N-type well 403 , thereby reducing the manufacturing cost.

Fig. 5a shows a method 500 for fabricating a transistor according to an embodiment of the present invention.

As shown in Figure 5a, the manufacturing method 500 includes:

Executing step S501, providing a substrate of a first conductivity type, in which a well of a second conductivity type is doped;

Execute step S503, doping the substrate of the first conductivity type and/or the well of the second conductivity type to form a doped layer of the first conductivity type;

Step S505 is executed to form a deposited doped layer of the second conductivity type, which is located outside the surface of the substrate of the first conductivity type and at least partially on the doped layer of the first conductivity type, so that the deposited doped layer of the second conductivity type and A PN junction is formed between the doped layers of the first conductivity type;

Execute step S507, forming a source region of the first conductivity type in the well of the second conductivity type, and forming a drain region of the first conductivity type in the well of the second conductivity type and/or in the substrate of the first conductivity type, so that the first conductivity type The source region of the first conductivity type is electrically connected to the drain region of the first conductivity type.

It can be understood that the transistor fabrication method 500 can be used to fabricate source-follower transistors in image sensors. In practical applications, the process of making an image sensor also includes steps of forming photodiodes in pixel units of the image sensor, and other transistors, such as transfer transistors, reset transistors, and row selection transistors, which will not be repeated here.

In some examples, the edge of the deposited doped layer of the second conductivity type is located on the dielectric layer on the surface of the substrate of the first conductivity type, or on the isolation trench in the substrate of the first conductivity type. In the process of etching the deposited doped layer of the second conductivity type, the dielectric layer or isolation trench between its edge and the substrate of the first conductivity type can make the etching of the deposited doped layer of the second conductivity type automatic stop on the dielectric layer or the isolation trench, so as to avoid etching damage to the substrate of the first conductivity type and the resulting damage to the transistor.

In some examples, before step S505, it also includes: forming a dielectric layer on the surface of the substrate of the first conductivity type and/or forming an isolation trench in the substrate of the first conductivity type; The step of the impurity layer further includes: partially etching the dielectric layer, so that the doped layer of the first conductivity type is at least partially exposed; depositing doped polysilicon or amorphous silicon on the exposed doped layer of the first conductivity type to form Depositing the doped layer of the second conductivity type; and partially etching the doped layer of the second conductivity type so that the edge of the etched doped layer of the second conductivity type is located on the dielectric layer and/or isolating the trench superior.

In one embodiment, the step of partially etching the dielectric layer further includes: partially etching the dielectric layer so that the doped layer of the first conductivity type and the well of the second conductivity type are at least partially exposed. Therefore, doped polysilicon or amorphous silicon needs to be deposited on the exposed doped layer of the first conductivity type and the well of the second conductivity type to form a deposited doped layer of the second conductivity type. The doped layer of the electrode of the second conductivity type directly formed on the well of the second conductivity type can be in electrical contact with the well of the second conductivity type below, so that the well of the second conductivity type can be electrically drawn out without making via holes or other electrical contacts. The connection structure is used to lead out the second conductivity type well.

5b to 5e show schematic cross-sectional views of the manufacturing method 500 of FIG. 5a. Wherein, the transistor formed by the manufacturing method 500 is a P-type field effect transistor. Those of ordinary skill in the art should understand that the working principle is also applicable to the case where the transistor is an N-type field effect transistor. Next, with reference to FIGS. 5 a to 5 e , an embodiment of a method 500 for fabricating the transistor for an image sensor will be described in detail.

As shown in FIG. 5 b , a P-type substrate 501 is provided, and a photodiode region 502 and an N-type well 503 are formed in the P-type substrate 501 . The N-type well 503 and the photodiode region 502 are separated from each other by the P-type substrate 501 therebetween.

Afterwards, as shown in FIG. 5 c , a P-type doped layer 511 is formed, which is at least partially located in the N-type well 503 . In FIG. 5 c , the P-type doped layer 511 is entirely located in the N-type well 503 . In addition, a PN junction of the transistor is formed between the N-type well 503 and the P-type doped layer 511 located therein. In some other embodiments, the P-type doped layer 511 may also be partially located in the P-type substrate 501 and partially located in the N-type well 503 . It should be noted that the steps of forming the P-type doped layer 511 and the N-type well 503 are usually implemented by ion implantation. After each ion implantation, the P-type substrate 501 needs to be annealed, such as rapid annealing. To activate ions and reduce lattice defects caused by implantation.

Next, a dielectric layer 504 is formed on the surface of the P-type substrate 501 . The dielectric layer 504 is, for example, silicon oxide or other dielectric materials, and the dielectric layer 504 can be formed by, for example, an oxidation process or a deposition process. Optionally, in some examples, an isolation trench (not shown in the figure) may also be formed in the P-type substrate 501 , and the isolation trench is generally located outside the N-type well 511 .

Then, as shown in FIG. 5d, an N-type deposited doped layer 505 is formed, which is located outside the surface of the P-type substrate 501 and at least partially on the N-type well 503, so that the N-type deposited doped layer 505 and the N-type A PN junction is formed between the P-type doped layers 511 in the well 503 .

Specifically, the N-type deposited doped layer 505 can be formed through the following steps: first, partially etch the dielectric layer 504 to form a window on the P-type substrate 501, and the window makes the P-type doped layer 511 at least Partially exposed; Next, deposit doped polysilicon or amorphous silicon on the exposed P-type doped layer 511 to form an N-type deposited doped layer 505; afterward, partially etch the N-type deposited doped layer 505 and The edge of the N-type deposited doped layer 505 is located on the dielectric layer 504, or the edge of the N-type deposited doped layer 505 is located on the isolation trench, that is, the edge of the N-type deposited doped layer 505 is not directly located on the P-type substrate 501. In some examples, polysilicon or amorphous silicon can be deposited by a chemical vapor deposition process, and the polysilicon or amorphous silicon can be doped with P-type ions, such as phosphorus or arsenic ions, to form doped polysilicon or amorphous silicon. In other examples, polysilicon or amorphous silicon can be deposited by chemical vapor deposition, and then P-type ions can be doped in the deposited polysilicon or amorphous silicon, for example, by diffusion or ion implantation. . In some other examples, polysilicon or amorphous silicon can be deposited by chemical vapor deposition process, and then the deposited polysilicon or amorphous silicon can be partially etched, and then the source region and the drain region can be formed before or after forming The etched polysilicon or amorphous silicon is ion-implanted to dope impurity ions.

In a preferred embodiment, the N-type doped layer 505 is also directly formed on the N-type well 503 . Correspondingly, the dielectric layer 504 is etched such that the P-type doped layer 511 and the N-type well 503 are at least partially exposed, and doped polysilicon or doped polysilicon is deposited on the exposed P-type doped layer 511 and the N-type well 503 Amorphous silicon is used to form N-type deposited doped layers.

It can be seen that through the window of the dielectric layer, the deposited polysilicon can directly contact the underlying P-type doped layer 511, thereby forming a PN junction on the other side of the conduction channel of the JFET. This PN junction together with the PN junction between the P-type doped layer 511 and the N-type well 503 jointly define the conduction channel of the junction field effect transistor, and the N-type well 503 and the N-type deposited doped layer 505 together act as The two gates of a junction field effect transistor.

Next, as shown in FIG. 5e, a P-type source region 507 and a P-type drain region 509 are formed in the N-type well 503, and the P-type source region 507 and the P-type drain region 509 are electrically connected to each other. In the example of FIG. 5e, the P-type source region 507 and the P-type drain region 509 are electrically connected through the P-type doped layer 511 therebetween. It can be understood that in some embodiments, the P-type drain region 509 can also be formed on the P-type substrate 501 outside the N-type well 503, and the P-type drain region 509 can pass through the P-type substrate between the P-type drain region 509 and the N-type well 503. The bottom 501 is electrically connected to the N-type well 503 , and is further electrically connected to the P-type source region 507 through the P-type doped layer 511 .

It can be seen that since the N-type deposition doped layer 505 can be formed in the P-type substrate 501 without ion implantation, it can be formed through a deposition process. This can reduce one ion implantation and annealing treatment, thereby reducing the manufacturing cost of the transistor. In addition, due to the reduction of one ion implantation, the profile of the conductive channel is easy to control, and no deep junction depth will be caused by too many times of annealing. Therefore, the junction field effect transistor does not need to form a deep isolation trench in the P-type substrate 501 outside the conductive channel to isolate adjacent regions, such as between the N-type well 503 and the photodiode region 502, which can reduce the manufacturing process. difficulty, and reduce the transistor area.

While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative and exemplary and not restrictive; the invention is not limited to the foregoing embodiments.

Other changes to the disclosed embodiments can be understood and effected by those of ordinary skill in the art by studying the specification, disclosure, drawings and appended claims. In the claims, the word "comprising" does not exclude other elements and steps, and the word "a" does not exclude a plurality. In the actual application of the invention, one component may perform the functions of multiple technical features cited in the claims. Any reference signs in the claims should not be construed as limiting the scope.

Claims (10)

1. an imageing sensor, is characterized in that, comprises pel array, and the one or more pixel cells in described pel array comprise a source and follow transistor, and it is junction field effect transistor that transistor is followed in described source, and it comprises:

First conductivity type substrate;

Second conductive type of trap, is arranged in described first conductivity type substrate;

Second conduction type deposit doped layer, to be positioned at outside described first conductivity type substrate surface and to be positioned on described second conductive type of trap at least partly;

First conduction type source region, is arranged in described second conductive type of trap;

First conductivity type drain region, is arranged in described first conductivity type substrate and/or is arranged in described second conductive type of trap;

First conduction type doped layer, at least partly between described second conductive type of trap and described second conduction type deposit doped layer, to make described first conduction type source region be electrically connected with described first conductivity type drain region, and form PN junction respectively between itself and described second conductive type of trap and between itself and described second conduction type deposit doped layer.

2. imageing sensor according to claim 1, is characterized in that, described second conduction type deposit doped layer comprises polysilicon layer or the amorphous silicon layer of doping.

3. imageing sensor according to claim 1, it is characterized in that, described second conductive type of trap and described second conduction type deposit doped layer are outer overlapped at least partly at described first conduction type doped layer, are electrically connected to each other to make described second conductive type of trap and described second conduction type deposit doped layer.

4. imageing sensor according to claim 1, it is characterized in that, described first conductivity type drain region and/or described first conduction type doped layer are positioned at outside described second conductive type of trap at least partly, are electrically connected with the first conductivity type substrate to make described first conductivity type drain region.

5. imageing sensor according to claim 1, is characterized in that, on the dielectric layer that the edge of described second conduction type deposit doped layer is arranged in the first conductivity type substrate surface or be positioned on the isolated groove of the first conductivity type substrate.

6. a manufacture method for transistor, is characterized in that, comprises the steps:

There is provided the first conductivity type substrate, in described first conductivity type substrate, doping is formed with the second conductive type of trap;

Adulterate formation first conduction type doped layer in described first conductivity type substrate and/or described second conductive type of trap;

Form the second conduction type deposit doped layer, it to be positioned at outside described first conductivity type substrate surface and to be positioned on described first conduction type doped layer at least partly, to make to form PN junction between described second conduction type deposit doped layer and described first conduction type doped layer;

The first conduction type source region is formed in described second conductive type of trap, and the first conductivity type drain region is formed in described second conductive type of trap and/or in described first conductivity type substrate, be electrically connected with described first conductivity type drain region to make described first conduction type source region.

7. manufacture method according to claim 6, is characterized in that, on the dielectric layer that the edge of described second conduction type deposit doped layer is arranged in the first conductivity type substrate surface or be positioned on the isolated groove of the first conductivity type substrate.

8. manufacture method according to claim 7, is characterized in that,

Before the step forming described second conduction type deposit doped layer, also comprise: form described dielectric layer on described first conductivity type substrate surface and/or form isolated groove in described first conductivity type substrate;

And the step of described formation second conduction type deposit doped layer comprises further:

Dielectric layer described in partial etching, exposes at least partly to make described first conduction type doped layer;

The polysilicon of deposit doping on described the first conduction type doped layer exposed or amorphous silicon are to form described second conduction type deposit doped layer; And

Second conduction type deposit doped layer described in partial etching also makes the second conduction type deposit doped layer edge be etched be positioned on described dielectric layer and/or on described isolated groove.

9. manufacture method according to claim 8, is characterized in that, the step of described partial etching dielectric layer comprises further: dielectric layer described in partial etching, exposes at least partly to make described first conduction type doped layer and described second conductive type of trap.

10. manufacture method according to claim 8, it is characterized in that, the described polysilicon of deposit doping or the step of amorphous silicon comprise further: adulterate to the polysilicon of institute's deposit or amorphous silicon while polysilicon described in deposit or amorphous silicon, or after polysilicon described in deposit or amorphous silicon, the polysilicon of institute's deposit or amorphous silicon are adulterated.