CN102714181A - Semiconductor device - Google Patents
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- CN102714181A CN102714181A CN2010800555749A CN201080055574A CN102714181A CN 102714181 A CN102714181 A CN 102714181A CN 2010800555749 A CN2010800555749 A CN 2010800555749A CN 201080055574 A CN201080055574 A CN 201080055574A CN 102714181 A CN102714181 A CN 102714181A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 81
- 238000009792 diffusion process Methods 0.000 claims abstract description 292
- 230000003068 static effect Effects 0.000 claims abstract description 81
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 238000003860 storage Methods 0.000 claims abstract description 18
- 238000005468 ion implantation Methods 0.000 claims description 10
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 claims description 7
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 239000011574 phosphorus Substances 0.000 claims description 7
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- 238000004519 manufacturing process Methods 0.000 description 64
- 150000004767 nitrides Chemical class 0.000 description 18
- 238000010438 heat treatment Methods 0.000 description 16
- 229910052751 metal Inorganic materials 0.000 description 15
- 239000002184 metal Substances 0.000 description 15
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 8
- 229910052785 arsenic Inorganic materials 0.000 description 8
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
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- 230000000694 effects Effects 0.000 description 6
- 229910021332 silicide Inorganic materials 0.000 description 6
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 4
- 229910052796 boron Inorganic materials 0.000 description 4
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- 239000011229 interlayer Substances 0.000 description 4
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- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 2
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/016—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including vertical IGFETs
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
- H10B10/125—Static random access memory [SRAM] devices comprising a MOSFET load element the MOSFET being a thin film transistor [TFT]
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B99/00—Subject matter not provided for in other groups of this subclass
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/02—Manufacture or treatment characterised by using material-based technologies
- H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
- H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
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- Semiconductor Memories (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
本发明的半导体存储器件由在衬底上排列有6个MOS晶体管的静态型存储单元所构成。所述6个MOS晶体管分别由用以存取存储器的第1及第2NMOS存取晶体管、用以驱动用来保持存储单元的数据的存储节点的第3及第4NMOS驱动晶体管、及供给用以保持存储单元的数据的电荷的第1及第2PMOS负载晶体管所构成。用以存取存储器的第1及第2NMOS存取晶体管，在与衬底垂直的方向阶层地配置有第1扩散层、柱状半导体层及第2扩散层；所述柱状半导体层配置在所述第1扩散层与所述第2扩散层之间，且在所述柱状半导体层的侧壁形成有栅极。用以保持存储单元的数据而驱动存储节点的第3及第4NMOS驱动晶体管，在与衬底垂直的方向阶层地配置有第3扩散层、柱状半导体层及第4扩散层，所述柱状半导体层配置在所述第3扩散层与所述第4扩散层之间，且在所述柱状半导体层的侧壁形成有栅极；用以保持存储单元的数据而供给电荷的第1及第2PMOS负载晶体管分别在与衬底垂直的方向阶层地配置有第5扩散层、柱状半导体层及第6扩散层，所述柱状半导体层配置在所述第5扩散层与所述第6扩散层之间，且在所述柱状半导体层的侧壁形成有栅极。再者，形成第3及第4NMOS驱动晶体管的第3扩散层的上端与第4扩散层的下端之间的长度，比形成第1及第2NMOS存取晶体管的第1扩散层的上端与第2扩散层的下端之间的长度为短。
The semiconductor memory device of the present invention is composed of a static type memory cell in which six MOS transistors are arranged on a substrate. The 6 MOS transistors are respectively provided by the first and second NMOS access transistors for accessing the memory, the third and fourth NMOS drive transistors for driving the storage nodes used to hold the data of the memory cells, and the supply for holding The data charge of the memory cell is composed of the first and second PMOS load transistors. The first and second NMOS access transistors for accessing the memory are arranged in layers in a direction perpendicular to the substrate with a first diffusion layer, a columnar semiconductor layer, and a second diffusion layer; the columnar semiconductor layer is arranged on the first Between the first diffusion layer and the second diffusion layer, a gate is formed on a side wall of the columnar semiconductor layer. The third and fourth NMOS drive transistors used to hold the data of the memory cell and drive the storage node are provided with a third diffusion layer, a columnar semiconductor layer, and a fourth diffusion layer in a layered manner in a direction perpendicular to the substrate. The columnar semiconductor layer Arranged between the third diffusion layer and the fourth diffusion layer, and a gate is formed on the side wall of the columnar semiconductor layer; the first and second PMOS loads are used to hold the data of the memory cell and supply the charge The transistor has a fifth diffusion layer, a columnar semiconductor layer, and a sixth diffusion layer arranged in layers in a direction perpendicular to the substrate, the columnar semiconductor layer is arranged between the fifth diffusion layer and the sixth diffusion layer, And a gate is formed on the sidewall of the columnar semiconductor layer. Furthermore, the length between the upper end of the third diffusion layer forming the third and fourth NMOS drive transistors and the lower end of the fourth diffusion layer is greater than the length between the upper end and the second diffusion layer forming the first and second NMOS access transistors. The length between the lower ends of the diffusion layer is short.
Description
技术领域 technical field
本发明涉及一种半导体器件。 The present invention relates to a semiconductor device. the
背景技术 Background technique
使用半导体集成电路、特别是使用MOS晶体管的集成电路迈向高集成化。随着该高集成化，其中所使用的MOS晶体管的微细化进展至纳米领域。数字电路的基本电路虽为逆变器电路(inverter circuit)，但若构成该逆变器电路的MOS晶体管进一步细微化，则会有以下问题：漏电流的抑制困难，因热载体效应而造成可靠性降低，且因要求确保所需的电流量而无法缩小电路的占有面积。为了解决以上的问题，提案一种对衬底在垂直方向配置源极、栅极、漏极，且栅极围绕岛状半导体层的构造的环绕栅极晶体管（SurroundingGate Transistor，SGT)(参照例如专利文献1、专利文献2、专利文献3)。 Integrated circuits using semiconductor integrated circuits, especially integrated circuits using MOS transistors, are advancing toward high integration. Along with this high integration, miniaturization of MOS transistors used therein has progressed to the nanometer range. Although the basic circuit of a digital circuit is an inverter circuit, if the MOS transistors constituting the inverter circuit are further miniaturized, there will be the following problems: it is difficult to suppress the leakage current, and reliability is caused by the heat carrier effect. performance is reduced, and it is impossible to reduce the occupied area of the circuit because it is required to ensure the required amount of current. In order to solve the above problems, a kind of surrounding gate transistor (SurroundingGate Transistor, SGT) with a structure in which the source, gate and drain are arranged in the vertical direction to the substrate, and the gate surrounds the island-shaped semiconductor layer is proposed (see for example patent Document 1, Patent Document 2, Patent Document 3). the
在静态型存储单元中，已知通过将驱动晶体管的电流驱动力设为存取晶体管的电流驱动力的2倍，而确保动作稳定性（非专利文献1）。 In static memory cells, it is known that operation stability can be ensured by making the current driving force of the drive transistor twice that of the access transistor (Non-Patent Document 1). the
若欲以上述SGT构成静态型存储单元时，为了确保动作稳定性，而欲实现将驱动晶体管的电流驱动力设为存取晶体管的电流驱动力的2倍时，由于必须将栅极宽度设为2倍，因而使用2个驱动晶体管。亦即，造成存储单元面积的增大。 If the above-mentioned SGT is used to form a static memory cell, in order to ensure the stability of the operation, when the current driving force of the driving transistor is set to be twice the current driving force of the access transistor, the gate width must be set to 2 times, thus using 2 drive transistors. That is, an increase in the memory cell area is caused. the
再者，SGT的制造方法提案有一种在形成柱状半导体层后，堆积栅极导电膜，并使之平坦化，进行蚀刻而作成所希望的长度的技术（专利文献4）。依据以该高集成且高性能而获得高良率的SGT的制造方法，SGT的物理栅极长度在晶圆上的全部的晶体管中为一定。 Furthermore, a method of manufacturing SGT is proposed in which, after forming a columnar semiconductor layer, a gate conductive film is deposited, planarized, and etched to have a desired length (Patent Document 4). According to this high-integration and high-performance SGT manufacturing method that achieves a high yield, the physical gate length of the SGT is constant for all transistors on the wafer. the
此外，若静态型存储单元更进一步微细化，因尺寸缩小，连接于存储节点的MOS晶体管的栅极电容及扩散层电容会减少，此时若将放射线从外部照射至静态型存储单元时，会在半导体衬底内沿着放射线的射程，产生电子空穴对，该电子空穴对的至少一方会流入形成漏极的扩散层而产生数据的反 转，并产生无法保持正确数据的软性错误现象。该软性错误现象存储单元的微细化越进展，连接于存储节点的MOS晶体管的栅极电容及扩散层电容的减少会比在放射线产生的电子空穴对更显著，因此近年来在微细化进展的静态型存储单元中成为重大的问题。因此，已有报导在静态型存储单元的存储节点形成电容器，以确保存储节点所需的充分电荷量，藉此避免软性错误，以确保动作稳定性（专利文献5）。 In addition, if the static memory cell is further miniaturized, the gate capacitance and the diffusion layer capacitance of the MOS transistor connected to the storage node will decrease due to the reduction in size. Electron-hole pairs are generated along the range of radiation in the semiconductor substrate, and at least one of the electron-hole pairs will flow into the diffusion layer forming the drain to cause data inversion and soft errors that cannot maintain correct data. Phenomenon. As the miniaturization of the memory cell of this soft error phenomenon progresses, the reduction of the gate capacitance and the diffusion layer capacitance of the MOS transistor connected to the storage node will be more significant than the electron-hole pairs generated by radiation. Therefore, miniaturization has progressed in recent years. becomes a significant problem in static memory units. Therefore, it has been reported that a capacitor is formed at the storage node of a static memory cell to ensure sufficient charge required by the storage node, thereby avoiding soft errors and ensuring operational stability (Patent Document 5). the
（先前技术文献） (Prior technical literature)
（专利文献） (patent literature)
专利文献1：日本特开平2-71556号公报 Patent Document 1: Japanese Patent Application Laid-Open No. 2-71556
专利文献2：日本特开平2-188966号公报 Patent Document 2: Japanese Patent Laying-Open No. 2-188966
专利文献3：日本特开平3-145761号公报 Patent Document 3: Japanese Patent Application Laid-Open No. 3-145761
专利文献4：日本特开2009-182317号公报 Patent Document 4: Japanese Patent Laid-Open No. 2009-182317
专利文献5：日本特开2008-227344号公报 Patent Document 5: Japanese Patent Laid-Open No. 2008-227344
（非专利文献） (non-patent literature)
H.Kawasaki,M.Khater,M.Guillorn,N.Fuller,J.Chang,S.Kanakasabapathy,L.Chang,R.Muralidhar,K.Babich,Q.Yang,J.Ott,D.Klaus,E.Kratschmer,E.Sikorski,R.Miller,R.Viswanathan,Y.Zhang,J.Silverman,Q.Ouyang,A.Yagishita,M.Takayanagi,W.Haensch,and K.Ishimaru,″Demonstration of Highly Scaled FinFET SRAM Cells with High-κ/Metal Gateand Investigation of Characteristic Variability for the 32nm node and beyond（具有高介电常数/金属栅极的高度缩放薄膜晶体管静态存储器单元的示范及对于32纳米以下的节点的特性变动的调查）″,IEDM,237-240页,2008. H. Kawasaki, M. Khater, M. Guillorn, N. Fuller, J. Chang, S. Kanakasabapathy, L. Chang, R. Muralidhar, K. Babich, Q. Yang, J. Ott, D. Klaus, E. Kratschmer, E. Sikorski, R. Miller, R. Viswanathan, Y. Zhang, J. Silverman, Q. Ouyang, A. Yagishita, M. Takayanagi, W. Haensch, and K. Ishimaru, "Demonstration of Highly Scaled FinFET SRAM Cells with High-κ/Metal Gate and Investigation of Characteristic Variability for the 32nm node and beyond )", IEDM, pages 237-240, 2008.
发明内容 Contents of the invention
（发明所欲解决的问题） (Problem to be solved by the invention)
因此，本发明的课题在于提供一种以利用SGT的高集成确保动作稳定性的静态型存储单元。 Therefore, an object of the present invention is to provide a static memory cell that ensures operational stability by high integration using SGTs. the
（解决问题的手段） (means to solve the problem)
为了达成所述目的，本发明的半导体器件，为具备在衬底上排列有6个MOS晶体管的静态型存储单元的半导体存储器件，其中，所述6个MOS晶 体管由用以存取存储器的第1及第2NMOS存取晶体管、用以驱动用来保持存储单元的数据的存储节点的第3及第4NMOS驱动晶体管、及供给用以保持存储单元的数据的电荷的第1及第2PMOS负载晶体管所构成，用以存取存储器的第1及第2NMOS存取晶体管，分别以使柱状半导体层配置在第1扩散层与第2扩散层之间的方式在与衬底垂直的方向阶层地配置有所述第1扩散层、所述柱状半导体层及所述第2扩散层，且在所述柱状半导体层的侧壁形成有栅极；用以保持存储单元的数据而驱动存储节点的第3及第4NMOS驱动晶体管，分别以使柱状半导体层配置在第3扩散层与第4扩散层之间的方式在与衬底垂直的方向阶层地配置有所述第3扩散层、所述柱状半导体层及所述第4扩散层，且在所述柱状半导体层的侧壁形成有栅极；用以保持存储单元的数据而供给电荷的第1及第2PMOS负载晶体管，分别以使柱状半导体层配置在第5扩散层与第6扩散层之间的方式在与衬底垂直的方向阶层地配置有所述第5扩散层、所述柱状半导体层及所述第6扩散层，且在所述柱状半导体层的侧壁形成有栅极；所述第1扩散层、第3扩散层、第5扩散层分别与衬底电性绝缘地配置；形成所述第3及第4NMOS驱动晶体管的第3扩散层的上端与第4扩散层的下端之间的长度，比形成第1及第2NMOS存取晶体管的第1扩散层的上端与第2扩散层的下端之间的长度为短。 In order to achieve the above object, the semiconductor device of the present invention is a semiconductor memory device having a static memory cell with six MOS transistors arranged on the substrate, wherein the six MOS transistors are used to access the memory The first and second NMOS access transistors, the third and fourth NMOS drive transistors for driving the storage nodes for holding the data of the memory cells, and the first and second PMOS loads for supplying the charges for holding the data of the memory cells Composed of transistors, the first and second NMOS access transistors for accessing the memory are arranged in layers in the direction perpendicular to the substrate so that the columnar semiconductor layer is arranged between the first diffusion layer and the second diffusion layer. There are the first diffusion layer, the columnar semiconductor layer, and the second diffusion layer, and a gate is formed on the sidewall of the columnar semiconductor layer; a third gate for maintaining data of the memory cell and driving the storage node and a fourth NMOS drive transistor, wherein the third diffusion layer, the columnar semiconductor layer are arranged in layers in a direction perpendicular to the substrate so that the columnar semiconductor layer is arranged between the third diffusion layer and the fourth diffusion layer and the fourth diffusion layer, and a gate is formed on the sidewall of the columnar semiconductor layer; the first and second PMOS load transistors for maintaining the data of the memory cell and supplying charges are arranged so that the columnar semiconductor layer is arranged on the Between the fifth diffusion layer and the sixth diffusion layer, the fifth diffusion layer, the columnar semiconductor layer, and the sixth diffusion layer are arranged in layers in a direction perpendicular to the substrate, and the columnar semiconductor A gate is formed on the sidewall of the layer; the first diffusion layer, the third diffusion layer, and the fifth diffusion layer are arranged electrically insulated from the substrate; the third diffusion layer of the third and fourth NMOS drive transistors is formed The length between the upper end of the first diffusion layer and the lower end of the fourth diffusion layer is shorter than the length between the upper end of the first diffusion layer and the lower end of the second diffusion layer forming the first and second NMOS access transistors. the
此外，本发明的优选实施方式中，提供一种半导体器件，为具备在衬底上排列有6个MOS晶体管的静态型存储单元的半导体存储器件，其中，所述6个MOS晶体管由用以存取存储器的第1及第2NMOS存取晶体管、为了保持存储单元的数据而驱动存储节点的第3及第4NMOS驱动晶体管、及为了保持存储单元的数据而供给电荷的第1及第2PMOS负载晶体管所构成，用以存取存储器的第1及第2NMOS存取晶体管，分别以使柱状半导体层配置在第1扩散层与第2扩散层之间的方式在与衬底垂直的方向阶层地配置有所述第1扩散层、所述柱状半导体层及所述第2扩散层，且在所述柱状半导体层的侧壁形成有栅极；用以保持存储单元的数据而驱动存储节点的第3及第4NMOS驱动晶体管，分别以使柱状半导体层配置在第3扩散层与第4扩散层之间的方式在与衬底垂直的方向阶层地配置有所述第3扩散层、所述柱状半导体层及所述第4扩散层，且在所述柱状半导体层的侧壁形成有栅极；所述第1扩散层、第3扩散层、第5扩散层分别与衬底电性绝缘地配置；用 以保持存储单元的数据而供给电荷的第1及第2PMOS负载晶体管，分别以使柱状半导体层配置在第5扩散层与第6扩散层之间的方式在与衬底垂直的方向阶层地配置有所述第5扩散层、所述柱状半导体层及所述第6扩散层，且在所述柱状半导体层的侧壁形成有栅极；形成所述第3及第4NMOS驱动晶体管的第3扩散层的上端与第4扩散层的下端之间的长度，比形成第1及第2PMOS负载晶体管的第5扩散层的上端与第6扩散层的下端之间的长度为短。 In addition, in a preferred embodiment of the present invention, a semiconductor device is provided, which is a semiconductor memory device having a static memory cell with six MOS transistors arranged on a substrate, wherein the six MOS transistors are used to store The first and second NMOS access transistors for accessing the memory, the third and fourth NMOS drive transistors for driving the storage node in order to hold the data of the memory cell, and the first and second PMOS load transistors for supplying charge in order to hold the data of the memory cell The first and second NMOS access transistors for accessing the memory are arranged in layers in a direction perpendicular to the substrate so that the columnar semiconductor layer is arranged between the first diffusion layer and the second diffusion layer. The first diffusion layer, the columnar semiconductor layer, and the second diffusion layer, and gates are formed on the sidewalls of the columnar semiconductor layer; the third and second gates are used to hold the data of the memory cell and drive the storage node 4 NMOS drive transistors, in which the third diffusion layer, the columnar semiconductor layer, and the The fourth diffusion layer, and a gate is formed on the sidewall of the columnar semiconductor layer; the first diffusion layer, the third diffusion layer, and the fifth diffusion layer are respectively electrically insulated from the substrate; The first and second PMOS load transistors for storing the data of the cell and supplying charges are respectively arranged in layers in a direction perpendicular to the substrate in such a manner that the columnar semiconductor layer is arranged between the fifth diffusion layer and the sixth diffusion layer. The fifth diffusion layer, the columnar semiconductor layer and the sixth diffusion layer, and a gate is formed on the sidewall of the columnar semiconductor layer; the upper end of the third diffusion layer forming the third and fourth NMOS drive transistors The length between the lower end of the fourth diffusion layer is shorter than the length between the upper end of the fifth diffusion layer forming the first and second PMOS load transistors and the lower end of the sixth diffusion layer. the
此外，本发明的优选实施方式中，形成所述第1及第2NMOS存取晶体管的第1扩散层的上端与第2扩散层的下端之间的长度，为形成在第3及第4NMOS驱动晶体管的第3扩散层的上端与第4扩散层的下端之间的长度的1.3倍至3倍的范围。 In addition, in a preferred embodiment of the present invention, the length between the upper end of the first diffusion layer and the lower end of the second diffusion layer forming the first and second NMOS access transistors is equal to that of the third and fourth NMOS drive transistors. 1.3 times to 3 times the length between the upper end of the third diffusion layer and the lower end of the fourth diffusion layer. the
此外，本发明的优选实施方式中，形成所述第1及第2PMOS负载晶体管的第5扩散层的上端与第6扩散层的下端之间的长度，为形成在第3及第4NMOS驱动晶体管的第3扩散层的上端与第4扩散层的下端之间的长度的1.3倍至3倍的范围。 In addition, in a preferred embodiment of the present invention, the length between the upper end of the fifth diffusion layer and the lower end of the sixth diffusion layer forming the first and second PMOS load transistors is equal to that of the third and fourth NMOS drive transistors. The range of 1.3 times to 3 times the length between the upper end of the third diffusion layer and the lower end of the fourth diffusion layer. the
此外，本发明的优选实施方式中，所述栅极的从下端至上端的长度相同。 In addition, in a preferred embodiment of the present invention, the gates have the same length from the lower end to the upper end. the
此外，本发明的优选实施方式中，所述第3及第4NMOS驱动晶体管的第3扩散层的上端，比所述第1及第2NMOS存取晶体管的第1扩散层的上端为高。 Furthermore, in a preferred embodiment of the present invention, upper ends of the third diffusion layers of the third and fourth NMOS drive transistors are higher than upper ends of the first diffusion layers of the first and second NMOS access transistors. the
此外，本发明的优选实施方式中，所述第3及第4NMOS驱动晶体管的第4扩散层的下端，比所述第1及第2NMOS存取晶体管的第2扩散层的下端为低。 Furthermore, in a preferred embodiment of the present invention, lower ends of the fourth diffusion layers of the third and fourth NMOS drive transistors are lower than lower ends of the second diffusion layers of the first and second NMOS access transistors. the
此外，本发明的优选实施方式中，所述第3及第4NMOS驱动晶体管的第3扩散层的上端，比所述第1及第2NMOS存取晶体管的第1扩散层的上端为高，所述第3及第4NMOS驱动晶体管的第4扩散层的下端，比所述第1及第2NMOS存取晶体管的第2扩散层的下端为低。 In addition, in a preferred embodiment of the present invention, the upper ends of the third diffusion layers of the third and fourth NMOS drive transistors are higher than the upper ends of the first diffusion layers of the first and second NMOS access transistors, and the Lower ends of the fourth diffusion layers of the third and fourth NMOS drive transistors are lower than lower ends of the second diffusion layers of the first and second NMOS access transistors. the
此外，本发明的优选实施方式中，在形成所述第3及第4NMOS驱动晶体管的各第3扩散层后，形成所述第1及第2NMOS存取晶体管的各第1扩散层。 Furthermore, in a preferred embodiment of the present invention, after forming the third diffusion layers of the third and fourth NMOS drive transistors, the first diffusion layers of the first and second NMOS access transistors are formed. the
此外，本发明的优选实施方式中，所述第3及第4NMOS驱动晶体管的 第4扩散层、与所述第1及第2NMOS存取晶体管的各第2扩散层是通过离子植入而形成，用以形成所述第3及第4NMOS驱动晶体管的各第4扩散层的离子植入的能量，比用以形成所述第1及第2NMOS存取晶体管的各第2扩散层的离子植入的能量为高。 In addition, in a preferred embodiment of the present invention, the fourth diffusion layers of the third and fourth NMOS drive transistors and the second diffusion layers of the first and second NMOS access transistors are formed by ion implantation, The energy of the ion implantation used to form the respective fourth diffusion layers of the third and fourth NMOS drive transistors is higher than the energy of the ion implantation used to form the respective second diffusion layers of the first and second NMOS access transistors. Energy is high. the
此外，本发明的优选实施方式中，在所述第3及第4NMOS驱动晶体管的第4扩散层包含有磷。 Furthermore, in a preferred embodiment of the present invention, phosphorus is contained in the fourth diffusion layers of the third and fourth NMOS drive transistors. the
（发明效果） (Invention effect)
依据本发明，可提供一种可使驱动晶体管的沟道长度比存取晶体管的沟道长度为短，且以高集成确保动作稳定性的静态型存储单元及其制造方法。 According to the present invention, it is possible to provide a static type memory cell and its manufacturing method in which the channel length of the drive transistor is shorter than that of the access transistor, and operation stability is ensured with high integration. the
附图说明 Description of drawings
图1（a）显示本发明第1及第2实施方式的静态型存储单元的平面图。（b）为（a）的X-X’线的剖面图。 FIG. 1( a ) shows a plan view of static memory cells according to the first and second embodiments of the present invention. (b) is a cross-sectional view of line X-X' in (a). the
图2（a）显示本发明第3及第5实施方式的静态型存储单元的剖面图。（b）显示本发明第4及第6实施方式的静态型存储单元的剖面图。 FIG. 2( a ) shows cross-sectional views of static memory cells according to third and fifth embodiments of the present invention. (b) is a cross-sectional view showing the static memory cells according to the fourth and sixth embodiments of the present invention. the
图3显示本发明第7实施方式的静态型存储单元的剖面图。 FIG. 3 shows a cross-sectional view of a static memory cell according to a seventh embodiment of the present invention. the
图4显示本发明第8实施方式的静态型存储单元的剖面图。 FIG. 4 shows a cross-sectional view of a static memory cell according to an eighth embodiment of the present invention. the
图5显示本发明第9实施方式的静态型存储单元的剖面图。 FIG. 5 shows a cross-sectional view of a static memory cell according to a ninth embodiment of the present invention. the
图6显示本发明第10实施方式的静态型存储单元的剖面图。 FIG. 6 shows a cross-sectional view of a static memory cell according to a tenth embodiment of the present invention. the
图7说明本发明实施方式的静态型存储单元的制造方法的剖面图。 7 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图8说明本发明实施方式的静态型存储单元的制造方法的剖面图。 8 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图9说明本发明实施方式的静态型存储单元的制造方法的剖面图。 9 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图10说明本发明实施方式的静态型存储单元的制造方法的剖面图。 FIG. 10 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图11说明本发明实施方式的静态型存储单元的制造方法的剖面图。 FIG. 11 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图12说明本发明实施方式的静态型存储单元的制造方法的剖面图。 12 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图13说明本发明实施方式的静态型存储单元的制造方法的剖面图。 FIG. 13 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图14说明本发明实施方式的静态型存储单元的制造方法的剖面图。 FIG. 14 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图15说明本发明实施方式的静态型存储单元的制造方法的剖面图。 15 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图16说明本发明实施方式的静态型存储单元的制造方法的剖面图。 16 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图17说明本发明实施方式的静态型存储单元的制造方法的剖面图。 17 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图18说明本发明实施方式的静态型存储单元的制造方法的剖面图。 18 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图19说明本发明实施方式的静态型存储单元的制造方法的剖面图。 19 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图20说明本发明实施方式的静态型存储单元的制造方法的剖面图。 20 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图21说明本发明实施方式的静态型存储单元的制造方法的剖面图。 FIG. 21 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图22说明本发明实施方式的静态型存储单元的制造方法的剖面图。 22 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图23说明本发明实施方式的静态型存储单元的制造方法的剖面图。 23 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图24说明本发明实施方式的静态型存储单元的制造方法的剖面图。 FIG. 24 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图25说明本发明实施方式的静态型存储单元的制造方法的剖面图。 25 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图26说明本发明实施方式的静态型存储单元的制造方法的剖面图。 26 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图27说明本发明实施方式的静态型存储单元的制造方法的剖面图。 27 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图28说明本发明实施方式的静态型存储单元的制造方法的剖面图。 28 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图29说明本发明实施方式的静态型存储单元的制造方法的剖面图。 29 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图30说明本发明实施方式的静态型存储单元的制造方法的剖面图。 30 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图31说明本发明实施方式的静态型存储单元的制造方法的剖面图。 31 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图32说明本发明实施方式的静态型存储单元的制造方法的剖面图。 32 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图33说明本发明实施方式的静态型存储单元的制造方法的剖面图。 33 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图34说明本发明实施方式的静态型存储单元的制造方法的剖面图。 34 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图35说明本发明实施方式的静态型存储单元的制造方法的剖面图。 35 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图36说明本发明实施方式的静态型存储单元的制造方法的剖面图。 36 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图37说明本发明实施方式的静态型存储单元的制造方法的剖面图。 37 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图38说明本发明实施方式的静态型存储单元的制造方法的剖面图。 38 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图39说明本发明实施方式的静态型存储单元的制造方法的剖面图。 39 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图40说明本发明实施方式的静态型存储单元的制造方法的剖面图。 40 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图41说明本发明实施方式的静态型存储单元的制造方法的剖面图。 Fig. 41 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图42说明本发明实施方式的静态型存储单元的制造方法的剖面图。 42 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图43说明本发明实施方式的静态型存储单元的制造方法的剖面图。 43 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图44说明本发明实施方式的静态型存储单元的制造方法的剖面图。 44 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图45说明本发明实施方式的静态型存储单元的制造方法的剖面图。 45 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图46说明本发明实施方式的静态型存储单元的制造方法的剖面图。 Fig. 46 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图47说明本发明实施方式的静态型存储单元的制造方法的剖面图。 47 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图48说明本发明实施方式的静态型存储单元的制造方法的剖面图。 48 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图49说明本发明实施方式的静态型存储单元的制造方法的剖面图。 49 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图50说明本发明实施方式的静态型存储单元的制造方法的剖面图。 FIG. 50 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图51说明本发明实施方式的静态型存储单元的制造方法的剖面图。 Fig. 51 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图52说明本发明实施方式的静态型存储单元的制造方法的剖面图。 Fig. 52 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图53说明本发明实施方式的静态型存储单元的制造方法的剖面图。 53 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图54说明本发明实施方式的静态型存储单元的制造方法的剖面图。 54 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图55说明本发明实施方式的静态型存储单元的制造方法的剖面图。 Fig. 55 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图56说明本发明实施方式的静态型存储单元的制造方法的剖面图。 Fig. 56 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图57说明本发明实施方式的静态型存储单元的制造方法的剖面图。 57 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
图58说明本发明实施方式的静态型存储单元的制造方法的剖面图。 Fig. 58 is a cross-sectional view illustrating a method of manufacturing a static memory cell according to an embodiment of the present invention. the
具体实施方式 Detailed ways
以下，参照附图说明本发明的实施方式。此外，本发明并非由以下所示的实施方式所限定者。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, this invention is not limited by embodiment shown below. the
图1显示本发明第1实施方式的静态型存储单元的平面图及剖面图。第3NMOS驱动晶体管101具备第3扩散层119、柱状半导体层149、及第4扩散层107。在第3NMOS驱动晶体管101的柱状半导体层149、第4扩散层107的一部分及第3扩散层119的一部分的侧壁，隔着栅极绝缘膜113形成有栅极125。
FIG. 1 shows a plan view and a cross-sectional view of a static memory cell according to a first embodiment of the present invention. The third
第1NMOS存取晶体管103具备第1扩散层121、柱状半导体层151、及第2扩散层109。在第1NMOS存取晶体管103的柱状半导体层151、第2扩散层109的一部分及第1扩散层121的一部分的侧壁，隔着栅极绝缘膜115形成有栅极126。
The first
栅极125的栅极高度在第3NMOS驱动晶体管的附近变低，物理栅极长度比栅极126短。形成第1NMOS存取晶体管103的第1扩散层121与第2扩散层109之间的长度，为形成第3NMOS驱动晶体管101的第3扩散层119与第4扩散层107之间的长度的2倍。藉此，驱动晶体管的电流驱动力在未增加面积的情形下可设为存取晶体管的电流驱动力的2倍，且可确保动作稳 定性。
The gate height of the
第1PMOS负载晶体管102具备第5扩散层120、柱状半导体层150、及第6扩散层108。在第1PMOS负载晶体管102的柱状半导体层150、第5扩散层120的一部分及第6扩散层108的一部分的侧壁，隔着栅极绝缘膜114形成有栅极125。
The first
第3NMOS驱动晶体管101与第1PMOS负载晶体管102以栅极125连接。此外，第3扩散层119、第5扩散层120、第1扩散层121以硅化物（图中未示出）连接。在本附图中，为了使第3扩散层119、第5扩散层120、第1扩散层121分别与衬底电性绝缘，虽使用SOI衬底，但只要可电性绝缘即可，例如亦可使用Si衬底，以形成PN接合，并利用PN接合的反偏压状态而形成电性绝缘。
The third
第4NMOS驱动晶体管106具备第3扩散层124、柱状半导体层、及第4扩散层112。在第4NMOS驱动晶体管106的柱状半导体层、第3扩散层124的一部分及第4扩散层112的一部分的侧壁，隔着栅极绝缘膜118形成有栅极128。 The fourth NMOS drive transistor 106 includes a third diffusion layer 124 , a columnar semiconductor layer, and a fourth diffusion layer 112 . A gate 128 is formed on the side walls of the columnar semiconductor layer of the fourth NMOS drive transistor 106 , a part of the third diffusion layer 124 , and a part of the fourth diffusion layer 112 via the gate insulating film 118 . the
第2NMOS存取晶体管104具备第1扩散层122、柱状半导体层、及第2扩散层110。在第2NMOS存取晶体管104的柱状半导体层、第1扩散层122的一部分及第2扩散层110的一部分的侧壁，隔着栅极绝缘膜116形成有栅极127。虽图中未示出，但形成第2NMOS存取晶体管104的第1扩散层122与第2扩散层110之间的长度，为形成第4NMOS驱动晶体管106的第3扩散层124与第4扩散层112之间的长度的2倍。 The second NMOS access transistor 104 includes a first diffusion layer 122 , a columnar semiconductor layer, and a second diffusion layer 110 . A gate 127 is formed on the side walls of the columnar semiconductor layer of the second NMOS access transistor 104 , a part of the first diffusion layer 122 , and a part of the second diffusion layer 110 via the gate insulating film 116 . Although not shown in the figure, the length between the first diffusion layer 122 and the second diffusion layer 110 forming the second NMOS access transistor 104 is equal to the length between the third diffusion layer 124 and the fourth diffusion layer forming the fourth NMOS drive transistor 106. 2 times the length between 112. the
第2PMOS负载晶体管105具备第5扩散层123、柱状半导体层、及第6扩散层111。在第2PMOS负载晶体管105的柱状半导体层、第5扩散层123的一部分及第6扩散层111的一部分的侧壁，隔着栅极绝缘膜117形成有栅极128。 The second PMOS load transistor 105 includes a fifth diffusion layer 123 , a columnar semiconductor layer, and a sixth diffusion layer 111 . A gate 128 is formed on the side walls of the columnar semiconductor layer of the second PMOS load transistor 105 , a part of the fifth diffusion layer 123 , and a part of the sixth diffusion layer 111 via the gate insulating film 117 . the
第4NMOS驱动晶体管106与第2PMOS负载晶体管105以栅极125连接。此外，第1扩散层122、第5扩散层123、第3扩散层124以硅化物（图中未示出）连接。
The fourth NMOS drive transistor 106 is connected to the second PMOS load transistor 105 through a
再者，在本附图中，为了使第1扩散层122、第5扩散层123、第3扩散层124分别与衬底电性绝缘，虽使用SOI衬底，但只要可电性绝缘即可，例 如亦可使用Si衬底，以形成PN接合，并利用PN接合的反偏压状态而形成电性绝缘。 Furthermore, in this drawing, in order to electrically insulate the first diffusion layer 122, the fifth diffusion layer 123, and the third diffusion layer 124 from the substrate respectively, although an SOI substrate is used, as long as it can be electrically insulated , For example, a Si substrate can also be used to form a PN junction, and the reverse bias state of the PN junction can be used to form electrical insulation. the
在栅极125上形成有接触件130，在第1扩散层122、第5扩散层123上形成有接触件137。接触件130、137以金属142连接。在栅极128上形成有接触件139，在第5扩散层120、第1扩散层121上形成有接触件132。接触件139、132以金属144连接。在第6扩散层108上形成有接触件131，在第6扩散层111上形成有接触件138，在接触件131、138连接有金属143，且供给有电源。
A
在第4扩散层107上形成有接触件129，且形成有金属141，且供给有电源。在第4扩散层112上形成有接触件140，且形成有金属148，且供给有电源。在第2扩散层109上形成有接触件133，且形成有金属145，以作为位线。在第2扩散层110上形成有接触件136，且形成有金属210，以作为位线。在栅极126上形成有接触件134，且形成有金属146，以作为字符线。在栅极127上形成有接触件135，且形成有金属147，以作为字符线。
On the
本发明第2实施方式的静态型存储单元的平面图及剖面图与图1相同。在该实施方式中，形成第3NMOS驱动晶体管101的第3扩散层119与第4扩散层107之间的长度，比形成第1PMOS负载晶体管102的第5扩散层120与第6扩散层108之间的长度为短。在SRAM中，PMOS的负载晶体管以最小尺寸形成，且形成为PMOS的负载晶体管的电流驱动力比NMOS的存取晶体管的电流驱动力小。亦即，NMOS的存取晶体管及PMOS的负载晶体管的沟道长度形成为相同。因此，在本发明中，NMOS的驱动晶体管101的沟道长度比PMOS的驱动晶体管102的沟道长度为短。
The plan view and cross-sectional view of the static memory cell according to the second embodiment of the present invention are the same as those in FIG. 1 . In this embodiment, the length between the
图2（a）及（b）显示本发明第3及第4实施方式的静态型存储单元的剖面图。在图2（a）中，形成第1NMOS存取晶体管103的第1扩散层121的上端与第2扩散层109的下端之间的长度，设为形成第3NMOS驱动晶体管101的第3扩散层119的上端与第4扩散层107的下端之间的长度的1.3倍。在图2（b）中，形成第1NMOS存取晶体管103的第1扩散层121的上端与第2扩散层109的下端之间的长度，设为形成第3NMOS驱动晶体管101的第3扩散层119的上端与第4扩散层107的下端之间的长度的3倍。将驱动晶体管的沟道长度设为越短，越能确保动作稳定性，但若一方变短时，则 会产生短沟道效应，而无法截断晶体管。因此，虽可依所要的要求适当选择，但就一例而言，若设为上述的1.3倍至3倍之间的范围，则可谋求动作稳定性的确保及短沟道效应的抑制。
2( a ) and ( b ) show cross-sectional views of static memory cells according to third and fourth embodiments of the present invention. In FIG. 2( a ), the length between the upper end of the
本发明第5及第6实施方式的静态型存储单元的平面图及剖面图与图2（a）及（b）相同。在第5实施方式中，形成第1PMOS负载晶体管102的第5扩散层120的上端与第6扩散层108的下端之间的长度，设为形成第3NMOS驱动晶体管101的第3扩散层119的上端与第4扩散层107的下端之间的长度的1.3倍。在第6实施方式中，形成第1PMOS负载晶体管102的第5扩散层120的上端与第6扩散层108的下端之间的长度，设为形成第3NMOS驱动晶体管101的第3扩散层119的上端与第4扩散层107的下端之间的长度的3倍。将驱动晶体管的沟道长度设为越短，越能确保动作稳定性，但若一方变短时，则会产生短沟道效应，而无法截断晶体管。因此，虽可依所要的要求适当选择，但就一例而言，若设为上述的1.3倍至3倍之间的范围，则可谋求动作稳定性的确保及短沟道效应的抑制。
Plan views and cross-sectional views of static memory cells according to fifth and sixth embodiments of the present invention are the same as those in FIGS. 2( a ) and ( b ). In the fifth embodiment, the length between the upper end of the
图3显示本发明第7实施方式的静态型存储单元的剖面图。将栅极125、126的物理栅极长度设为相同者。由于栅极125、126的从下端至上端的长度（亦即物理栅极长度）为相同，因此可使用所述的SGT的制造方法，该方法在形成柱状半导体层后，堆积栅极导电膜，并使之平坦化，进行回蚀刻而作成所希望的长度。
FIG. 3 shows a cross-sectional view of a static memory cell according to a seventh embodiment of the present invention. The physical gate lengths of the
通常，使沟道长度变短者如图1所示，使物理栅极长度变短。若使物理栅极长度变短，则栅极电容会变小。若栅极电容变小，则会发生软性错误(soft.error)，而无法确保动作稳定性。另一方面，图3仅使驱动晶体管的电流驱动力变短，物理栅极长度则相同，因此虽将驱动晶体管的沟道长度设为2倍，栅极电容亦不会变小。亦即，驱动晶体管的电流驱动力可设为存取晶体管的电流驱动力的二倍，以确保动作稳定性，且避免软性错误，而可确保动作稳定性。 Generally, shortening the channel length shortens the physical gate length as shown in FIG. 1 . If the physical gate length is shortened, the gate capacitance will be reduced. If the gate capacitance becomes small, a soft error (soft.error) will occur, and operation stability cannot be ensured. On the other hand, in FIG. 3, only the current driving force of the driving transistor is shortened, and the physical gate length is the same. Therefore, even if the channel length of the driving transistor is doubled, the gate capacitance will not be reduced. That is, the current driving force of the driving transistor can be set to twice that of the access transistor to ensure operation stability, avoid soft errors, and ensure operation stability. the
图4显示本发明第8实施方式的静态型存储单元的剖面图。在图4的实施方式中，物理栅极长度相同，第3NMOS驱动晶体管101的第3扩散层119的上端，位于比第1NMOS存取晶体管103的第1扩散层121的上端更高的位置。藉此，第3NMOS驱动晶体管101可增大栅极125与第3扩散层119 之间的重叠电容。当第3NMOS驱动晶体管101截断时，栅极125与第3扩散层119间的重叠电容成为寄生在存储节点的寄生电容，由于重叠电容较大，因此可进一步避免软性错误，而可确保动作稳定性。
FIG. 4 shows a cross-sectional view of a static memory cell according to an eighth embodiment of the present invention. In the embodiment shown in FIG. 4 , the physical gate lengths are the same, and the upper end of the
图5显示本发明第9实施方式的静态型存储单元的剖面图。与图4不同的是，第3NMOS驱动晶体管101的第3扩散层119的上端、与第1NMOS存取晶体管103的第1扩散层121的上端的高度为相同，第3NMOS驱动晶体管101的第4扩散层107的下端，比第1NMOS存取晶体管103的第2扩散层109的下端为低。
FIG. 5 shows a cross-sectional view of a static memory cell according to a ninth embodiment of the present invention. The difference from FIG. 4 is that the height of the upper end of the
即使在第5实施方式中，由于仅使驱动晶体管的沟道长度变短，物理栅极长度则相同，因此虽将驱动晶体管的电流驱动力设为2倍，栅极电容亦不会变小，因此驱动晶体管的电流驱动力可设为存取晶体管的电流驱动力的二倍，以确保动作稳定性，且复避免软性错误，而可确保动作稳定性。然而，并没有如图4的更进一步的优点，即当第3NMOS驱动晶体管101截断时，栅极125与第3扩散层119间的重叠电容成为寄生在存储节点的寄生电容，由于重叠电容较大，因此可进一步避免软性错误，而可确保动作稳定性。然而，当将存储节点设计成来到晶体管的上方时，具有更加避免软性错误的优点。但是，之后会在制造方法进行说明，为了制作图4的形状，在第3扩散层用的离子植入后，需要比较长的热处理。以离子植入形成第4扩散层107时，通过使用提高植入的能量、或扩散长度较长的磷，即可使第3NMOS驱动晶体管101的第4扩散层107的下端，比第1NMOS存取晶体管103的第2扩散层109的下端为低。亦即，可使热处理比图4为少。
Even in the fifth embodiment, since only the channel length of the driving transistor is shortened and the physical gate length is kept the same, even if the current driving force of the driving transistor is doubled, the gate capacitance does not become smaller. Therefore, the current driving force of the driving transistor can be set as twice that of the accessing transistor to ensure operation stability and avoid soft errors to ensure operation stability. However, there is no further advantage as shown in Figure 4, that is, when the third
图6显示本发明第10实施方式的静态型存储单元的剖面图。与图4不同的是，第3NMOS驱动晶体管101的第3扩散层119的上端，比第1NMOS存取晶体管103的第1扩散层121的上端为高，第3NMOS驱动晶体管101的第4扩散层107的下端，比第1NMOS存取晶体管103的第2扩散层109的下端为低。
FIG. 6 shows a cross-sectional view of a static memory cell according to a tenth embodiment of the present invention. 4 is that the upper end of the
即使在图6的实施方式中，由于使驱动晶体管的沟道长度比存取晶体管的沟道长度短，因此可确保动作稳定性。再者，亦可作到图4的优点的避免软性错误。由于第3扩散层119的扩散长度较短，因此与制作图4的形状相比较，能以较少的热处理来形成。当以离子植入形成第4扩散层107时，通 过使用提高植入的能量、或扩散长度较长的磷，即可使第3NMOS驱动晶体管101的第4扩散层107的下端，比第1NMOS存取晶体管103的第2扩散层109的下端为低。亦即，可使热处理比图4为少，且亦可避免软性错误。然而，与图4的形状及图5的形状相比较，制造步骤会增加。虽显示以上各式各样的形态，但依所要的要求适当地选择即可。
Also in the embodiment of FIG. 6 , since the channel length of the driving transistor is made shorter than that of the access transistor, operational stability can be ensured. Furthermore, the advantage of FIG. 4 can also be achieved to avoid soft errors. Since the diffusion length of the
以下，参照图7至图32说明用以形成本发明实施方式的图4的静态型存储单元构造的制造步骤的一例。 Hereinafter, an example of manufacturing steps for forming the static memory cell structure of FIG. 4 according to the embodiment of the present invention will be described with reference to FIGS. 7 to 32 . the
图7显示在硅152上形成有氧化膜157，并在氧化膜上形成平面状硅158，且形成分别在上部具有氮化膜硬掩模(hard mask)162、163、164的柱状硅159、160、161的状态。
7 shows that an
从图7的状态通过堆积氧化膜，并进行回蚀刻，如图8所示形成氧化膜侧壁165、166、167。然后，形成用以形成第3扩散层119的抗蚀剂(resist)168。
From the state of FIG. 7 , by depositing an oxide film and performing etching back, oxide
在此状态下，如图9所示植入砷，以形成第3扩散层119。
In this state, arsenic is implanted as shown in FIG. 9 to form a
然后，如图10所示，剥离抗蚀剂168，并剥离氧化膜侧壁165、166、167，以进行第一次的热处理。 Then, as shown in FIG. 10 , the resist 168 is stripped off, and the oxide film sidewalls 165 , 166 , and 167 are stripped off to perform the first heat treatment. the
再者，如图11所示，形成氧化膜侧壁169、170、171。之后，形成用以形成第1扩散层121的抗蚀剂172。
Furthermore, as shown in FIG. 11 , oxide
在该状态下，如图12所示，植入砷而形成第1扩散层121。
In this state, as shown in FIG. 12 , arsenic is implanted to form the
然后，如图13所示，剥离抗蚀剂172，并剥离氧化膜侧壁169、170、171，以进行第二次的热处理。第3扩散层119由于接受二次的热处理，因此第3扩散层119的上端比第1扩散层121的上端为高。藉此，驱动晶体管的沟道长度比存取晶体管的沟道长度为短，而可确保动作稳定性。
Then, as shown in FIG. 13 , the resist 172 is stripped off, and the oxide film sidewalls 169 , 170 , and 171 are stripped off to perform a second heat treatment. Since the
接着，如图14所示，形成氧化膜侧壁173、174、175。然后，形成用以形成第5扩散层120的抗蚀剂176。
Next, as shown in FIG. 14 , oxide
在该状态下，如图15所示，植入硼而形成第5扩散层120。
In this state, as shown in FIG. 15 , boron is implanted to form the
从该状态，如图16所示，剥离抗蚀剂176，并剥离氧化膜侧壁173、174、175，以进行热处理。
From this state, as shown in FIG. 16, the resist 176 is peeled off, and the oxide
然后，如图17所示，形成形成组件分离用的抗蚀剂，进行硅的蚀刻，以剥离抗蚀剂。 Then, as shown in FIG. 17, a resist is formed to form a device isolation, and silicon is etched to remove the resist. the
接着，如图18所示，以埋设组件间的方式形成氧化膜153，然后堆积常 压CVD氧化膜，并进行回蚀刻，藉此形成氧化膜177。此时，氧化膜178、179、180会残留在氮化膜硬掩模162、163、164上。
Next, as shown in FIG. 18, an
再者，如图19所示，形成栅极绝缘膜113、114、115，堆积栅极导电膜181，并使之平坦化。氧化膜178、179、180露出后，蚀刻氧化膜178、179、180，且复进行平坦化，将氮化膜硬掩模作为挡止件。栅极绝缘膜为氧化膜、氮化膜、氧氮化膜、高电介质膜中的一种。栅极导电膜多晶硅、金属与多晶硅的积层膜、金属膜中的一种。
Furthermore, as shown in FIG. 19,
接着，如图20所示，对栅极绝缘膜181进行回蚀刻，而获得所希望的物理栅极长度。结果，在全部的晶体管中物理栅极长度为一定。
Next, as shown in FIG. 20, the
然后，堆积氧化膜，并堆积氮化膜，进行蚀刻，而残存为侧壁状，如图21所示，形成由氧化膜184、氮化膜185所构成的绝缘膜侧壁、由氧化膜186、氮化膜187所构成的绝缘膜侧壁、及由氧化膜188、氮化膜189所构成的绝缘膜侧壁。
Then, an oxide film is deposited, a nitride film is deposited, and etching is performed to leave a sidewall shape. As shown in FIG. , the insulating film sidewall formed by the
接着，如图22所示，形成用以对栅极进行蚀刻的抗蚀剂182、183。 Next, as shown in FIG. 22 , resists 182 and 183 for etching the gate are formed. the
然后，如图23所示，对栅极导电膜181进行蚀刻，形成栅极125、126，对氧化膜177进行蚀刻，形成氧化膜154、155，并剥离抗蚀剂182、183。
Then, as shown in FIG. 23 , the gate
接着，如图24所示，对由氧化膜184、氮化膜185所构成的绝缘膜侧壁、由氧化膜186、氮化膜187所构成的绝缘膜侧壁、及由氧化膜188、氮化膜189所构成的绝缘膜侧壁进行蚀刻。
Then, as shown in FIG. The sidewall of the insulating film made of the
再者，堆积氮化膜，进行蚀刻，而残存为侧壁状，如图25所示，形成氮化膜侧壁190、191、192、193、194。 Further, a nitride film is deposited and etched to remain in the form of sidewalls. As shown in FIG. 25 , nitride film sidewalls 190 , 191 , 192 , 193 , and 194 are formed. the
接着，如图26所示，形成用以形成第2扩散层107、109的抗蚀剂195。 Next, as shown in FIG. 26, a resist 195 for forming the second diffusion layers 107 and 109 is formed. the
然后，如图27所示，离子植入砷而形成第4扩散层107、第2扩散层109。
Then, as shown in FIG. 27 , arsenic is ion-implanted to form a
然后，如图28所示，剥离抗蚀剂195，以进行热处理。 Then, as shown in FIG. 28, the resist 195 is peeled off for heat treatment. the
如图29所示，形成用以形成第6扩散层108的抗蚀剂196。
As shown in FIG. 29, a resist 196 for forming the
接着，如图30所示，离子植入硼而形成第6扩散层108。
Next, as shown in FIG. 30 , boron is ion-implanted to form a
然后，如图31所示，剥离抗蚀剂196，以进行热处理。 Then, as shown in FIG. 31, the resist 196 is peeled off for heat treatment. the
然后，如图32所示，堆积层间膜156，以形成接触件129、130、131、132、133、134，并形成金属141、142、143、144、145、146。在形成层间膜之前，亦可在第3扩散层119、第5扩散层120、第1扩散层121上形成硅 化物。此外，亦可在第4扩散层107、第6扩散层108、第2扩散层109上形成硅化物。
Then, as shown in FIG. 32 , an
由以上得知，通过使驱动晶体管的沟道长度比存取晶体管的沟道长度为短，而确保动作稳定性。再者，通过将驱动晶体管的物理栅极长度与存取晶体管的物理栅极长度设为相同，可使用所述SGT的制造方法。亦即，驱动晶体管的电流驱动力可设为存取晶体管的电流驱动力的二倍，以确保动作稳定性，且由于仅使驱动晶体管的沟道长度变短，物理栅极长度相同，因此尽管将驱动晶体管的电流驱动力设为二倍，栅极电容亦不会变小，因此可避免软性错误，且确保动作稳定性。再者，显示一种用以形成以下构造的制造方法，该构造为：驱动晶体管的第3扩散层的上端设为位于比存取晶体管的第1扩散层的上端更高的位置，因此，驱动晶体管可将栅极与第3扩散层间的重叠电容增大，且复可避免软性错误，且确保动作稳定性。 From the above, it can be seen that the operation stability can be ensured by making the channel length of the driving transistor shorter than that of the access transistor. Furthermore, by making the physical gate length of the drive transistor the same as the physical gate length of the access transistor, the above-described SGT manufacturing method can be used. That is, the current driving force of the driving transistor can be set to twice the current driving force of the access transistor to ensure operation stability, and since only the channel length of the driving transistor is shortened, the physical gate length is the same, so although By doubling the current driving force of the drive transistor, the gate capacitance will not be reduced, so soft errors can be avoided and operation stability can be ensured. Furthermore, a manufacturing method for forming a structure in which the upper end of the third diffusion layer of the drive transistor is positioned higher than the upper end of the first diffusion layer of the access transistor is shown, so that the driving The transistor can increase the overlap capacitance between the gate and the third diffusion layer, avoid soft errors, and ensure operation stability. the
以下，参照图33至图58说明用以形成本发明实施方式的图5的静态型存储单元构造的制造步骤的一例。 Hereinafter, an example of manufacturing steps for forming the static memory cell structure of FIG. 5 according to the embodiment of the present invention will be described with reference to FIGS. 33 to 58 . the
图33为以下构造：在硅152上形成有氧化膜157，且在氧化膜157上形成平面状的硅158，且形成有分别在上部具有氮化膜硬掩模162、163、164的柱状硅159、160、161。
33 shows a structure in which an
接着，如图34所示，堆积氧化膜，并进行回蚀刻，而形成氧化膜侧壁169、170、171。然后，形成用以形成第3扩散层119、第1扩散层121的抗蚀剂172。
Next, as shown in FIG. 34 , an oxide film is deposited and etched back to form oxide
再者，如图35所示，植入砷而形成第3扩散层119、第1扩散层121。
Furthermore, as shown in FIG. 35 , arsenic is implanted to form the
然后，如图36所示，剥离抗蚀剂172，并剥离氧化膜侧壁169、170、171，以进行热处理。
Then, as shown in FIG. 36, the resist 172 is peeled off, and the oxide
接着，如图37所示，形成氧化膜侧壁173、174、175。之后，形成用以形成第5扩散层120的抗蚀剂176。
Next, as shown in FIG. 37, oxide
然后，如图38所示，植入硼而形成第5扩散层120。
Then, as shown in FIG. 38 , boron is implanted to form the
然后，如图39所示，剥离抗蚀剂176，并剥离氧化膜侧壁173、174、175，以进行热处理。
Then, as shown in FIG. 39, the resist 176 is peeled off, and the oxide
然后，如图40所示，形成组件分离形成用的抗蚀剂，进行硅的蚀刻，以剥离抗蚀剂。 Then, as shown in FIG. 40 , a resist for component isolation formation is formed, and silicon is etched to remove the resist. the
接着，如图41所示，以埋设组件间的方式形成氧化膜153，然后堆积常压CVD氧化膜，并进行回蚀刻，藉此形成氧化膜177。此时，氧化膜178、179、180会残留在氮化膜硬掩模162、163、164上。
Next, as shown in FIG. 41 , an
再者，如图42所示，形成栅极绝缘膜113、114、115，堆积栅极导电膜181，并使之平坦化。氧化膜178、179、180露出后，蚀刻氧化膜178、179、180，且进行平坦化，将氮化膜硬掩模作为挡止件。栅极绝缘膜为氧化膜、氮化膜、氧氮化膜、高电介质膜中的一种。栅极导电膜为多晶硅、金属与多晶硅的积层膜、金属膜中的一种。
Furthermore, as shown in FIG. 42,
接着，如图43所示，对栅极绝缘膜181进行回蚀刻，而获得所希望的物理栅极长度。结果，在全部的晶体管中物理栅极长度为一定。
Next, as shown in FIG. 43, the
然后，如图44所示，堆积氧化膜，并堆积氮化膜，进行蚀刻，而残存为侧壁状，以形成由氧化膜184、氮化膜185所构成的绝缘膜侧壁、由氧化膜186、氮化膜187所构成的绝缘膜侧壁、及由氧化膜188、氮化膜189所构成的绝缘膜侧壁。
Then, as shown in FIG. 44, an oxide film is deposited, a nitride film is deposited, and etching is performed to leave a sidewall shape to form an insulating film sidewall composed of an
接着，如图45所示，形成用以对栅极进行蚀刻的抗蚀剂182、183。 Next, as shown in FIG. 45 , resists 182 and 183 for etching the gate are formed. the
然后，如图46所示，对栅极导电膜181进行蚀刻，形成栅极125、126，对氧化膜177进行蚀刻，形成氧化膜154、155，并剥离抗蚀剂182、183。
Then, as shown in FIG. 46 , the gate
接着，如图47所示，对由氧化膜184、氮化膜185所构成的绝缘膜侧壁、由氧化膜186、氮化膜187所构成的绝缘膜侧壁、及由氧化膜188、氮化膜189所构成的绝缘膜侧壁进行蚀刻。
Next, as shown in FIG. The sidewall of the insulating film made of the
再者，如图48所示，堆积氮化膜，进行蚀刻，而残存为侧壁状，以形成氮化膜侧壁190、191、192、193、194。
Furthermore, as shown in FIG. 48, a nitride film is deposited, etched, and left in the form of side walls to form nitride
接着，如图49所示，形成用以形成第4扩散层107的抗蚀剂201。
Next, as shown in FIG. 49, a resist 201 for forming the
然后，如图50所示，离子植入砷或磷而形成第4扩散层107。使用砷时只要增大离子植入的能量即可。此外，通过使用扩散长度较长的磷，即可使第3NMOS驱动晶体管101的第4扩散层107的下端，比第1NMOS存取晶体管103的第2扩散层109的下端为低。可适当地选择使用砷，或使用磷。
Then, as shown in FIG. 50, arsenic or phosphorus is ion-implanted to form a
然后，如图51所示，剥离抗蚀剂201，以进行热处理。 Then, as shown in FIG. 51, the resist 201 is peeled off for heat treatment. the
如图52所示，形成用以形成第2扩散层109的抗蚀剂202。
As shown in FIG. 52, a resist 202 for forming the
接着，如图53所示，离子植入砷而形成第2扩散层109。
Next, as shown in FIG. 53 , arsenic is ion-implanted to form a
然后，如图54所示，剥离抗蚀剂202，以进行热处理。 Then, as shown in FIG. 54, the resist 202 is peeled off for heat treatment. the
然后，如图55所示，形成用以形成第6扩散层108的抗蚀剂203。
Then, as shown in FIG. 55, a resist 203 for forming the
接着，如图56所示，离子植入硼而形成第2扩散层108。
Next, as shown in FIG. 56 , boron is ion-implanted to form a
然后，如图57所示，剥离抗蚀剂203，以进行热处理。 Then, as shown in FIG. 57, the resist 203 is peeled off to perform heat treatment. the
此外，如图58所示，堆积层间膜156，以形成接触件129、130、131、132、133、134，并形成金属141、142、143、144、145、146。在形成层间膜之前，亦可在第3扩散层119、第5扩散层120、第1扩散层121上形成硅化物。此外，亦可在第4扩散层107、第6扩散层108、第2扩散层109上形成硅化物。
Furthermore, as shown in FIG. 58 , an
如以上所述，通过使驱动晶体管的沟道长度比存取晶体管的沟道长度为短，即可确保动作稳定性，使热处理比图1更少。 As described above, by making the channel length of the drive transistor shorter than the channel length of the access transistor, operation stability can be ensured, and heat treatment can be reduced compared to FIG. 1 . the
以上，虽显示用以形成图4及图5的构造的制造方法，但针对图6所示的构造，可通过组合形成图4的第3扩散层119、第1扩散层121的方法与形成图5的第4扩散层107、第2扩散层109的方法而形成。
Above, although the manufacturing method for forming the structure of FIG. 4 and FIG. 5 was shown, for the structure shown in FIG. 6, the method of forming the
此外，本发明可在不脱离本发明的广义的精神及范围的情形下进行各式各样的实施方式及变形。此外，上述的实施方式为用以说明本发明的一实施例，并非由上述的实施方式来限定本发明的技术范围。 In addition, various embodiments and modifications can be made to the present invention without departing from the broad spirit and scope of the present invention. In addition, the above-mentioned embodiment is an example for describing the present invention, and the technical scope of the present invention is not limited by the above-mentioned embodiment. the
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| US10424663B2 (en) * | 2017-05-23 | 2019-09-24 | International Business Machines Corporation | Super long channel device within VFET architecture |
| JP6328832B2 (en) * | 2017-07-05 | 2018-05-23 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． | Semiconductor device manufacturing method and semiconductor device |
| KR102210793B1 (en) | 2017-11-01 | 2021-02-03 | 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드 | Columnar semiconductor device and its manufacturing method |
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| JP4006566B2 (en) * | 2001-02-07 | 2007-11-14 | セイコーエプソン株式会社 | Semiconductor device, memory system and electronic device |
| WO2009095998A1 (en) * | 2008-01-29 | 2009-08-06 | Unisantis Electronics (Japan) Ltd. | Semiconductor storage device |
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| US20100219483A1 (en) * | 2008-01-29 | 2010-09-02 | Fujio Masuoka | Semiconductor storage device |
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