CN102710242A - On-chip power-on reset detection circuit applied to high-frequency phase locked loop (PLL) - Google Patents
On-chip power-on reset detection circuit applied to high-frequency phase locked loop (PLL) Download PDFInfo
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- CN102710242A CN102710242A CN2012101987543A CN201210198754A CN102710242A CN 102710242 A CN102710242 A CN 102710242A CN 2012101987543 A CN2012101987543 A CN 2012101987543A CN 201210198754 A CN201210198754 A CN 201210198754A CN 102710242 A CN102710242 A CN 102710242A
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Abstract
本发明提出一种适用于但不限定于高频PLL的片内上电复位检测电路。上电复位检测电路在电源电压未升高到设定值时，输出一直为低电平；当电源电压升高到设定值时，输出置为高电平信号，使电路开始正常工作。当电源电压达到正常电压值时，输出低电平，给出一个上电复位脉冲信号，从而实现了上电复位检测。具有易于实现，静态功耗低的特点。对于避免对电源电压上电敏感的高频电路的简便点，提供了新的解决方案。
The invention proposes an on-chip power-on reset detection circuit suitable for but not limited to a high-frequency PLL. When the power-on reset detection circuit does not rise to the set value, the output is always low level; when the power supply voltage rises to the set value, the output is set to a high level signal, so that the circuit starts to work normally. When the power supply voltage reaches the normal voltage value, it outputs a low level and gives a power-on reset pulse signal, thereby realizing power-on reset detection. It has the characteristics of easy implementation and low static power consumption. A new solution is provided for the convenience of avoiding high-frequency circuits that are sensitive to supply voltage power-up.
Description
Technical field
The invention belongs to technical field of integrated circuits, a testing circuit is replied in concrete design by cable, is particularly useful for electrification reset testing circuit in the sheet in the high frequency PLL circuit.
Background technology
The electrification reset testing circuit is highly suitable for the mixed signal chip of CMOS technology in the sheet.When chip system was powered up, owing to electric capacity reason on the plate, the supply voltage in the chip can slowly rise to normal working voltage from zero.But arbitrary metal-oxide-semiconductor for the cmos device in the chip; Work and only need a voltage that surpasses the pipe threshold value; If supply voltage does not rise to the normal working voltage of chip system requirement; Circuit is started working be easy to cause the error of digital circuit or memory cell, cause system's run-time error; For high frequency PLL circuit; If in power up; Charge pump discharges and recharges electric capacity because phase frequency detector produces wrong output signal and can voltage controlled oscillator be controlled voltage signal and be changed to a fixed potential; Be easy to cause whole cycle of phase-locked loop losing lock like this, can't produce normal clock.So it is quite important for chip to study the interior electrification reset testing circuit of a kind of new sheet.
Summary of the invention
The present invention is for solving the problems of the technologies described above, and proposes a kind ofly to be applicable to but to be not limited to electrification reset testing circuit in the sheet of high frequency PLL.The electrification reset testing circuit is not when supply voltage is elevated to set point, and output is low level always; When supply voltage was elevated to set point, output was changed to high level signal, makes circuit begin operate as normal.When supply voltage reached the normal voltage value, output low level provided an electrification reset pulse signal.Open Enable Pin by the electrification reset pulse signal, let the interior phase-locked loop of chip start working.When supply voltage reached the normal voltage value, output low level provided an electrification reset pulse signal, thereby has realized the electrification reset detection.Have and be easy to realize the characteristics that quiescent dissipation is low.To the power on easy point of responsive high-frequency circuit of supply voltage new solution is provided for avoiding.
The technical solution adopted for the present invention to solve the technical problems is: propose a kind ofly to be applicable to but to be not limited to electrification reset testing circuit in the sheet of high frequency PLL; It is characterized in that: comprise power on delay circuit and electrification reset testing circuit, the electrification reset testing circuit is not when supply voltage is elevated to set point, and output is low level always; When supply voltage is elevated to set point; Output is changed to high level signal, makes circuit begin operate as normal, when supply voltage reaches the normal voltage value; Output low level provides an electrification reset pulse signal.The electrification reset testing circuit is not when supply voltage is elevated to set point, and output is low level always; When supply voltage was elevated to set point, output was changed to high level signal, makes circuit begin operate as normal.When supply voltage reached the normal voltage value, output low level provided an electrification reset pulse signal.Open Enable Pin by the electrification reset pulse signal, let the interior phase-locked loop of chip start working.When supply voltage reached the normal voltage value, output low level provided an electrification reset pulse signal, thereby has realized the electrification reset detection.Have and be easy to realize the characteristics that quiescent dissipation is low.For avoiding to the power on easy point of responsive high-frequency circuit of supply voltage.
It also is when the sheet external power begins to power on; Power vd D+ is charged by identical pin pin with VDD-simultaneously in the sheet; Produce two different voltage IN+ of the speed that powers on and IN-through the delay circuit that powers on, IN+, the IN-current potential is different can produce the crosspoint because the speed that powers on is different.
It also is to adopt resistance, electric capacity and PMOS pipe to form delay circuit, adds the PMOS pipe and strengthens the time-delay that powers on, and under equal time delay condition, can reduce resistance and capacitance.
It also is to adopt the mode of multi-stage cascade, uses small size resistance capacitance value to realize the delay effect of big resistance capacitance.
It also is to power on when finishing, and IN-voltage is fixed as one and is lower than supply voltage value, and IN+ voltage is fixed as supply voltage.
It is that also POR_OUT is output as low level when the IN-current potential is higher than the IN+ current potential; When the IN+ current potential was higher than the IN-current potential, POR_OUT was output as high level; After voltage charging in the sheet was accomplished, the IN+ current potential equaled supply voltage in the sheet, and POR_OUT is output as low level, accomplished electrification reset and detected.
It also is to adopt little current comparator, inverter, single-ended common-source stage amplifier to form the electrification reset testing circuit, and powering on, circuit is in low power consumpting state when finishing.
It is that also along with the change in voltage that powers on, the comparator input pipe is in different conducting states, electro-detection reset effect in the realization.
It is that also the time-delay meeting that the delay circuit that powers on produces is different owing to the deviation in different temperatures, voltage and manufacturing generation, but owing to the gain of comparator is enough big, the electrification reset testing circuit still can be realized electro-detection and reset function.
Compared with prior art, the present invention has following beneficial effect:
(1) uses the high-gain comparator, guarantee when chip power does not reach requirement voltage, the zero setting always of output signal.
(2) the electrification reset testing circuit that uses can be through being provided with input pipe different working district, the back output level zero setting that realizes powering on fully, and quiescent dissipation is very little.
(3) avoid for the easy point of responsive high-frequency circuit that supply voltage is powered on, new solution is provided.
Description of drawings
Fig. 1 is the delay circuit sketch map that powers on of the present invention.
Fig. 2 is an electrification reset testing circuit sketch map of the present invention.
Fig. 3 is to use electrification reset testing circuit structural representation block diagram in the sheet of a kind of high frequency PLL that the present invention uses.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further specified.
Be applicable to but be not limited to electrification reset testing circuit in the sheet of high frequency PLL that it is characterized in that: comprise power on delay circuit and electrification reset testing circuit, the electrification reset testing circuit is not when supply voltage is elevated to set point; Output is low level always, and when supply voltage was elevated to set point, output was changed to high level signal; Make circuit begin operate as normal; When supply voltage reached the normal voltage value, output low level provided an electrification reset pulse signal.The electrification reset testing circuit is not when supply voltage is elevated to set point, and output is low level always; When supply voltage was elevated to set point, output was changed to high level signal, makes circuit begin operate as normal.When supply voltage reached the normal voltage value, output low level provided an electrification reset pulse signal.Open Enable Pin by the electrification reset pulse signal, let the interior phase-locked loop of chip start working.When supply voltage reached the normal voltage value, output low level provided an electrification reset pulse signal, thereby has realized the electrification reset detection.
It also is when the sheet external power begins to power on; Power vd D+ is charged by identical pin pin with VDD-simultaneously in the sheet; Produce two different voltage IN+ of the speed that powers on and IN-through the delay circuit that powers on, IN+, the IN-current potential is different can produce the crosspoint because the speed that powers on is different.
It also is to adopt resistance, electric capacity and PMOS pipe to form delay circuit, adds the PMOS pipe and strengthens the time-delay that powers on, and under equal time delay condition, can reduce resistance and capacitance.
It also is to adopt the mode of multi-stage cascade, uses small size resistance capacitance value to realize the delay effect of big resistance capacitance.
It also is to power on when finishing, and IN-voltage is fixed as one and is lower than supply voltage value, and IN+ voltage is fixed as supply voltage.
It is that also POR_OUT is output as low level when the IN-current potential is higher than the IN+ current potential; When the IN+ current potential was higher than the IN-current potential, POR_OUT was output as high level; After voltage charging in the sheet was accomplished, the IN+ current potential equaled supply voltage in the sheet, and POR_OUT is output as low level, accomplished electrification reset and detected.
It also is to adopt little current comparator, inverter, single-ended common-source stage amplifier to form the electrification reset testing circuit, and powering on, circuit is in low power consumpting state when finishing.
It is that also along with the change in voltage that powers on, the comparator input pipe is in different conducting states, electro-detection reset effect in the realization.
It is that also the time-delay meeting that the delay circuit that powers on produces is different owing to the deviation in different temperatures, voltage and manufacturing generation, but owing to the gain of comparator is enough big, the electrification reset testing circuit still can be realized electro-detection and reset function.
Fig. 1 is the delay circuit sketch map that powers on of the present invention, and is as shown in Figure 1: comprise PMOS pipe M1, M2, resistance R 1, R2, R3, R4, capacitor C 1, C2; Electrification reset testing circuit, Fig. 2 are electrification reset testing circuit sketch map of the present invention, and be as shown in Figure 2: comprise NMOS pipe M5, M6, M7, M9, M10, PMOS pipe M1, M2, M3, M4, M8, resistance R 1.
Wherein: PMOS pipe M1 shown in Figure 1, M2, resistance R 3, R4, capacitor C 1, C2 constitute the delay circuit that powers on; When the sheet external power begins to power on; Power vd D+ is charged by identical pin pin with VDD-simultaneously in the sheet, and delay circuit produces power on speed different two voltage IN+, IN-through powering on; IN+, IN-current potential difference can produce the crosspoint because the speed that powers on is different.
NMOS pipe M5 shown in Figure 2, M6, M7, M9, M10, PMOS pipe M1, M2, M3, M4, M8, resistance R 1 constitutes the electrification reset testing circuit.When the IN-current potential was higher than the IN+ current potential, POR_OUT was output as low level; When the IN+ current potential was higher than the IN-current potential, POR_OUT was output as high level; After voltage charging in the sheet was accomplished, the IN+ current potential equaled supply voltage in the sheet, and POR_OUT is output as low level.The completion electrification reset detects.
As shown in Figure 1, PMOS pipe M1, M2, resistance R 3, R4, capacitor C 1, C2 constitute the delay circuit that powers on, and when the sheet external power began to power on, power vd D+ was charged by identical pin pin with VDD-simultaneously in the sheet.Because power supply is very low in the chip, VDD-does not have electric current to pass through resistance R 4, and the grid of M2 is in electronegative potential conducting always, and VDD-forms path with ground; Make the interior power supply electrifying speed of sheet be lower than VDD+, along with supply voltage continues to raise, A point current potential is near VDD-voltage; Because A point current potential is very low, does not have electric current to pass through resistance R 3, the grid of M1 is in electronegative potential conducting always; The A point forms path with ground, and the A point speed that powers on is reduced, and the IN+ point is equivalent to VDD-by the electrifying condition of delaying time.By the IN-of the direct dividing potential drop of resistance, because there is not the relation of time-delay, the speed that powers on is identical with VDD+, and still combined potential is lower than the IN+ point.
NMOS pipe M5 as shown in Figure 2, M6, M7, M9, M10, PMOS pipe M1, M2, M3, M4, M8, resistance R 1 constitutes the electrification reset testing circuit.Wherein M1, M2, M3, M4, M5, M6, M7 constitute comparator, and M3, M4 cross-couplings form the cascodes load respectively with M1, M2.M3 grid and M6 drain electrode is connected, is given to the inverter that M8, M9 form as output, and inverter output connects the single-ended common-source stage amplifier of being made up of M10 and R1, exports the electrification reset detection signal.
IN+ that is produced by the delay circuit that powers on and the IN-speed one fast one that powers on is slow, and final level is one high and one low.When the IN-current potential was higher than the IN+ current potential, supply voltage was given to the drain electrode of NMOS pipe M5, M6 after PMOS manages M1, M3 and PMOS pipe M2, M4 dividing potential drop, and greater than IN+ and IN-; NMOS pipe M5, M6 are in the saturation region at this moment, because PMOS manages M3, M4 cross-couplings, the voltage of IN-and IN+ is done difference compare; Make comparator be output as zero; Height is put in inverter output, and the common-source stage amplifier amplifies the electric current that voltage difference produces, and POR_OUT is output as low level.
When the IN+ current potential was higher than the IN-current potential, this moment, supply voltage was given to the drain voltage of NMOS pipe M5, M6 after PMOS manages M1, M3 and PMOS pipe M2, M4 dividing potential drop, still greater than IN+ and IN-; NMOS pipe M5, M6 keep the saturation region at this moment, by PMOS pipe M3, M4 cross-couplings, the voltage of IN-and IN+ are done difference relatively; Make comparator be output as one, inverter output zero setting, the common-source stage amplifier amplifies the electric current that voltage difference produces; POR_OUT is output as high level, accomplishes this moment and goes up electro-detection.
After voltage charging in the sheet was accomplished, the IN+ current potential was equal to supply voltage in the sheet, and this moment, supply voltage was given to the drain voltage of NMOS pipe M5, M6 after PMOS manages M1, M3 and PMOS pipe M2, M4 dividing potential drop; Less than IN+ voltage, greater than IN-voltage, NMOS pipe M5, M7 are in linear zone at this moment; NMOS pipe M6 is in the saturation region; Because IN+ is far longer than IN-, the differential pair electric current is put a little through NMOS pipe M5, M7 fully over the ground, and this moment, comparator circuit can be regarded single inverter circuit as.Because as the PMOS of load pipe pipe M1, M2, M3, M4 charging current a electric current of putting less than M5 and M7; Make comparator be output as zero, inverter output is changed to high level, and the common-source stage amplifier amplifies the electric current that voltage difference produces; POR_OUT is output as low level, accomplishes electrification reset and detects.Can design comparator quiescent point electric current through emulation is than low value, and after the completion of electrification reset testing circuit resetted, the quiescent dissipation of integrated circuit can be very little, realizes low power dissipation design.
Because in the deviation that different temperatures, voltage and manufacturing produce, the time-delay meeting that the delay circuit that powers on produces is different, but because the gain of comparator is enough big, the electrification reset testing circuit still can be realized electro-detection and reset function.If the temperature drift of technology is bigger, can suitably the delay circuit time-delay that powers on be strengthened.
Fig. 3 is to use electrification reset testing circuit structural representation block diagram in the sheet of a kind of high frequency PLL that the present invention uses, and as shown in Figure 3, the electrification reset testing circuit is not when supply voltage is elevated to set point; Output is low level always, and when supply voltage was elevated to set point, output was changed to high level signal; Make circuit begin operate as normal; When supply voltage reached the normal voltage value, output low level provided an electrification reset pulse signal; The electrification reset testing circuit is not when supply voltage is elevated to set point, and output is low level always; When supply voltage was elevated to set point, output was changed to high level signal, makes circuit begin operate as normal; When supply voltage reached the normal voltage value, output low level provided an electrification reset pulse signal; Open Enable Pin by the electrification reset pulse signal, let the interior phase-locked loop of chip start working, when supply voltage reaches the normal voltage value; Output low level provides an electrification reset pulse signal, thereby has realized the electrification reset detection.
Claims (10)
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210198754.3A CN102710242B (en) | 2012-06-17 | 2012-06-17 | On-chip power-on reset detection circuit applied to high-frequency phase locked loop (PLL) |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201210198754.3A CN102710242B (en) | 2012-06-17 | 2012-06-17 | On-chip power-on reset detection circuit applied to high-frequency phase locked loop (PLL) |
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| CN102710242A true CN102710242A (en) | 2012-10-03 |
| CN102710242B CN102710242B (en) | 2015-04-08 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105675955A (en) * | 2016-01-21 | 2016-06-15 | 中山芯达电子科技有限公司 | A zero power consumption voltage detection circuit |
| CN112204884A (en) * | 2018-05-31 | 2021-01-08 | 华为技术有限公司 | Power-on Reset Circuit and Isolated Half-Bridge Driver |
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| US7636019B1 (en) * | 2005-06-07 | 2009-12-22 | Cypress Semiconductor Corporation | Phase lock loop pre-charging system and method |
| CN100583633C (en) * | 2006-09-29 | 2010-01-20 | 联发科技股份有限公司 | Power-on reset circuit |
| CN101860353A (en) * | 2010-06-17 | 2010-10-13 | 广州市广晟微电子有限公司 | Clock circuit control device in digital-analog mixed chip and method thereof |
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2012
- 2012-06-17 CN CN201210198754.3A patent/CN102710242B/en not_active Expired - Fee Related
Patent Citations (4)
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| US7636019B1 (en) * | 2005-06-07 | 2009-12-22 | Cypress Semiconductor Corporation | Phase lock loop pre-charging system and method |
| US20070120612A1 (en) * | 2005-11-29 | 2007-05-31 | Semiconductor Manufacturing International (Shanghai) Corporation | Phase lock loop indicator |
| CN100583633C (en) * | 2006-09-29 | 2010-01-20 | 联发科技股份有限公司 | Power-on reset circuit |
| CN101860353A (en) * | 2010-06-17 | 2010-10-13 | 广州市广晟微电子有限公司 | Clock circuit control device in digital-analog mixed chip and method thereof |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105675955A (en) * | 2016-01-21 | 2016-06-15 | 中山芯达电子科技有限公司 | A zero power consumption voltage detection circuit |
| CN105675955B (en) * | 2016-01-21 | 2018-08-10 | 中山芯达电子科技有限公司 | Zero-power-consumption voltage detection circuit |
| CN112204884A (en) * | 2018-05-31 | 2021-01-08 | 华为技术有限公司 | Power-on Reset Circuit and Isolated Half-Bridge Driver |
| CN112204884B (en) * | 2018-05-31 | 2024-04-26 | 华为技术有限公司 | Power-on reset circuit and isolated half-bridge driver |
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| CN102710242B (en) | 2015-04-08 |
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Address after: 410000 Hunan province Changsha municipal environmental protection science and Technology Industrial Park in Yuhua District Business Center 3 floor Patentee after: HUNAN HKT TECHNOLOGY Co.,Ltd. Address before: 410000 Hunan province Changsha municipal environmental protection science and Technology Industrial Park in Yuhua District Business Center 3 floor Patentee before: Hunan Huakuantong Electronic Technology Co.,Ltd. |
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Granted publication date: 20150408 |