CN102760083A - Multiprocessor operation control method and system thereof - Google Patents

Abstract

The invention discloses an operation control method and system of a multiprocessor, which coordinate the operation sequence of a monitoring processor and a plurality of target processors in executing different operation programs. Obtaining the operation state values of other processors from the buffer block by the monitoring processor; the monitoring processor selects at least one target processor according to the operation state value; the monitoring processor assigns a target processor to execute a corresponding slave operation program and modifies the operation state value of each target processor in the buffer module; the monitoring processor repeats the above-mentioned setting operation status value and assigns other targets to process and execute the corresponding operation programs until the main operation program is completed.

Description

Multiprocessor operation control method and system thereof

technical field

The invention discloses a flow control method and its system, in particular to a multi-processor operation control method and its system.

Background technique

With the refinement of the manufacturing process of the integrated circuit, the processor can achieve a smaller size and have a stronger computing performance at the same time. The development of processors has evolved from a single processor providing single computing capabilities in the past to multi-processors providing their own computing capabilities. Then, the change is that a single processor can provide multi-threaded (threads) computing power. Finally, the evolution to multiprocessors can provide multithreaded operations.

In the process of multi-processor processing, it is necessary to allocate resources to each processor, so as to ensure that each processor will not be idle. Therefore, the processors will query the queries and loads mastered by other processors through polling or interrupts.

Existing polling is initiated by a processor that continually asks other processors to see if the other processors have completed a previous command. The initiating processor can only issue the next command if other processors have completed the command. Although the polling method can ensure that each processor has its own schedule and resources to use. Since the initiating processor needs to wait for the processor to respond during polling, the initiating processor can issue the next command. So the waiting time for polling will be longer than the running time.

In order to shorten the waiting time of polling, another method of interrupt processing has been proposed. Interrupt handling is only a temporary call to the processor to perform work on other devices. Once an interrupt occurs, the processor will store the status information of the registers at that time. After the interrupted transaction ends, the calculation can be restarted based on the state information. In other words, the processor needs to temporarily suspend the working program and turn to handle the related interrupt transaction. Finally, the processor must also provide the ability to resume normal work, so as to continue the unfinished program after processing the interrupt. Compared with polling processing, interrupt processing does not need to wait for other processors to respond, so the initiating processor can issue interrupt requests to different processors. Although interrupt processing can reduce the waiting time, more hardware resources are needed to record the state of the processor during interrupt processing.

Therefore, problems such as long waiting time and consumption of hardware resources will occur when the multi-processor is dispatched (for example: polling processing or interrupt processing).

Contents of the invention

In view of the above problems, the present invention provides a multi-processor operation control method to coordinate the operation sequence of the monitoring processor and multiple target processors executing different operation programs.

The operation control method of the multiprocessor disclosed by the present invention comprises the following steps: the monitoring processor executes the main operation program; the monitoring processor obtains the operating status values of other target processors from the buffer block; the monitoring processor selects at least one The target processor; the monitoring processor resets the operating status values of other selected target processors, so that other target processors execute corresponding subordinate operating programs according to the new operating status values; the monitoring processor repeatedly sets the operating status values until the monitoring processor completes the main operation program; after the monitoring processor completes the main operation program, the monitoring processor will clear the operation status values of other target processors in the buffer block.

The present invention further proposes a multi-processor operation control system including: a monitoring processor, a target processor and a buffer block. When the monitoring processor and the target processor are executing their respective programs, the processor will write its state value into the buffer block. The monitoring processor executes the main operation program, and obtains the operating status values of other target processors from the buffer block; the monitoring processor selects at least one target processor; the monitoring processor resets the selected other target processors operation state value, so that other target processors execute corresponding subordinate operation programs according to the new operation state value; the monitoring processor repeats the steps of setting the operation state value until the monitoring processor completes the main operation program; the monitoring processor completes the main operation program After running the program, the monitoring processor will clear the running status values of other target processors in the buffer block.

The invention provides a multi-processor control method and its system for coordinating the operation sequence of multiple processors executing different operation programs. Each processor of the present invention does not need to obtain the usage status of other processors through interrupts, polling and other means. Therefore, the multi-processor allocation process of the present invention can reduce the time spent on inquiry, so as to improve the operating efficiency of the processors.

Regarding the features and implementation of the present invention, the preferred embodiment is described in detail as follows in conjunction with the accompanying drawings.

Description of drawings

Fig. 1 is a schematic diagram of the architecture of the present invention;

Fig. 2 is a schematic diagram of the operation process of the present invention;

FIG. 3A is a schematic structural diagram of the slave operation program of the present invention;

3B is a schematic diagram of the buffer module of the present invention;

FIG. 3C is a schematic diagram of the overall architecture of the present invention;

FIG. 3D is a program pointer and a program state value of the target processor of the present invention;

FIG. 3E is a program pointer and a program state value of the target processor of the present invention;

Fig. 3F is the program pointer and program status value of the target processor of the present invention;

FIG. 4 is a schematic diagram of pulse signals during operation of the present invention.

Among them, reference signs:

control system 100

processor 110

Monitor Processor 111

target processor 112

buffer module 120

Subordinate Operations Procedure 130

Label A subordinate operation procedure 131-1

Label B subordinate operation procedure 131-2

Label C subordinate operation procedure 131-3

Detailed ways

The present invention can be applied to an integrated circuit chip (integrated circuit, IC) with multiple processors, such as: tablet computer, personal computer, smart phone (Smart Phone) or personal digital assistant (Personal digital assistant, PDA). Please refer to FIG. 1 , which is a schematic diagram of the architecture of the present invention. The control system 100 of the present invention is composed of a plurality of processors 110 and buffer modules 120 . Each processor 110 is electrically connected to the buffer module 120 .

Here, one of the operating processors 110 is selected and defined as the monitoring processor 111 , and the other assigned processors are the target processors 112 . The monitoring processor 111 is used for dispatching other target processors 112 to run corresponding operation programs. The monitoring processor 111 can further determine the number of target processors 112 according to the load requirement of the main operating program or the idle processors 110 . The operating program currently executed by the monitoring processor 111 is defined as the main operating program. The operating program executed by the target processor 112 assigned by the monitor processor 111 is defined as the slave operating program 131 .

The buffer module 120 is used to record the operating status value of each processor executing the operating program, and the operating status value includes at least the identification code of the processor, the program pointer (Program Counter, PC), the program status value (Program Status, PS), write Enter flag or read flag. When the processor is executing the operation program, the processor will update the corresponding operation status value in real time. Therefore, the monitoring processor 111 can determine whether the processor is being used according to the operating state value. Furthermore, the operating state value of the processor 110 can be used to determine whether to be assigned as the target processor 112 . If the main operating program requires more than two target processors 112 during execution, the monitoring processor 111 may determine whether to be assigned as the target processor 112 according to the load level of the processor 110 . For example, when the program pointer and the program status value are "0" at the same time, it means that the processor 110 is completely idle, and it can also be set to treat the processor 110 as idle or busy when it is below a certain threshold. The buffer module 120 can be implemented by a queue (Queue) or a stack (Stack).

The multiprocessor control method of the present invention includes the following steps, please also refer to Figure 2, which is a schematic diagram of the operation flow of the present invention:

Step S210: Execute the main operation program by the monitoring processor;

Step S220: the monitoring processor acquires the operating status values of other target processors from the buffer block;

Step S230: the monitoring processor selects at least one target processor;

Step S240: the monitoring processor assigns the selected target processors to execute corresponding subordinate operating programs, and the monitoring processor resets the operating status values of the selected target processors;

Step S250: the monitoring processor repeats the step of assigning the slave operation program until the monitoring processor completes the main operation program; and

Step S260: After the monitoring processor completes the main operation program, the monitoring processor will flush (Flush) the operating status values of all target processors in the buffer block.

First, the monitoring processor 111 executes the main operation program. The monitoring processor 111 obtains the operating status values of other target processors 112 from the buffer block. The monitoring processor 111 determines the target processor 112 to be assigned according to the acquired operation state value. For example, the monitor processor 111 may select a processor whose program pointer or program status value is “0” as the target processor 112 .

After the monitoring processor 111 selects the target processor 112 , the monitoring processor 111 assigns the selected target processor 112 to execute the corresponding subordinate operation program 131 . At the same time, the monitoring processor 111 also resets the operating state value of the selected target processor 112 , so that other monitoring processors 111 prohibit the use of these assigned target processors 112 . The monitoring processor 111 repeatedly drives the target processor 112 to execute the corresponding slave operating program 131 according to the main operating program until the monitoring processor 111 completes the main operating program.

Finally, when the monitoring processor 111 completes the main operation program, the monitoring processor 111 clears all the operating status values of the target processor 112 in the buffer block, so as to release the usage right of the target processor 112 . The monitoring processor 111 of the present invention assigns each slave operation program 131 to different target processors 112 in a pipelined (Pipeline) manner, so that each target processor 112 can process its own Slave operation program 131 .

In order to clearly illustrate the overall operation of the present invention, the operation process of the monitoring processor 111 and one target processor 112 is used as an illustration here, but the number of target processors 112 is not limited to this. Assuming that the processor 2 serves as the monitoring processor 111, and the processor 1 is the target processor 112, and executes the subordinate operation programs 131 such as Label A, Label B and Label C, as shown in FIG. 3A, which is the subordinate operation program 131 Schematic. From a software point of view, each time the target processor 112 completes the slave operation program 131 , it will output different output values. From a hardware point of view, every time the target processor 112 completes the slave operation program 131 , it will generate different pulse signals (Pulse). The monitoring processor 111 (the monitoring processor 111 is PE2 of the following pseudo code, and the target processor 112 corresponds to PE1 of the pseudo code) then runs the following pseudo code of the main operating program:

Firstly, the monitoring processor 111 repeatedly monitors whether the program state value of the target processor 112 changes (changed from 0 to 1 in this example) in the execution flow of the main operating program. In the pseudo code of this embodiment, a cycle is used to control the operation sequence of the target processor 1121 for Label A, Label B and Label C, but it is not limited thereto. During the process of assigning the target processor 112 , other logic control can be used to determine the execution order of the slave operation program 131 .

The monitoring processor 111 will read whether the program state value of the A0 field in the buffer module 120 is changed to 1 in time. When the program status value of the A0 field is still 0, the monitor processor 111 does not assign the target processor 112 to execute the Label B slave operation program 131-2.

When the Label A subordinate operation program 131-1 is executed, corresponding annotations are made on the field of the corresponding processor in the buffer module 120, as shown in Fig. 3B and Fig. 3C, which are respectively the buffer module and the overall operation schematic diagram. In Fig. 3B, the program pointer and the program state value of the target processor 112 are respectively set to Label A and 0, which means that the monitoring processor 111 will assign the target processor 112 to execute the LabelA slave operating program 131-1, and the target processor The operational state value of 112 is set to 0. In this way, other monitoring processors 111 can observe from the buffer module 120 that the target processor 112 (that is, the original processor 1 ) has been used. Therefore, other monitoring processors 111 will not call the original processor 1 (that is, the target processor 112). After the Label A slave operation program 131-1 is completed, the program status value will be set to 1, as shown in FIG. 3D. When the program state value of the A0 field is 1, the monitor processor 111 assigns the target processor 112 to execute the Label B slave operation program 131-2.

Next, the monitor processor 111 drives the target processor 112 to execute the Label B slave operation program 131-2. The monitor processor 111 sets the program pointer and program status value of the target processor 112 of the buffer module 120 to Label B and 0 respectively, please refer to FIG. 3E . The monitoring processor 111 always reads the operating state value of the target processor 112 of the buffer module 120 and determines whether the operating state value has changed. When the program state value of the B0 field is 1, the monitor processor 111 assigns the target processor 112 to execute the Label C slave operation program 131-3.

Similarly, the monitor processor 111 will drive the target processor 112 to execute the Label C slave operation program 131-3. The monitor processor 111 sets the program pointer and program status value of the target processor 112 of the buffer module 120 to Label C and 0 respectively, please refer to FIG. 3F . When the program state value of the C0 field is 1, the monitor processor 111 assigns the target processor 112 to execute the Label A slave operation program 131-1. After the monitoring processor 111 completes the Label C slave operation program 131-3, the monitor processor 111 will execute the Label A slave operation program 131-1 again according to the cycle of the main operation program.

As mentioned above, the multiprocessor control system 100 of the present invention not only generates corresponding output values when executing each slave operation program 131, but also generates corresponding pulses output through different slave operation programs for the hardware. Signal. Assume that the Label A slave operating program 131-1 generates 4 pulses, the Label B slave operating program 131-2 generates 2 pulses, and the Label C slave operating program 131-3 generates 6 pulses. Please refer to FIG. 4 , which is a schematic diagram of the pulse signal during operation of the present invention.

In addition to the above implementation aspects, the present invention can also be applied to the control system 100 of the multi-object processor 112 . As mentioned above, the monitoring processor 111 can assign different target processors 112 to execute respective slave operating programs 131 while executing the main operating program.

The invention provides a multi-processor control method and its system for coordinating the operation sequence of multiple processors executing different operation programs. Each processor of the present invention does not need to obtain the usage status of other processors through interrupts, polling and other means. Therefore, the multi-processor allocation process of the present invention can reduce the time spent on inquiry, so as to improve the operating efficiency of the processors.

Claims (10)

1. A method for controlling the operation of a multiprocessor, coordinating a monitoring processor and a plurality of target processors in the execution of different operating procedures, characterized in that the control method comprises the following steps: executing a main operating program by the supervisory processor; The monitoring processor obtains an operation state value of the target processors from a buffer block; the monitor processor selects at least one of the target processors; and The monitoring processor assigns the target processors to execute a corresponding dependent operating program, and the monitoring processor resets the operating status values of the selected target processors. 2. The operation control method of a multiprocessor according to claim 1, wherein the operation status value at least includes an identification code, a program pointer, a program status value, a write flag or a read flag mark. 3. The operation control method of a multi-processor according to claim 2, wherein the monitoring processor selects the target processors according to the operation state value. 4. The operation control method of a multiprocessor as claimed in claim 1, wherein the monitor processor repeats the step of assigning the slave program until the monitor processor completes the master program. 5. The operation control method of a multiprocessor as claimed in claim 4, wherein, after the monitoring processor completes the main operation program, the monitoring processor will clear the memory of the target processors in the buffer block. The operational status value. 6. A multi-processor control system that coordinates a plurality of processors to execute the operation sequence of different operation programs, characterized in that the control system includes: a buffer block for recording an operation state value of the processors; At least one target processor, each of which executes a dependent operation program, writes the operation state value of the target processor into the buffer block; and A monitoring processor is used to execute a main operating program, the monitoring processor obtains the operating status values of the target processors from the buffer block, and selects at least one target processor, and the monitoring processor resets The operating state values of the selected target processors are selected, so that the target processors execute the corresponding dependent operating programs according to the new operating state values. 7. The multiprocessor control system as claimed in claim 6, wherein the operating status value at least includes an identification code, a program pointer, a program status value, a write flag or a read flag . 8. The multiprocessor control system as claimed in claim 6, wherein after the monitoring processor completes the main operation program, the monitoring processor will clear the buffer blocks of the target processors Operational status value. 9. The multi-processor control system as claimed in claim 6, wherein the monitor processor repeatedly assigns the slave process until the monitor processor completes the master process. 10. The multiprocessor control system as claimed in claim 6, wherein after the monitoring processor completes the main operation program, the monitoring processor will clear the buffer blocks of the target processors Operational status value.

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