CN102761316A - Delay element, variable delay line, and voltage controlled oscillator, as well as display device and system comprising the same - Google Patents

Abstract

It relates to delay elements, variable delay lines, voltage controlled oscillators, and display devices and systems including the same. Provides a voltage-controlled oscillator, etc., whose central oscillation frequency does not change even if there is a temperature change, by a simple structure. The delay element includes: a delay generating unit that adds a delay amount to an input signal to generate an output signal; and a delay control unit that controls the delay. The delay control unit has a delay adjustment circuit that outputs a first control signal for adjusting a delay amount, and a temperature compensation circuit that outputs a second control signal for compensating for a characteristic change due to temperature. The delay control section outputs a third control signal obtained by synthesizing the first control signal and the second control signal to the delay generation section so as to control the amount of delay. The delay control unit obtains the third control signal by connecting the delay adjustment circuit and the temperature compensation circuit in series.

Description

Delay element, variable delay line, voltage controlled oscillator, and display device and system including same

This application is a divisional application of the Chinese invention patent application. The invention name of the original application is "delay element, variable delay line, voltage-controlled oscillator, and display device and system including the same". The application number of the original application is 200810178825.7. The filing date is December 1, 2008.

Cross References to Related Applications

This application is based on the priority claims of Japanese Patent Application No. 2007-308622 filed on November 29, 2007 and Japanese Patent Application No. 2008-281019 filed on October 31, 2008, the entire contents of which are incorporated herein by reference.

technical field

The invention relates to delay elements, variable delay lines, voltage controlled oscillators, and the like. More specifically, the present invention relates to a circuit element capable of adjusting a delay amount or frequency and capable of performing temperature compensation. In addition, the invention relates to devices such as display devices using those circuit elements.

Background technique

A voltage-controlled oscillator whose oscillation frequency is changed by an applied voltage can easily control the oscillation frequency because it can generate a control signal more easily than a current-controlled type. Therefore, such a voltage controlled oscillator is widely used. There are also several techniques called voltage controlled oscillators. Among them, a circuit in which a closed loop is formed by a plurality of cells each including an inverter configured with a transistor and having a function of adjusting the delay of the inverter is often used because of its simple circuit structure. An inverter configured with a closed loop can form an oscillator called a ring oscillator, which is formed so as to oscillate according to a feedback method. In a voltage controlled oscillator configured with an inverter, there is a circuit of the type described below, that is, it has a function of adjusting the delay of the inverter by having an additional transistor added to the connection between the inverter and the power supply The structure of is realized, and the delay element constituted by the inverter and the added transistor is used as a unit. With this circuit, the oscillation frequency is changed by adjusting the bias voltage of the gate of the transistor connected to the power supply.

Japanese Unexamined Patent Publication No. 05-136693 (Fig. 1, paragraphs 0003-0004, 0009-0011, etc.: Patent Document 1) discloses a phase-locked loop by adding a technique for compensating temperature characteristics to this voltage control the oscillator to form. FIG. 63 is a diagram showing a phase-locked loop described in Patent Document 1. Referring to FIG. The phase locked loop is configured with a voltage controlled oscillator 910 , a phase comparator 904 , a low pass filter 905 and a selection circuit 906 . In addition, a potential compensation circuit for determining an oscillation clock when oscillation is started is connected to the selection circuit 906 . Furthermore, a temperature compensation circuit 920 is connected to the voltage control circuit 910 .

The voltage controlled oscillator 910 is configured with a ring oscillator that obtains oscillation by feeding back the outputs of odd-numbered stages of CMOS (Complementary Metal Oxide Silicon) transistors 911 connected in series to the input side. The oscillation clock is determined when an oscillation control voltage is supplied to the gate of an N-channel type MOS (metal oxide silicon) transistor (hereinafter, referred to as “NMOS transistor”) 912 connected to the ground side of each CMOS transistor 911 OCK frequency. The phase comparator 904 detects the phase difference between the oscillation clock OCK of the voltage controlled oscillator 910 and the reference clock RCK of a specific period, and inputs a detection output PD representing the phase difference between those clocks to the low-pass filter 905 . A low-pass filter 905 removes a high-frequency component of the output PD of the phase comparator 904 representing the phase difference between the oscillation clock OCK and the reference clock RCK, and inputs it to the selection circuit 906 as the first control voltage VC1. The frequency of the oscillation clock OCK of the voltage controlled oscillator 910 is determined by supplying the first control voltage VC1 or the second control voltage VC2 from the selection circuit 906 to the gate of the MOS transistor 912.

In addition, a P-channel type MOS transistor (hereinafter referred to as “PMOS transistor”) 913 is connected to the current source side of each CMOS transistor 911, and a temperature compensation voltage VTC for turning on the PMOS transistor 913 according to temperature increase is applied to the PMOS transistor 913 gates. The temperature compensation circuit 920 that generates the temperature compensation voltage VTC is configured with: a resistor 921 connected in series between the power supply ground and an NMOS transistor 922 whose gate is connected to the drain; output of the junction; and a PMOS transistor 924 connected to the output side of the CMOS transistor 923 while its gate is connected to the drain. The output of the CMOS transistor 923 is supplied to the voltage controlled oscillator 910 as a temperature compensation voltage VTC. Therefore, when the driving capability of the MOS transistor 922 deteriorates due to an increase in temperature, the voltage drop of the NMOS transistor 922 becomes significant. Accordingly, the potential at the junction point between the resistor 921 and the NMOS transistor 922 increases, thereby turning off the P-channel side of the CMOS transistor 923 and turning on the N-channel side thereof. Therefore, the temperature compensation voltage VTC which is the output of the CMOS transistor 923 is pulled up. Due to the increase of the temperature compensation voltage VTC, the on-resistance of the PMOS transistor 913 connected to each CMOS transistor 911 of the voltage controlled oscillator 910 is reduced. Therefore, it is possible to compensate for the deterioration of the driving capability of the CMOS transistor 911 caused by the increase in temperature, thereby suppressing an increase in the delay amount of each CMOS transistor 911 . Therefore, large fluctuations in the frequency of the oscillation clock OCK can be prevented.

In addition, the selection circuit 906 supplies the first control voltage VC1 fluctuating according to the phase difference between the oscillation clock OCK and the reference clock RCK or the second control voltage VC2 of a fixed level to the gate of the NMOS transistor 912 . The first control voltage VC1 is obtained from the comparison output PD of the phase comparator 904 that detects the phase difference between the oscillation clock OCK output by the voltage controlled oscillator 910 and the reference clock RCK, and is input to the selection circuit 906 . At the same time, the second control voltage VC2 is obtained from a voltage compensation circuit 930 capable of obtaining a constant level output irrespective of fluctuations in the potential of the current source, and input to the selection circuit 906 . The voltage compensation circuit 930 generating the second control voltage VC2 of a constant level is configured with: an NMOS transistor 931 connected to the power supply side and having a power supply potential supplied to its gate; and two NMOS transistors 932, 933 connected in series to the ground side and has a gate connected to the drain. The voltage compensation circuit 930 outputs the potential of the junction point between the NMOS transistor 931 and the NMOS transistor 932 as the second control voltage VC2. By using such a voltage compensation circuit 930, the potential on the power supply side of the NMOS transistor 932 always shows a voltage higher than the ground potential by the amount of the threshold of the NMOS transistors 932, 933. Therefore, the second control voltage VC2 obtained from the junction point between the NMOS transistors 931, 932 always maintains a constant level regardless of fluctuations in the power supply potential.

However, in the delay element of the voltage controlled oscillator described in Patent Document 1, there are two parts that can be adjusted from the outside for stabilizing the oscillation frequency with respect to changes in temperature. Therefore, the structure becomes complicated. In addition, there are some problems as described below.

The first problem is insufficient temperature compensation because the temperature compensation performed by the temperature compensation circuit of Patent Document 1 generates a temperature compensation voltage by using only the difference between resistance and temperature dependence of a diode-connected transistor. Temperature compensation by this structure becomes insufficient for three reasons described below.

The first reason is that there is a large difference in voltage-current characteristics of resistance and diode-connected transistors. In particular, diode-connected transistors are often used as a replacement for resistors, however, the linearity of voltage and current is not good. Therefore, the voltage determined by those two elements exhibits poor linearity with respect to changes in current due to temperature.

The second reason is that the temperature dependence of resistance and diode-connected transistors varies with voltage region. There is a small change in the temperature dependence of the resistance caused by the voltage. Meanwhile, the temperature dependence of the transistor greatly changes depending on the voltage because the temperature dependence of the mobility and the temperature dependence of the threshold have a large effect, and they reverse their effects with respect to the temperature. Therefore, the change in voltage generated according to the temperature across the two elements changes so that the correspondence between the change in temperature and the change in voltage becomes non-linear. In some cases, their relationship becomes inverted, making it difficult to perform control over them.

The third reason is a voltage for temperature generated in a temperature compensation circuit configured with a resistor and a diode-connected transistor and used to compensate for a change in characteristics due to a temperature change generated in a voltage controlled oscillator configured with a transistor There is no exact agreement between voltages. That is, the voltage controlled oscillator and the temperature compensation circuit have different temperature dependencies, and therefore, the temperature compensation effect is insufficient. For these three reasons, the temperature compensation performed by the technique of Patent Document 1 is insufficient.

The second problem is having large timing variations in performance because differently controlled biases (voltages) need to be applied to the power and ground sides of the delay element. That is, a bias voltage from the temperature compensation circuit is applied to the power supply side, and a bias voltage from the potential compensation circuit is applied to the ground side. With this structure, the power side and the ground side will be under completely different controls. Therefore, under widely different bias conditions, a transistor receiving a bias on the power supply side (913 in FIG. 63) and a transistor receiving a bias on the ground side (912 in FIG. 63) are used. Therefore, the state of deterioration of transistors on the current source side and the ground side greatly changes, and therefore deterioration caused by one of the transistors changes the performance of the voltage controlled oscillator and greatly affects long-term reliability. As mentioned, the timing variation in performance is significant.

Similar to the second problem, the third problem arises due to the fact that the function of the potential compensation circuit for adjusting the frequency and the function of the temperature compensation circuit for compensating the temperature operate in different parts of the delay element. That is, the technique of Patent Document 1 requires two parts that are provided inside the delay element and that can be adjusted from the outside. Therefore, the above technique cannot be applied to a structure having only one externally adjustable portion provided within the delay element.

Also, in the case where there are two external adjustable parts within the delay element, if the two external adjustable parts are constructed to be controlled in the same way so as to avoid the second problem of timing variation, the result becomes the same as having only one adjustable The same structure as the case of the adjustment part. Therefore, the technique described above cannot be applied to this situation. That is, when it is configured such that transistors for respectively receiving bias voltages supplied to the power supply side and the ground side are simultaneously controlled by respectively supplying bias voltages under which both transistors change in the same manner, only There is a bias voltage that can be used practically. Therefore, the technique of Patent Document 1 cannot be applied. Also, where there are two external adjustable sections within the delay element, these two adjustable sections are used. Therefore, no other adjustable functions can be added. Therefore, use this technique only under very limited conditions.

A fourth problem is that there is no versatility in using the structure. That is, the delay element is limited to configure its structure with an inverter and a transistor added to the inverter, and other structures cannot be used.

Contents of the invention

Therefore, an exemplary object of the present invention is to provide a simple-structured voltage-controlled oscillator, etc., whose center oscillation frequency does not change even when there is a temperature change. For example, it is possible to provide a voltage-controlled oscillator or the like with a simple structure that can perform temperature compensation without using external components such as a temperature-compensated quartz oscillator or the like.

Another exemplary object of the present invention is to provide a delay element having a function of adjusting a delay amount and compensating for a characteristic change caused by temperature by applying an effect to a single portion of the delay element. In addition, a variable delay line and a voltage controlled oscillator capable of adjusting frequency and compensating for temperature by utilizing that delay element are provided. Another exemplary object of the present invention is to provide delay elements of various structures having functions of adjusting a delay amount and compensating for a change in characteristics caused by temperature. In addition, a variable delay line and a voltage controlled oscillator are provided that adjust frequency and compensate for temperature by utilizing that delay element. Another exemplary object of the present invention is to provide a display device having a functional circuit unit and a display unit integrally formed compensating for temperature characteristics thereof. Furthermore, various devices and systems using that display device as one of the structural modules are provided. Another exemplary object of the present invention is to provide a display device with low power consumption. Furthermore, various devices and systems using that display device as one of the structural modules will be provided.

A delay element according to an exemplary aspect of the present invention includes a delay generating section that adds a certain delay amount to an input signal to generate an output signal, and a delay control section that controls the delay amount. The delay control section includes a delay adjustment circuit that outputs a first control signal for adjusting a delay amount, and a temperature compensation circuit that outputs a second control signal for compensating for a characteristic change caused by temperature. The delay control section outputs a third control signal obtained by synthesizing the first control signal and the second control signal to the delay generation section so as to control the amount of delay.

A variable delay line according to another exemplary aspect of the present invention includes a plurality of delay elements of the present invention connected in series.

A voltage controlled oscillator according to still another exemplary aspect of the present invention is configured with the variable delay line of the present invention, having an output terminal of one of a plurality of delay elements in which is connected to one of delay elements of a stage preceding that delay element. A closed loop at the input terminal.

A display device according to still another exemplary aspect of the present invention includes the voltage controlled oscillator of the present invention and a functional circuit unit including the voltage controlled oscillator.

A system according to still another exemplary aspect of the present invention includes the display device of the present invention as one of the structural modules.

Description of drawings

1 shows a block diagram of a delay element according to a first exemplary embodiment of the present invention, wherein FIG. 1A shows a schematic diagram of the delay element, and FIG. 1B shows details of the delay element;

2 is a circuit block diagram showing a first example of a delay control section of the first exemplary embodiment;

3 is a circuit block diagram showing a first example of a delay generating section of the first exemplary embodiment;

4 is a circuit block diagram showing a second example of the delay generating section of the first exemplary embodiment;

5 is a circuit block diagram showing a third example of the delay generating section of the first exemplary embodiment;

Fig. 6 is a circuit block diagram showing the mirror effect of the delay generating section shown in Fig. 5;

7 is a circuit block diagram showing a fourth example of the delay generating section of the first exemplary embodiment;

8 is a circuit block diagram showing a fifth example of the delay generating section of the first exemplary embodiment;

9 is a circuit block diagram showing a sixth example of the delay generating section of the first exemplary embodiment;

10 is a block diagram of a delay element representing a second exemplary embodiment of the present invention, wherein FIG. 10A represents a schematic diagram of the delay element, and FIG. 10B represents details of the delay element;

11 is a circuit block diagram showing a delay control section and a first example of a synthesis circuit of the second exemplary embodiment;

12 is a block diagram showing a variable delay array according to a third exemplary embodiment;

13 is a block diagram showing a variable delay array according to a fourth exemplary embodiment;

14 is a block diagram showing a variable delay array according to a fifth exemplary embodiment;

15 is a block diagram showing a voltage controlled oscillator according to a sixth exemplary embodiment;

FIG. 16 is a block diagram showing an oscillator related to the sixth exemplary embodiment;

17 is a circuit block diagram showing a first example of a voltage controlled oscillator according to a sixth exemplary embodiment;

18 is a circuit block diagram showing a second example of a voltage-controlled oscillator according to the sixth exemplary embodiment;

19 is a circuit block diagram showing a third example of the voltage controlled oscillator according to the sixth exemplary embodiment;

20 is a block diagram showing a voltage controlled oscillator according to a seventh exemplary embodiment;

21 is a block diagram showing a voltage controlled oscillator according to the eighth exemplary embodiment;

22 is a circuit block diagram showing another example of a delay element according to each of the exemplary embodiments;

23 is a graph showing the relationship between gate voltage and leakage current of a single gate transistor;

Fig. 24 is a graph showing the relationship between the gate voltage and the leakage current of a double gate transistor;

25 is a circuit block diagram showing an example of a symmetrical load configured with two transistors;

26 is a circuit block diagram showing a voltage-controlled oscillator according to Embodiment 1;

27 is a graph showing the relationship between the control bias voltage and the oscillation frequency at room temperature (27 degrees Celsius) with respect to the voltage controlled oscillator according to Embodiment 1;

28 is a graph showing the relationship between the control bias voltage and the oscillation frequency of the voltage controlled oscillator according to Embodiment 1 when the bias voltage for compensating the temperature characteristic is fixed and the temperature is changed from 0 degrees to 80 degrees at intervals of 20 degrees ;

29 is a graph showing the relationship between the control bias voltage and the oscillation frequency of the voltage controlled oscillator according to Embodiment 1 when applying a bias voltage for compensating temperature characteristics while changing the temperature from 0 degrees to 80 degrees at intervals of 20 degrees the graph of

30 is a graph showing the relationship between temperature and frequency of the voltage controlled oscillator according to Embodiment 1 with respect to the case of using the temperature compensation bias and the case of not using the temperature compensation bias while fixing the control bias at 2V picture;

31 is a circuit block diagram showing a voltage-controlled oscillator according to Comparative Example 1;

32 is a graph showing the relationship between the control bias voltage and the oscillation frequency at room temperature (27 degrees) with respect to the voltage controlled oscillator according to Comparative Example 1;

33 is a graph showing the relationship between the control bias voltage and the oscillation frequency of the voltage controlled oscillator according to Comparative Example 1 when the bias voltage for compensating the temperature characteristic is fixed and the temperature is changed from 0 degrees to 80 degrees at intervals of 20 degrees ;

34 is a circuit block diagram showing a voltage-controlled oscillator according to Embodiment 2;

35 is a graph showing the relationship between the control bias voltage and the oscillation frequency at room temperature (27 degrees) with respect to the voltage controlled oscillator according to Embodiment 2;

36 is a graph showing the relationship between the control bias voltage and the oscillation frequency according to Embodiment 2 when the bias voltage for compensating the temperature characteristic is fixed and the temperature is changed from 0 degrees to 80 degrees at intervals of 20 degrees;

37 is a graph showing the relationship between the control bias voltage and the oscillation frequency of the voltage controlled oscillator according to Embodiment 2 when a bias voltage for compensating temperature characteristics is applied while changing the temperature from 0 degrees to 80 degrees at intervals of 20 degrees. the graph of

38 is a circuit block diagram showing a voltage-controlled oscillator according to Embodiment 3;

39 is a graph showing the relationship between the control bias voltage and the oscillation frequency at room temperature (27 degrees) with respect to the voltage controlled oscillator according to Embodiment 3;

40 is a graph showing the relationship between the control bias voltage and the oscillation frequency of the voltage controlled oscillator according to Embodiment 3 when the bias voltage for compensating the temperature characteristic is fixed and the temperature is changed from 0 degrees to 80 degrees at intervals of 20 degrees ;

41 is a graph showing the relationship between the control bias voltage and the oscillation frequency of the voltage controlled oscillator according to Embodiment 3 when a bias voltage for compensating temperature characteristics is applied while changing the temperature from 0 degrees to 80 degrees at intervals of 20 degrees the graph of

42 is a circuit block diagram showing a voltage-controlled oscillator according to Embodiment 4;

43 is a graph showing the relationship between the control bias voltage and the oscillation frequency at room temperature (27 degrees) with respect to the voltage controlled oscillator according to Embodiment 4;

44 is a graph showing the relationship between the control bias voltage and the oscillation frequency of the voltage controlled oscillator according to Embodiment 4 when the bias voltage for compensating the temperature characteristic is fixed and the temperature is changed from 0 degrees to 80 degrees at intervals of 20 degrees ;

45 is a graph showing the relationship between the control bias voltage and the oscillation frequency of the voltage controlled oscillator according to Embodiment 4 when a bias voltage for compensating temperature characteristics is applied while changing the temperature from 0 degrees to 80 degrees at intervals of 20 degrees. the graph of

46 is a graph showing the relationship between the temperature and the frequency of the voltage controlled oscillator according to Embodiment 4 regarding the case of using the temperature compensation bias and the case of not using the temperature compensation bias while fixing the control bias at 2V picture;

47 is a circuit block diagram showing a voltage-controlled oscillator according to Embodiment 5;

Fig. 48 is a graph showing the relationship between the control bias voltage and the oscillation frequency at room temperature (27 degrees) with respect to the voltage controlled oscillator according to Embodiment 4 and Embodiment 5;

49 is a graph showing the relationship between the control bias voltage and the oscillation frequency with respect to the voltage controlled oscillator according to Embodiment 4 and Embodiment 5 when the transistor is damaged;

50 is a block diagram showing a first example of the resistance adding method according to Embodiment 5;

51 is a block diagram showing a second example of the resistance adding method according to Embodiment 5;

52 is a block diagram showing a third example of the resistance adding method according to Embodiment 5;

53 is a circuit block diagram showing a part of a voltage-controlled oscillator according to Embodiment 6;

54 is a circuit block diagram showing a voltage controlled oscillator according to Embodiment 7;

55 is a circuit block diagram showing a voltage-controlled oscillator according to Embodiment 8;

56A is a plan view showing a display device according to Embodiment 10 of the present invention, and FIG. 56B is a perspective view showing a system according to Embodiment 11 of the present invention;

57 is a circuit block diagram showing a delay generating section according to Embodiment 12;

58 is a circuit block diagram showing a delay generating section according to Embodiment 13;

FIG. 59 is a circuit block diagram showing a delay generating section according to Embodiment 14;

60 is a circuit block diagram showing a delay generation section having a level shift circuit according to Embodiment 13 and Embodiment 14;

FIG. 61 is a circuit block diagram showing a core portion of the temperature sensor described in Patent Document 2 used in Embodiment 15;

62 is a circuit block diagram showing a reference voltage generation circuit according to Embodiment 16; and

Fig. 63 is a circuit block diagram showing the configuration of a phase-locked loop using a conventional voltage controlled oscillator.

Detailed ways

(First Exemplary Embodiment)

1A and 1B show block diagrams of a delay element according to a first exemplary embodiment of the present invention, wherein FIG. 1A shows a schematic diagram of the delay element, and FIG. 1B shows details of the delay element. Hereinafter, an explanation is provided by referring to the accompanying drawings.

The delay element 10 of this exemplary embodiment includes a delay generation section 11 that adds a delay amount τd to an input signal Vi to generate an output signal, and a delay control section 12 that controls the delay amount τd. The delay control section 12 has a delay adjustment circuit 13 that outputs the control signal S1 as a first control signal for adjusting the delay amount τd, and has a temperature compensation circuit 14 that outputs the control signal S2 as a second control signal for compensation by Changes in properties due to temperature. The delay control section 12 outputs the control signal S3, which is a third control signal obtained by synthesizing the control signal S1 and the control signal S2, to the delay generation section 11 so as to control the delay amount τd. The delay control unit 12 obtains the control signal S3 by connecting the delay adjustment circuit 13 and the temperature compensation circuit 14 in series. The control signal S0 corresponds to a predetermined delay amount τd, and is output to the delay adjustment circuit 13 from another circuit not shown.

That is, the delay control section 12 for controlling delay has a configuration in which a delay adjustment circuit 13 and a temperature compensation circuit 14 are connected in series. As shown in FIG. 1A , the delay element 10 generates a certain delay amount τd between an input signal Vi from the left side of the diagram and an output signal Vo from the right side of the diagram. Referring to FIG. 1B , delay element 10 has delay control section 12 provided with delay adjustment circuit 13 and temperature compensation circuit 14 in addition to delay generation section 11 . The delay adjustment circuit 13 and the temperature compensation circuit 14 are connected in series with respect to each other. In FIG. 1B , the control signal S3 is output from the delay adjustment circuit 13 to the delay generator 11 . However, the control signal S3 may be output from the temperature compensation circuit 14 or a junction between the delay adjustment circuit 13 and the temperature compensation circuit 14 .

By connecting the delay adjustment circuit 13 and the temperature compensation circuit 14 in series, their functions can be synthesized. That is, it is possible to generate the control signal S3 in which the function of adjusting the delay amount τd and the function of compensating the temperature characteristic are synthesized.

In particular, when the main components constituting the delay adjustment circuit 13 and the temperature compensation circuit 14 are voltage-current conversion elements, the delay element 10 that can be adjusted by voltage can be formed. The voltage-current conversion element outputs current according to the input voltage. In this exemplary embodiment, the delay adjustment circuit 13 and the temperature compensation circuit 14 are connected in series so that one of the voltage-current conversion elements is influenced by the other. Therefore, the current output from each of the voltage-current conversion elements is changed. For example, when the applied voltage of the voltage-current conversion element in the temperature compensation circuit 14 is changed while the applied voltage of the voltage-current conversion element in the delay adjustment circuit 13 is set constant, not only The current output from the voltage-current conversion element of , and the current output from the voltage-current conversion element in the delay adjustment circuit 13 is also changed. In this way, the effects of the delay adjustment circuit 13 and the temperature compensation circuit 14 can be synthesized. The combined effect, that is, the output current from the voltage-current conversion element is directly or indirectly added to the delay generating section 11 as the control signal S3, and the delay amount τd is adjusted.

For example, main components of delay adjustment circuit 13 and temperature compensation circuit 14 may be formed by voltage-current conversion elements, and output current may be current-voltage converted to be applied to delay generation section 11 as a voltage bias. FIG. 2 shows an example of the delay control unit 12 embodying such a configuration.

FIG. 2 is a circuit block diagram showing a first example of the delay control section according to this exemplary embodiment. Hereinafter, description will be provided with reference to FIGS. 1 and 2 .

The delay control unit 12 has a delay adjustment circuit 13 and a temperature compensation circuit 14 . In this example, the voltage-current conversion element is constituted by an NMOS transistor. The delay adjustment circuit 13 has a circuit 13' including an NMOS transistor 2f as a voltage-current conversion element and a current mirror circuit 13". The temperature compensation circuit 14 includes an NMOS transistor 2g as a voltage-current conversion element. The NMOS transistors 2f and 2g are connected in series , and the current output thereby is input to a current mirror circuit 13" configured with PMOS transistors 1f, 1g. In the current mirror circuit 13", a current according to the current generated from the NMOS transistors 2f and 2g flows in the PMOS transistor 1g. At this time, the gate voltage of the PMOS transistors 1f and 1g is the voltage between the PMOS transistor 1f and the NMOS transistor 2f The voltage is determined by the PMOS transistor 1f and the NMOS transistors 2f, 2g. That is, by this connection, current-voltage conversion is performed. The gate voltage output of the PMOS transistor 1f, 1g is used as the control signal S3 for controlling the delay generating part 11.

In addition, another circuit 40 other than the main components of this example is connected in series with the PMOS transistor 1g. The bias voltage B1 corresponds to the control signal S0, for example. The bias voltage B2 is a signal corresponding to the current temperature, and is output from, for example, a temperature sensor (not shown) within the temperature compensation circuit 14 .

With this exemplary embodiment, delay adjustment and temperature compensation can be realized in a structure having only one externally controllable section within the delay generating section 11 . Meanwhile, with the structure of multiple external adjustable parts within the delay generating part 11, only one adjustable part is required for conventional delay adjustment and temperature compensation. Therefore, the remaining adjustable part can be used for other purposes, for example, for fine-tuning of the delay.

Various types are used for the delay generation section 11 of this exemplary embodiment. Hereinafter, some examples of the delay generation section 11 will be described with reference to the drawings.

FIG. 3 is a circuit block diagram showing a first example of the delay generation section according to this exemplary embodiment. Hereinafter, explanations are provided with reference to the accompanying drawings.

The delay generator 11a in this example is a circuit called a current-starved inverter (Current-Starved Inverter). In the delay generator 11 a, the PMOS transistor 1 a and the NMOS transistor 2 a connected between the input and the output constitute an inverter 3 . The PMOS transistor 1b and the NMOS transistor 2b are respectively connected between the inverter 3 and the high voltage side power supply (Vdd in the figure) and between the inverter 3 and the low voltage side power supply (the ground in the figure may be a potential other than ground). In other words, the PMOS transistor 1b is connected between the PMOS transistor 1a and the high-side power supply, and the NMOS transistor 2b is connected between the NMOS transistor 2a and the low-side power supply.

A bias voltage B11 is applied to the gate electrode of the PMOS transistor 1b, and a bias voltage B12 is applied to the gate electrode of the NMOS transistor 2b. By adjusting the bias voltages B11 and B12, the drain-source resistances of the PMOS transistor 1b and the NMOS transistor 2b can be adjusted to also vary the current flowing to the PMOS transistor 1a and the NMOS transistor 2a. Therefore, the delay amount of the delay generating section 11a can be adjusted by the bias voltages B11 and B12. That is, when the drain-source resistance is increased by both or one of the bias voltages B11 and B12, the current flowing to the inverter 3 is reduced, thereby increasing the delay amount τd of the delay generating section 11a. Conversely, when the drain-source resistance is reduced, the current flowing to the inverter 3 is increased, thereby reducing the delay amount τd of the delay generation section 11a.

In this exemplary embodiment, an adjustment bias (ie, control signal S3 ) generated by connecting the delay adjustment circuit 13 and the temperature compensation circuit 14 in series is input to the bias voltage B11 or the bias voltage B12 . This enables delay adjustment and temperature compensation to be performed. A single current-limited inverter only needs to have a PMOS transistor 1b or an NMOS transistor 2b. That is, three transistors can be configured.

FIG. 4 is a circuit block diagram showing a second example of the delay generating section according to this exemplary embodiment. The description is provided by primarily referring to FIG. 4 .

The delay generation section 11b of this example has an additional capacitance 4a added to the current-limited inverter. That is, by adding the additional capacitance 4a to the output portion of the delay generating portion 11a of FIG. 3, the delay generating portion 11b is formed. The charge and discharge current of the capacitor is increased by adding an additional capacitor 4a, thereby increasing the delay τd. With the delay generating section 11b, a delay element having a longer delay time than that of the delay generating section 11a of FIG. 3 can be formed. That is, when the voltage controlled oscillator is configured by using the delay generating section 11b, a voltage controlled oscillator having a lower frequency can be formed than in the case of using the delay generating section 11a of FIG. 3 . In addition, the reference value of the oscillation frequency can be controlled by the capacitance value of the additional capacitor 4a.

FIG. 5 is a circuit block diagram showing a third example of the delay generating section according to this exemplary embodiment. FIG. 6 is a circuit block diagram showing a mirror effect of the delay generator shown in FIG. 5 . Hereinafter, description will be provided by mainly referring to FIGS. 5 and 6 .

The delay generation section 11c of this example has an additional capacitance 4b added to the current-limited inverter. That is, the delay generation unit 11c is formed by adding an additional capacitor 4b between the input and output of the delay generation unit 11a in FIG. 3 . A big difference between the delay generation unit 11c and the delay generation unit 11b of FIG. 4 is that the additional capacitor 4b is formed as a mirror capacitor.

Fig. 6 illustrates the additional capacitance 4b as a mirror capacitance for describing the mirror effect. As a mirror capacitor instead of the additional capacitor 4b, an input mirror capacitor 4c is connected between the input and the low-voltage side power supply, and an output mirror capacitor 4d is connected between the output and the low-voltage side power supply. It is assumed here that the capacitance value of the additional capacitor 4 a in FIG. 4 is C, the capacitance value of the additional capacitor 4 b is also C, and the gain of the inverter 3 is A. In that case, the capacitance value of the input mirror capacitor 4c is "(1+|A|)·C", and the capacitance value of the output mirror capacitor 4d is "(1+1/|A|)·C". Both values are greater than the initial capacitance value C.

The gain A is determined by the drain conductance or transconductance of each transistor within the current limited inverter. The transconductance and drain conductance change according to voltage conditions. In particular, when a capacitor is charged, the mutual conductance becomes large. Therefore, the gain |A| becomes a value of about ten times, and the input mirror capacitance 4c becomes extremely large. Under operating conditions where the drain conductance becomes large, the gain |A| becomes extremely small. Therefore, the output mirror capacitance 4d becomes extremely large. As mentioned, the capacitance value of each mirror capacitor changes according to the voltage condition, and the total capacitance value of both is “(2+|A|+1/|A|)·C”. This value becomes substantially twice the value of the additional capacitance 4a of FIG. 4 or more. Add the input mirror capacitor 4c as the output capacitor of the previous stage. Therefore, when paying attention to a certain stage, the total capacitance of the input mirror capacitor 4c and the output mirror capacitor 4d becomes an additional capacitance of the output.

Therefore, in order to realize the same capacitance value as the additional capacitance 4a of FIG. 4, in this example, it is simply necessary to provide the additional capacitance 4b of half the capacitance value or less. Therefore, the layout area can be reduced. As described above, the delay generating section 11 c of this example is more advantageous in terms of layout area than the delay generating section 11 b of FIG. 4 . In addition, as in the case of the delay generating section 11 b of FIG. 4 , a delay element having a longer delay time than that of the delay generating section 11 a of FIG. 3 can be formed by the delay generating section 11 c. That is, when the voltage controlled oscillator is constructed by using the delay generating section 11c, a voltage controlled oscillator having a lower frequency can be formed than in the case of using the delay generating section 11a of FIG. In addition, the reference value of the oscillation frequency can be controlled by adding the capacitance value of the capacitor 4b.

FIG. 7 is a circuit block diagram showing a fourth example of the delay generation section according to this exemplary embodiment. Hereinafter, description will be provided mainly with reference to FIG. 7 .

The delay generator 11d of this example is an inverter using the transistor capacitance 5b whose source and drain are short-circuited as an additional capacitance. In this configuration, the drain of the adjustment transistor 5a is connected to the output of the inverter 3 including the PMOS transistor 1a and the NMOS transistor 2a, and a transistor capacitor 5b is connected between the source of the adjustment transistor 5a and the low-side power supply. The gate of transistor capacitor 5b is connected to the source of regulating transistor 5a, while the source and drain of transistor capacitor 5a are short-circuited and connected to the low side power supply.

Through this delay generation section 11d, the drain-source resistance of the adjustment transistor 5a is adjusted by the bias voltage B30 applied to the gate of the adjustment transistor 5a. Through this, the time constant determined by the resistance value of the drain-source resistance of the adjustment transistor 5a and the capacitance value of the transistor capacitance 5b is changed. As described above, it is possible to adjust the time constant due to the product of the additional resistance value of the transistor 5a and the additional capacitance value of the transistor capacitance 5b due to the adjustment of the bias voltage B30, and therefore, the delay amount τd of the entire delay element 10 can also be adjusted. The adjustment transistor 5a and the transistor capacitance 5b may be formed by PMOS transistors. In that case, the drain and source of the transistor capacitor 5b are connected to the high side power supply.

Unlike the cases of the delay generating section 11b of FIG. 4 and the delay generating section 11c of FIG. 5, with the delay generating section 11d, it is not necessary to form a capacitor as a dedicated element. Therefore, all basic design and fabrication can be done by considering only transistors as elements, making it easy to perform process development and fabrication.

FIG. 8 is a circuit block diagram showing a fifth example of the delay generating section according to this exemplary embodiment. Hereinafter, explanation is provided by mainly referring to FIG. 8 .

The delay generating section 11e of this example is an element of differential input, and is configured with, for example, a differential input pair, a resistive load, and a current source. The sources of the NMOS transistors 2c and 2d are connected to each other so as to form a differential input pair. The PMOS transistors 1c and 1d are connected to the drains of the NMOS transistors 2c and 2d, respectively. These PMOS transistors 1c and 1d are operated in a linear region (triode region) so as to be used as a resistive load. In addition, the NMOS transistor 2e functions as a current source.

When the positive input and the negative input are input to the two input terminals of the delay generating section 11e, both the positive output and the negative output are output to the two output terminals. The delay amount τd in the delay generation section 11e is adjusted by the bias voltage B12 applied to the PMOS transistors 1c, 1d serving as a resistive load, or by the bias voltage B11 applied to the NMOS transistor 2e serving as a power supply. In addition, there may be a structure in which PMOS transistors and NMOS transistors are exchanged with each other. Meanwhile, any other structure may be adopted as long as it has a differential input pair.

Unlike the configurations of the first to fourth examples described above, the amplitude of the signal becomes small by the delay generation section 11e because it uses a differential signal. Therefore, power consumption can be reduced. In addition, since differential signals are used, the influence of noise between signal lines such as grounds and power lines can be reduced. This makes it possible to suppress variations in delay time caused by noise. Therefore, the voltage controlled oscillator using the delay generating section 11e has a highly stable oscillation frequency.

FIG. 9 is a circuit block diagram showing a sixth example of the delay generation section according to this exemplary embodiment. Hereinafter, an explanation will be provided with reference to FIG. 9 .

The delay generator 11f of this example is an element in which two transistors are arranged. That is, for example, the delay generation unit 11f includes a PMOS transistor 1a inserted between the signal transmission line and an NMOS transistor 2a inserted between the signal transmission line and the low-voltage side power supply. By adjusting the bias voltage (bias B11 and bias B12 ) applied to the gate of each transistor, the amount of delay τd can be controlled.

When a signal that varies with the amplitude between the low-side power supply and the high-side voltage is input to the delay generator 11f, the output of the delay generator 11f may become smaller than the amplitude between the low-side power supply and the high-side power supply. In that case, an inverter or the like configured with PMOS transistors and NMOS transistors may be connected at the stage after the output in order to return the lower amplitude to the amplitude between the low voltage side power supply and the high voltage side power supply. As another structure, a structure may be employed in which an NMOS transistor inserted between the signal transmission line and a PMOS transistor inserted between the signal transmission line and the high-voltage side power supply are arranged.

Compared with the structures of the first to fifth examples, by the delay generation section 11f, a delay element using an extremely small number of elements can be realized. Therefore, the layout area can be reduced. In addition, since the number of components is reduced, the manufacturing of deterioration can be reduced, and therefore, the cost can be reduced.

As an exemplary advantage according to the present invention, the control signal from the delay adjustment circuit and the control signal from the temperature compensation circuit are synthesized and output to the delay generation section. This simplifies the interface between the delay control unit and the delay generation unit. Therefore, with a simple structure, it is possible to provide a voltage-controlled oscillator and the like whose center oscillation is stable even when there is a temperature change.

(Second Exemplary Embodiment)

10A and 10B are circuit block diagrams showing a delay element according to a second exemplary embodiment of the present invention, wherein FIG. 10A shows a schematic diagram of the delay element, and FIG. 10B shows details of the delay element. Hereinafter, explanations are provided with reference to the accompanying drawings.

The delay element 20 of this exemplary embodiment includes: a delay generating section 11 that adds a delay amount τd to an input signal Vi to generate an output signal; and a delay control section 22 that controls the delay amount τd. The delay control section 22 has a delay adjustment circuit 13 that outputs a control signal S1 as a first control signal for adjusting the delay amount τd, and has a temperature compensation circuit 14 that outputs a control signal S2 as a first control signal for compensating a characteristic change caused by temperature. the second control signal. The delay control section 22 outputs the control signal S3, which is a third control signal obtained by synthesizing the control signal S1 and the control signal S2, to the delay generation section 11 so as to control the delay amount τd. The delay control unit 22 obtains the control signal S3 by connecting the delay adjustment circuit 13 and the temperature compensation circuit 14 in parallel via the combination circuit 23 . The control signal S0 corresponds to a predetermined delay amount τd, and it is output to the delay adjustment circuit 13 from another circuit not shown.

The delay generation section 11, the delay adjustment circuit 13, and the temperature compensation circuit 14 are the same in structure as the first exemplary embodiment. Therefore, the structures shown in FIGS. 3 to 9 can also be used as the delay generation section 11 of this exemplary embodiment.

That is, the delay control section 22 for controlling delay is constituted by connecting the delay adjustment circuit 13 and the temperature compensation circuit 14 in a parallel relationship to the synthesis circuit 23 . Hereinafter, it will be described in detail.

In addition to having the same delay generating section 11 as the delay element 10 shown in FIG. twenty three. The delay adjustment circuit 13 and the temperature compensation circuit 14 are arranged in parallel with each other and connected to a synthesis circuit 23 . A control signal S3 serving as a delay control signal is output from the combination circuit 23 to the delay generator 11 .

By arranging the delay adjustment circuit 13 and the temperature compensation circuit 14 in parallel and connecting them to the synthesis circuit 23, their functions can be synthesized. That is, it is possible to generate the control signal S3 in which the function of adjusting the delay and the function of compensating the temperature characteristic are synthesized.

In particular, when the main components constituting the delay adjustment circuit 13 and the temperature compensation circuit 14 are voltage-current conversion elements, the delay element 20 that can be adjusted by voltage can be formed. The voltage-current conversion element outputs current according to the input voltage. In this exemplary embodiment, the delay adjustment circuit 13 and the temperature compensation circuit 14 are connected in parallel to the synthesis circuit 23 . Therefore, it is possible to output current by not causing one of the voltage-current conversion elements to be influenced by the other voltage-current conversion element, and to synthesize the output current at the synthesizing circuit 23 .

For example, when the applied voltage of the voltage-current conversion element in the temperature compensation circuit 14 is changed while setting the applied voltage of the voltage-current conversion element in the delay adjustment circuit 13 to be constant, from the voltage in the temperature compensation circuit 14- The current output by the current conversion element is changed. However, the current output from the voltage-current conversion elements within the parallel-connected delay adjustment circuit 13 does not change. These two currents are combined in the combining circuit 23 . In this way, the effects of the delay adjustment circuit 13 and the temperature compensation circuit 14 can be synthesized. The combined effect, that is, the output current from the voltage-current conversion element is directly or indirectly added to the delay generation section 11 as the control signal S3, and the delay amount τd is adjusted.

For example, main components of the delay adjustment circuit 13 and the temperature compensation circuit 14 can be formed including a voltage-current conversion element, and the output current from the synthesis circuit 23 can be current-voltage converted so as to be applied to the delay generation section 11 as a voltage bias. FIG. 11 shows an example of the delay control unit 22 and the combination circuit 23 in this configuration.

FIG. 11 is a circuit block diagram showing a first example of the delay control section according to this exemplary embodiment. Hereinafter, an explanation is provided with reference to FIGS. 10 and 11 .

The delay control unit 22 has a delay adjustment circuit 13 and a temperature compensation circuit 14 . Combining circuit 23 has combining section 23' and resistor 23". This is an example of an extremely simple circuit configuration. In this example, each of delay adjustment circuit 13 and temperature compensating circuit 14 includes NMOS transistors 2h, 2i. In addition, combining The portion 23' is formed of wiring connected in a T-letter shape. In addition, the resistor 23" constitutes a current-voltage conversion portion.

With the structure of this example, the output current from the delay adjustment circuit 13 and the output current from the temperature compensation circuit 14 are synthesized at the combining section 23" formed of wiring. The combined current flows in the resistance 23" serving as the current-voltage converting section , Therefore, the voltage output from the resistor 23" is changed. This makes it possible to obtain the voltage controlled by the delay adjustment circuit 13 and the temperature compensation circuit 14 (ie, the control signal S3). The control signal S3 is output to another circuit 24 and so on.

The resistor 23" can be changed to a diode-connected transistor, an OP amplifier, etc. In particular, when the resultant current value is a low current, it is desirable to use an OP amplifier.

(Third Exemplary Embodiment)

FIG. 12 is a block diagram showing a variable delay array according to a third exemplary embodiment of the present invention. Hereinafter, description will be provided with reference to the accompanying drawings.

The variable delay array 30 of this exemplary embodiment is configured with a plurality of delay elements 10 of the first exemplary embodiment connected in series. Instead of the delay element 10, the delay element 20 (FIG. 10) of the second exemplary embodiment may also be used. Note here that a variable delay array is also called a variable delay line. That is, the third exemplary embodiment of the present invention is a variable delay array 30 having delay elements 10 connected in series. Two inverters 31 connected on the output side are used to shape rising and falling of the waveform, and those inverters need not be provided. The same control bias (ie, control signal S0 of FIG. 1 ) is applied to each of all delay elements 10 . However, a separate control bias can also be applied. Furthermore, although only one control bias voltage is exemplified in this figure, bias voltages may be separately applied to the delay adjustment circuit 13 and the temperature compensation circuit 14 shown in FIG. 1 .

When the delay is controlled by voltage, the variable delay array 30 may also be called a voltage-controlled delay line. By changing the voltage used for control, the amount of delay of the output signal relative to the input signal can be changed. In the case where an output is also taken from a junction between a plurality of delay elements 10 connected in series, a plurality of outputs having different delay amounts can be obtained. For multiple outputs with different delay amounts, the delay amount can be changed instantly by changing the voltage used for control. For example, when the delay amount through the delay elements 10 is Y at a certain control voltage, the output after two connected delay elements 10 is "2Y", and the output after four connected delay elements 10 is "2Y". 4Y". In the case where the delay amount becomes “Y+ΔY”, the output after two connected delay elements 10 is “2×(Y+ΔY)”, and the output after four connected delay elements 10 is “4 ×(Y+ΔY)".

(Fourth Exemplary Embodiment)

FIG. 13 is a block diagram showing a variable delay array according to a fourth exemplary embodiment of the present invention. Hereinafter, description will be provided with reference to this figure.

The variable delay array 32 of this exemplary embodiment is configured with a plurality of delay elements 10 of the first exemplary embodiment connected in series. However, the delay elements 10 include a single delay control section 12 common to each of the delay elements 10 . The delay control section 12 controls the respective delay amounts by outputting the control signal S3 to each of the delay generation sections 11 supplied to the respective delay elements 10 . That is, the fourth exemplary embodiment is a variable delay array 32 formed by connecting a plurality of delay controllable delay generation sections 11 in series and by connecting a delay adjustment circuit 13 and a temperature compensation circuit 14 in series for the delay control section 12. constitute.

As in the case of the third exemplary embodiment shown in FIG. 12 , two inverters 31 connected on the output side are used for rising and falling of the shaped waveform, and it is not necessary to provide those inverters. The control signal S3 is applied to each of all the delay generation sections 11 from a circuit in which the delay adjustment circuit 13 and the temperature compensation circuit 14 are connected in series. In other words, in the fourth exemplary embodiment, only the delay generation sections 11 of the plurality of first exemplary embodiments are connected in series, and the same delay adjustment circuit 13 and temperature compensation circuit 14 are commonly used for all the delay generation sections 11.

(Fifth Exemplary Embodiment)

FIG. 14 is a block diagram showing a variable delay array according to a fifth exemplary embodiment of the present invention. Hereinafter, description will be provided with reference to this figure.

The variable delay array 33 of this exemplary embodiment is configured with a plurality of delay elements 20 of the second exemplary embodiment connected in series. However, the delay elements 20 include a single delay control section 22 common to each of the delay elements 20 . The delay control section 22 controls the respective delay amounts by outputting the control signal S3 to each of the delay generation sections 11 supplied to the respective delay elements 20 via the combining circuit 23 . That is, unlike the case of the fourth exemplary embodiment, the fifth exemplary embodiment is a variable delay array 33 configured in such a manner that the delay control section 22 having the delay adjustment circuit 13 and the temperature compensation circuit 14 arranged in parallel Connect to synthesis circuit 23.

As in the case of the third exemplary embodiment shown in FIG. 12 , two inverters 31 connected on the output side are used for rising and falling of the shaped waveform, and it is not necessary to provide those inverters. The control signal S3 is applied to each of all the delay generation sections 11 from the synthesis circuit 23 in which the delay adjustment circuit 13 and the temperature compensation circuit 14 are connected in parallel. In other words, in the fifth exemplary embodiment, only the delay generation sections 11 of the plurality of second exemplary embodiments are connected in series, and the same delay adjustment circuit 13, temperature compensation circuit 14, and synthesis circuit 23 are common to all Delay generating section 11 .

(Sixth Exemplary Embodiment)

FIG. 15 is a block diagram showing a voltage controlled oscillator (VCO) according to a sixth exemplary embodiment of the present invention. FIG. 16 is a block diagram showing an oscillator related to a sixth exemplary embodiment of the present invention. Hereinafter, explanations are provided with reference to the accompanying drawings.

The voltage controlled oscillator 35 of this exemplary embodiment is configured with the variable delay array 30 of the third exemplary embodiment, comprising a closed loop in which the output of one of the plurality of delay elements 10 is connected to that delay input to one of the delay elements of the subsequent stage of the element. In this exemplary embodiment, among the plurality of delay elements 10 , the output terminal of the delay element 10 of the last stage is connected to the input terminal of the delay element 10 of the first stage. Instead of the delay element 10 of the first exemplary embodiment, the delay element 20 of the second exemplary embodiment may also be used.

In other words, the sixth exemplary embodiment of the present invention is a voltage controlled oscillator 35 in which a plurality of delay elements 10 are connected in series to form a closed loop. As shown in FIG. 16, the oscillator 950 can be realized by forming a closed loop using an odd number of inverting type delay elements 951. Instead of using the inverting-type delay element 951, the voltage-controlled oscillator 35 may also be realized using the delay element 10 whose delay amount can be adjusted.

In this exemplary embodiment, three delay elements 10 are connected in series to form a closed loop. A control bias voltage is supplied to each of the delay elements 10 from the outside. A signal at a frequency corresponding to the structure of the closed loop can be taken from the output. By controlling the bias voltage, the frequency of the output signal can be changed.

The connection method in the closed loop in this exemplary embodiment changes depending on the structure of the delay element to be used, particularly the structure of the delay generation section within the delay element. Hereinafter, some situations will be described with reference to the accompanying drawings.

First, a case where the delay generation section uses an inverting element such as an inverter as a basic structure will be described. That is, the case of using the delay generating section shown in FIGS. 3 to 7 . Here, a voltage-controlled delay element using a delay generating section including those inverter circuits as a basic structure is called a voltage-controlled type inverter element. Fig. 17 is a circuit block diagram showing a first example of the sixth exemplary embodiment according to the present invention. Hereinafter, description will be provided with reference to the accompanying drawings.

By using the voltage-controlled inverting element 36 as the delay element 10, the voltage-controlled oscillator 35a of this example forms a closed loop. The voltage-controlled inverting element 36 is exemplified as an inverter having one terminal for applying a bias voltage in order to control a delay amount. In the closed loop using the voltage-controlled inverting elements 36 , both ends of the odd-numbered and serially connected voltage-controlled inverting elements 36 (ie, delay generating sections) are connected so as to form a closed loop. An odd number of voltage-controlled inverting elements 36 connected cannot maintain a logic stable state, and therefore, those elements oscillate at a frequency determined by the configuration of the circuit and the like.

Next, a case where the delay generation section has a differential input will be described. That is, use the case of the delay generating section as in FIG. 8 . FIG. 18 is a circuit block diagram showing a second example of the sixth exemplary embodiment of the present invention. Hereinafter, an explanation is provided by referring to the accompanying drawings.

The voltage controlled oscillator 35 b of this example forms a closed loop by using the differential input type delay element 37 as the delay element 10 . The differential input type delay element 37 has two inputs (inversion (-) input and non-inversion (+) input) and two outputs (inversion (-) output and non-inversion (+) output). In addition, the differential input type delay element 37 has a delay control section for adjusting the delay amount. In this example, an odd number of differential input type delay elements 37 is used to form a closed loop. However, the differential input type delay element 37 has two terminals (the inverting terminal and the non-inverting terminal), so even if there is an even number of elements, by connecting the inverting output of the last stage to the non-inverting input of the first stage and connecting the last The non-inverting output of the first stage is connected to the inverting input of the first stage, which can also realize the oscillation action. In this example, a differential input type delay element 37' having no function of adjusting the delay amount is connected to the final stage to obtain an output.

Finally, a case where the delay generation section is configured with two transistors as shown in FIG. 9 will be described. In this case, the structure becomes less complicated compared with the cases of FIGS. 17 and 18 . Fig. 19 is a circuit block diagram showing a third example of the sixth exemplary embodiment according to the present invention. Hereinafter, description will be provided with reference to the accompanying drawings.

The voltage controlled oscillator 35c of this example forms a closed loop by using the delay generation section 11f configured with two transistors as in the case of FIG. 9 . That is, the voltage controlled oscillator 35c of this example uses two delay elements, and each has a delay generator 11f in which two transistors are arranged. Three inverters are respectively connected to the later stages of those delay generating sections 11f. The three inverters include a single inverter 38 with a low threshold and two inverters 39 with a normal threshold.

Using an inverter 38 with a low threshold makes it possible to prevent the rising edge of the signal from being mainly determined by the bias voltages B11 and B12. Two inverters 39 with common thresholds at the latter stage are used to shape the waveform and correct the polarity of the signal.

This structure having the delay generating section 11f and the inverters 38, 39 is used as one unit. The voltage controlled oscillator 35c is formed by using two units. The output of the first unit is input to the second unit, and the output of the second unit is input to the first unit. This makes it possible to form the voltage-controlled oscillator 35c capable of adjusting the amount of delay in both directions (rising and falling). That is, with this example, a single delay element has an extremely simple structure. However, it is necessary to set inverters of different thresholds in the peripheral portion.

(Seventh Exemplary Embodiment)

FIG. 20 is a block diagram showing a voltage controlled oscillator according to a seventh exemplary embodiment of the present invention. Hereinafter, explanation is provided by referring to this figure.

The voltage controlled oscillator 40 of this exemplary embodiment is configured with the variable delay array 32 of the fourth exemplary embodiment, including the output terminal in which one of the plurality of delay elements 10 is connected to the output terminal in the subsequent stage of that delay element. A closed loop at the input of one of the delay elements. In this exemplary embodiment, among the plurality of delay elements 10 , the output terminal of the delay element 10 of the last stage is connected to the input terminal of the delay element 10 of the first stage.

However, the delay elements 10 include a single delay control section 12 common to each of the delay elements 10 . The delay control section 12 controls the respective delay amounts by outputting the control signal S3 to each of the delay generation sections 11 supplied to the respective delay elements 10 .

In other words, the seventh exemplary embodiment of the present invention is a voltage controlled oscillator 40 in which a plurality of delay elements 10 having a delay generation section 11 and capable of controlling the delay from the outside are connected in series in such a manner that closed loop. The voltage controlled oscillator 40 is configured to have a delay control section 12 capable of externally controlling the delay, which has a delay adjustment circuit 13 and a temperature compensation circuit 14 connected in series. The voltage controlled oscillator 40 is characterized in that the control signal S3 is transmitted from a single control section to all delay elements 11 .

That is, a plurality of delay generating sections 11 are connected in series to form a closed loop in this way. A control signal S3 as a control bias is applied to all the delay generation sections 11 from a circuit in which the delay adjustment circuit 13 and the temperature compensation circuit 14 are connected in series. As described, the seventh exemplary embodiment is configured to have only the delay generation section 11 of the first exemplary embodiment connected in series so as to form a closed loop, and the same delay adjustment circuit 13 and temperature compensation circuit 14 Common to all delay generators 11 . With this structure, a circuit in which the delay adjustment circuit 13 and the temperature compensation circuit 14 are connected in series is used for all the delay generation sections 11 .

(Eighth Exemplary Embodiment)

FIG. 21 is a block diagram showing a voltage controlled oscillator according to an eighth exemplary embodiment of the present invention. Hereinafter, explanation is provided by referring to this figure.

The voltage-controlled oscillator 41 of this exemplary embodiment is configured with the variable delay array 33 of the fifth exemplary embodiment, including the output terminal in which one of the plurality of delay elements 20 is connected to the output terminal in the subsequent stage of that delay element. A closed loop at the input of one of the delay elements. In this exemplary embodiment, among the plurality of delay elements 20 , the output terminal of the delay element 20 of the last stage is connected to the input terminal of the delay element 20 of the first stage.

However, the delay elements 20 include a single delay control section 22 common to each of the delay elements 20 . The delay control section 22 controls each delay amount by outputting the control signal S3 to each of the delay generation sections 11 supplied to the respective delay elements 20 via the synthesis circuit 23 .

In other words, the voltage controlled oscillator 41 of the eighth exemplary embodiment of the present invention differs from the voltage controlled oscillator 40 ( FIG. 20 ) of the seventh exemplary embodiment in the delay adjustment circuit 13 and the temperature compensation circuit 14 It is connected to the synthesis circuit 23 in parallel. In the eighth exemplary embodiment, a plurality of delay generation sections 11 are connected in series, forming a closed loop in this way. A control signal S3 as a control bias is applied to each of all the delay generation sections 11 from the synthesis circuit 23 connected in parallel to the delay adjustment circuit 13 and the temperature compensation circuit 14 .

As described, the eighth exemplary embodiment of the present invention is configured such that only the delay generation section 11 of the second exemplary embodiment is connected in series to form a closed loop, and the delay adjustment circuit 13 , the temperature compensation circuit 14 , and the combining circuit 23 Common to all delay generators 11 . With this structure, a circuit to which the delay adjustment circuit 13 and the temperature compensation circuit 14 are connected in series is used for all the delay generation sections 11 .

In each of the above-described exemplary embodiments, instead of using the delay elements 10 and 20 , a delay amount interpolation type delay element may also be used. FIG. 22 is a circuit block diagram showing another example of the delay element described in each of the exemplary embodiments.

The delay amount interpolation type delay element 25 of this example includes the plurality of delay elements 10 and the adder 26 of the first exemplary embodiment. In this example, two delay paths (ie, path 27 with a small delay amount arranged with a single delay element 10 and path 28 with a large delay amount arranged with two delay elements 10 ) are formed. For example, by synthesizing signals of two paths having different delay amounts by the adder 26 and interpolating the delay amounts with each other, the delay amount can be adjusted in a precise manner. The delay amount of the delay element 10 is adjusted by a control bias voltage from the outside to finely adjust the delay amount over an extremely wide range. The delay element 20 ( FIG. 10 ) of the second exemplary embodiment may also be used instead of the delay element 10 of the first exemplary embodiment.

(Ninth Exemplary Embodiment)

In the voltage controlled oscillator according to the ninth exemplary embodiment of the present invention, at least some or all of the transistors included in the delay adjustment circuit or the temperature compensation circuit of each of the above-described exemplary embodiments are multi-gate type transistors. That is, this exemplary embodiment uses a multi-gate type transistor having a plurality of gate electrodes. A multi-gate transistor as a circuit is equivalent to a structure in which a plurality of transistors having a plurality of gates and whose gates are connected to each other are connected in series. By using a multi-gate transistor, good characteristics can be obtained even when the source-drain voltage is increased.

FIG. 23 is a graph showing an example of the relationship between the gate voltage and the drain current of a single-gate transistor. FIG. 24 is a graph showing an example of the relationship between the gate voltage and the drain current of a multi-gate transistor. Hereinafter, explanations are provided by referring to the graphs. Note here that the graphs in FIG. 23 and FIG. 24 each represent the characteristics of a PMOS transistor, and the drain voltage is changed in each graph.

With a single gate transistor, the curve of gate voltage and drain current changes greatly as the drain voltage increases. In particular, for the same drain voltage, when the gate voltage increases from -5V to -10V, there is a change in the drain current ranging from 1 digit to 2 digits. The state of the curve is also changed, thus increasing the non-linearity of the characteristic with respect to the drain voltage.

These changes are suppressed by the double gate transistor. Therefore, these variations can be accounted for by a range of less than 1 digit under the same conditions. In addition, the variation of the curve is reduced so that the nonlinearity of the characteristic with respect to the drain voltage becomes reduced, thereby increasing the linearity. As mentioned, the use of multi-gate transistors provides good linearity of the drain current when there are variations in the source-drain voltage. Therefore, the controllability of the voltage controlled oscillator itself can be improved.

In addition, a multi-gate transistor may be used in part or all of the circuits connecting the bias voltage applying unit and the closed loop circuit of the voltage controlled oscillator of the present invention. When the linearity of the connected circuit is improved by using a multi-gate transistor for the circuit connecting the bias voltage applying section and the closed loop circuit, the linearity of the entire voltage controlled oscillator is improved. In particular, good characteristics can be obtained when the connection circuit for mutual conversion of voltage and current is a multi-gate transistor.

(Tenth Exemplary Embodiment)

In the voltage controlled oscillator according to the tenth exemplary embodiment of the present invention, at least some or all of the transistors included in the delay adjustment circuit or the temperature compensation circuit of each of the above-mentioned exemplary embodiments are configured with two The structure of the symmetrical load of the transistor. In a symmetrical load, the sources of the two transistors and their drains are connected to each other in parallel, and one of the transistors is diode connected. This structure is also known as a Maneatis resistor.

FIG. 25 is a circuit block diagram showing an example of a symmetrical load in which two transistors are arranged. Hereinafter, description will be provided with reference to this figure.

In the symmetrical load 45 of this example, the sources and drains of the two PMOS transistors are connected to each other so as to form a parallel structure, and the PMOS transistor 1a is diode-connected. With this, when the resistance control bias applied to the PMOS transistor 1b is changed, the resistance value between the source and the drain becomes highly linear, changing almost linearly with respect to the resistance control bias. Therefore, characteristics close to linear resistance can be obtained. When such a symmetrical load 45 is used, a resistance that varies almost linearly with respect to the delay adjustment bias and the temperature compensation bias can be used. Therefore, the accuracy of control can be improved, whereby characteristics with high linearity can be obtained.

(Eleventh Exemplary Embodiment)

The voltage controlled oscillator according to the eleventh exemplary embodiment of the present invention has the structure of the seventh exemplary embodiment, in which the delay adjustment circuit and the temperature compensation circuit according to each of the above-described embodiments are connected in series and the control signal is transferred from A single control section passes to all delay elements, wherein some or all of the transistors included in the control section are symmetrical loads configured with two transistors.

The eleventh exemplary embodiment uses symmetrical loads for the control section or synthesis circuit. Therefore, the linearity of the signal transmitted to the closed loop provided with the delay element can be improved, thereby improving the linearity of the oscillation frequency. That is, part or all of the circuits connecting the bias voltage applying section or the closed loop circuit are configured to have a diode-connected transistor and a transistor whose source and drain are connected to each other so as to be connected in parallel, and therefore, good characteristics can be obtained.

(Twelfth Exemplary Embodiment)

A voltage controlled oscillator according to a twelfth exemplary embodiment of the present invention has the structure of the eighth exemplary embodiment, in which a delay adjustment circuit and a temperature compensation circuit are connected in parallel to a synthesizing circuit, wherein the Some or all of the transistors are symmetrical loads configured with two transistors.

The twelfth exemplary embodiment uses symmetrical loads for the control section or synthesis circuit. Therefore, the linearity of the signal transmitted to the closed loop provided with the delay element can be improved, thereby improving the linearity of the oscillation frequency. That is, part or all of the circuits connecting the bias voltage applying section and the closed loop circuit are configured to have a diode-connected transistor and a transistor whose source and drain are connected to each other so as to be connected in parallel, and therefore, good characteristics can be obtained.

(Thirteenth Exemplary Embodiment)

A thirteenth exemplary embodiment of the present invention is the voltage-controlled oscillator according to one of the sixth to twelfth exemplary embodiments described above, and it is a voltage-controlled oscillator controlled by an analog signal.

(Fourteenth Exemplary Embodiment)

A fourteenth exemplary embodiment of the present invention is the voltage-controlled oscillator according to one of the above-described sixth to twelfth exemplary embodiments, and it is a voltage-controlled oscillator controlled by a digital signal.

(Fifteenth Exemplary Embodiment)

A fifteenth exemplary embodiment of the present invention is a display device in which a display unit and a temperature compensation function circuit using one of the first to fourteenth exemplary embodiments are integrally formed. The functional circuit unit whose temperature characteristic is compensated includes the voltage-controlled oscillator according to one of the first to fourteenth exemplary embodiments, a variable delay line, a delay element, and the like. Other functional circuits whose temperature characteristics are compensated may also be included. By integrally forming a display unit and such a functional circuit unit whose temperature characteristic is compensated, a display device whose temperature characteristic can be compensated can be realized. That is, the temperature characteristic of the functional circuit unit is compensated, and when necessary, the temperature characteristic of the display unit can be compensated by the functional circuit unit.

Such display devices operate extremely well over an extremely wide range of temperatures. The temperature sensor may be integrally formed with the display unit or the functional circuit unit, or may be provided externally. In particular, when provided integrally, it is desirable that the temperature sensor and the circuit unit that outputs a temperature compensation bias voltage according to the output of the temperature sensor itself have characteristics of resistance to temperature changes. Alternatively, it may be configured such that supply of the temperature compensation bias voltage is automatically triggered by a characteristic change caused by a temperature change in the temperature sensor and components in the circuit that output the temperature compensation bias voltage based on the output of the temperature sensor.

With a conventional display device in which a functional circuit unit and a display unit are integrally formed, insufficient operation or erroneous operation of various functional circuit units often occurs. One reason is that there are variations in temperature of various functional circuit units. That is, various functional circuits are integrally formed with the display unit such that the functional circuit unit is subjected to temperature changes close to the display unit. In addition, the temperature of various functional circuit units changes due to heat generated when power is consumed in the various functional circuit units themselves.

Subjecting to temperature changes close to the display unit means subject to temperature close to the external environment, since the display unit is arranged to be viewed by the human eye. The external ambient temperature is the temperature at which the display device is guaranteed to operate. It's sub-zero temperatures and sometimes reaches 60 degrees Celsius or more. Meanwhile, in many cases, a display unit is provided with a light source such as a backlight or a front light, thus subjecting the functional circuit unit to a temperature increase caused by heat generated by the light source. The temperature increase caused by the light source can vary from a few degrees to tens of degrees, depending on the structure of the display device.

When a temperature compensation circuit and a temperature sensor element provided outside the display device are used as a measure to take such temperature change into account, since the detected temperature is different from that of the functional circuit unit, it is difficult to perform sufficient temperature compensation. The fifteenth exemplary embodiment of the present invention can overcome the problems of the display device in which the functional circuit unit and the display unit are integrally formed.

(Sixteenth Exemplary Embodiment)

The sixteenth exemplary embodiment of the present invention relates to a system and various devices using the display device of the fifteenth exemplary embodiment as one of structural modules. By using the display device of the fifteenth exemplary embodiment, various devices and systems can operate in a good manner even if there is a temperature change. Therefore, it is possible to realize a device and a system whose display is not disturbed even under a harsh external environment, or even if there is an increase in the temperature of the device itself, or the like. Such a system does not require an external clock in normal operation. Usually, an external clock is provided by a crystal oscillator provided externally. When an external clock element such as a crystal oscillator is used, not only does the cost increase, but also a circuit for reducing the clock frequency is required because the external clock element operates at a frequency higher than that of the internal circuit of the device. If these circuits are added, the structure of the device becomes complicated, and at the same time, since the circuits operate at high frequencies, power consumption increases. In this exemplary embodiment, since an external clock element is not required, cost can be reduced, and power consumption can be reduced. Also, only when calibrating the system, by connecting to an external clock, the internal oscillation frequency can be corrected by an external clock. This makes it possible to provide a stable system for a long time. As described, only when the system is calibrated, even if configured to use an external clock, in normal operation, lower power consumption can be achieved compared to the conventional case.

Hereinafter, specific embodiments of the present invention will be described with reference to the accompanying drawings.

(Example 1)

Fig. 26 is a circuit block diagram showing a voltage controlled oscillator according to Embodiment 1 of the present invention. 27 to 30 are graphs showing the relationship between the control bias voltage and the oscillation frequency in the first embodiment. Hereinafter, explanations are provided by referring to those drawings.

Example 1 is a more specific example embodying the first exemplary embodiment ( FIGS. 1 to 9 ), the sixth exemplary embodiment ( FIG. 15 ), the ninth exemplary embodiment ( FIG. 24 ), and the like. Embodiment 1 uses a current-limited inverter as an inverting-type delay element, that is, the delay generating section 11 a of FIG. 3 . An odd number (for example, 31) of delay generators 11 a forms a closed loop. As in the case of FIG. 2, the PMOS transistors 1f and 1g constitute a current mirror circuit. In addition, the PMOS transistor 1f and the NMOS transistor 2j convert current into voltage. A bias voltage B1 as a control bias voltage for adjusting the frequency is applied to the NMOS transistor 2f. A bias voltage B2 for compensating temperature characteristics is applied to the NMOS transistor 2g. This structure can provide a voltage-controlled oscillator that can change the oscillation frequency by controlling the control voltage applied to the current-limited inverter.

FIG. 27 shows the relationship between the control bias (bias B1) and the oscillation frequency in the first embodiment. Referring to FIG. 27 , corresponding to the control bias voltage being varied in the range of 1V to 3.5V, the oscillation frequency is greatly varied in the frequency range of 1.5MHz to 7.5MHz. Oscillation was not obtained when the control bias was lower than 1V. Meanwhile, when the bias voltage was 3.5 V or higher, the oscillation frequency showed little change even if the control bias voltage was changed.

Figure 27 shows the results obtained at room temperature (27 degrees Celsius). Next, the performance change with respect to temperature is investigated. 28 shows the relationship between the control bias (bias B1) and the oscillation frequency of Embodiment 1 when the temperature is changed from 0°C to 80°C at intervals of 20°C while fixing the bias (bias B2) for compensating the temperature characteristic. Relationship. As can be seen from Fig. 28, the oscillation frequency greatly changes when the temperature changes. In addition, at a small control bias, there may be cases where oscillation cannot be obtained when the temperature is changed to the low temperature side. As described, without performing temperature compensation, when there is a large temperature change, the oscillation frequency greatly changes. Therefore, it becomes difficult to use the oscillator stably.

To handle this temperature change, the present invention applies a temperature compensating bias. As in the case of FIG. 28, FIG. 29 shows the control bias (bias B1) when the temperature is changed from 0°C to 80°C at intervals of 20°C when the temperature characteristic is compensated by using the bias voltage (bias B2) for compensating the temperature characteristic. ) and the relationship between the oscillation frequency. In FIG. 29, a temperature compensating bias is applied that provides an almost constant oscillation frequency when the control bias is 2V even when the temperature changes. Therefore, the change in oscillation frequency when there is a temperature change becomes significantly smaller compared to the case of FIG. 28 .

FIG. 30 shows the relationship between temperature and frequency with respect to the case of applying and not applying the temperature compensating bias when the control bias is fixed at 2V. As can be seen from FIG. 30 , when the temperature compensation bias is not applied, the oscillation frequency changes almost twice as the temperature changes from 20 degrees Celsius to 80 degrees Celsius, and no oscillation is obtained at 0 degrees Celsius. Meanwhile, when the temperature compensation bias is applied, the oscillation frequency becomes stable at about 6 MHz even if the temperature changes.

(comparative example 1)

FIG. 31 is a circuit block diagram showing a voltage controlled oscillator according to Comparative Example 1. FIG. 32 and 33 are graphs showing the relationship between the control bias voltage and the oscillation frequency of Comparative Example 1. FIG. Hereinafter, explanations are provided with reference to the accompanying drawings.

The structure of Comparative Example 1 is the same as that of Example 1 except that the NMOS transistor 2g ( FIG. 26 ) of Example 1 is replaced by a resistor 46 . Comparative Example 1 also uses a current-limited inverter as an inverting-type delay element, that is, the delay generating section 11 a of FIG. 3 . An odd number (for example, 31) of delay generators 11 a forms a closed loop. As in the case of FIG. 2, the PMOS transistors 1f and 1g constitute a current mirror circuit. In addition, the PMOS transistor 1f and the NMOS transistor 2j convert current into voltage. A bias voltage B1 as a control bias voltage for adjusting the frequency is applied to the NMOS transistor 2f. However, unlike the case of Embodiment 1, the bias voltage B2 ( FIG. 26 ) for compensating the temperature characteristic is not used. This structure can provide a voltage-controlled oscillator that can change the oscillation frequency by controlling the control voltage applied to the current-limited inverter.

FIG. 32 shows the relationship between the control bias voltage and the oscillation frequency in Comparative Example 1. FIG. Referring to FIG. 32 , corresponding to a change in the control bias voltage in the range of 1.5V to 4V, the oscillation frequency changes almost linearly. Figure 32 shows the results obtained at room temperature (27 degrees Celsius).

Next, FIG. 33 shows the relationship between the control bias voltage and the oscillation frequency when the temperature is changed from 0°C to 80°C at intervals of 20°C. When there is a temperature change, the oscillation frequency changes greatly. Especially at low temperatures, it often happens that oscillation cannot be obtained.

Unlike the case of Example 1, Comparative Example 1 cannot apply a temperature compensation bias. Therefore, a change in the oscillation frequency caused when there is a temperature change cannot be suppressed. Measures may also be used to compensate for temperature by external circuits other than those shown in FIG. 31 . In that case, however, compared with the case of Embodiment 1, the circuit becomes more complicated and the circuit scale is increased. For example, between the structures of Patent Document 1 and Embodiment 1, the complexity of the circuit is greatly different.

(Example 2)

Fig. 34 is a circuit block diagram showing a voltage controlled oscillator according to Embodiment 2 of the present invention. 35 to 37 are graphs showing the relationship between the control bias voltage and the oscillation frequency in the second embodiment. Hereinafter, explanations are provided by referring to those drawings.

Embodiment 2 has the same structure as Embodiment 1 except that NMOS transistors 2f, 2g (FIG. 26) of Embodiment 1 are replaced by NMOS transistors 21, 2m of double gate transistors. Embodiment 2 also uses a current-limited inverter as an inverting-type delay element, that is, the delay generation section 11 a of FIG. 3 . An odd number (for example, 31) of delay generators 11 a forms a closed loop. As in the case of FIG. 2, the PMOS transistors 1f, 1g constitute a current mirror circuit. In addition, the PMOS transistor 1f and the NMOS transistor 2j convert current into voltage. A bias voltage B1 as a control bias voltage for adjusting the frequency is applied to the NMOS transistor 2l. A bias voltage B2 for compensating temperature characteristics is applied to the NMOS transistor 2m. This structure can provide a voltage-controlled oscillator that can change the oscillation frequency by controlling the control voltage applied to the current-limited inverter.

FIG. 35 shows the relationship between the control bias voltage and the oscillation frequency in the second embodiment. Referring to FIG. 35 , corresponding to a change in the control bias voltage in the range of 1.5V to 4V, the oscillation frequency greatly changes in the range of slightly higher than 1 MHz to slightly lower than 7 MHz. There was no oscillation when the control bias was lower than 1.5V, and when the bias was 4V or higher, the oscillation frequency showed little change even when the control bias was changed.

Figure 35 shows the results obtained at room temperature (27 degrees Celsius). Next, changes in characteristics with respect to temperature are studied. 36 shows the relationship between the control bias and the oscillation frequency of Embodiment 2 when the temperature is changed from 0°C to 80°C at 20°C intervals while fixing the bias voltage (bias B2) for compensating the temperature characteristic. As seen from Fig. 36, the oscillation frequency greatly changes when the temperature changes. In addition, at a small control bias, there may be cases where oscillation cannot be obtained when the temperature is changed to the low temperature side. As described, under the condition that temperature compensation is not performed, when there is a large temperature change, the oscillation frequency greatly changes. Therefore, it becomes difficult to use the oscillator stably.

However, the temperature dependence in FIG. 36 is mitigated compared to Example 1 shown in FIG. 28 . This is because a double-gate transistor, which is a multi-gate type transistor, is used for the bias voltage applying section. That is, improvement in the linearity of drain current achieved by using a multi-gate type transistor serves to obtain good results with respect to current variation due to temperature dependence.

To handle these temperature changes, the present invention applies a temperature compensating bias. As in the case of FIG. 36 , FIG. 37 shows the control bias voltage and when the temperature is changed from 0 degrees Celsius to 80 degrees Celsius at intervals of 20 degrees while compensating the temperature characteristic by using the bias voltage (bias B2 ) for compensating the temperature characteristic. The relationship between the oscillation frequency. In FIG. 37, the temperature compensation bias is applied such that when the control bias is 3.3V, an almost constant oscillation frequency can be provided even if the temperature changes. Therefore, the change in oscillation frequency when there is a temperature change becomes significantly smaller compared to FIG. 36 .

When the case of Embodiment 1 shown in FIG. 29 in which temperature compensation is performed is compared with the case of Embodiment 2 shown in FIG. 37 in which temperature compensation is performed, it can be seen that with Embodiment 2, when the control deviation When the pressure is different from the predetermined value, the variation of the oscillation frequency at 20 degrees Celsius and 80 degrees Celsius is smaller. That is, when the control bias voltage is higher than the predetermined value, there is only about a 10% difference between the oscillation frequencies at temperatures between 20°C and 80°C by Example 2, and a difference of about 20% by Example 1 value. This is also an effect obtained by using a multi-gate type transistor. Since there are only small variations in the oscillation frequency, it is easy to fix the frequency at the desired frequency. Therefore, Embodiment 2 can provide better frequency stability than Embodiment 1.

(Example 3)

Fig. 38 is a circuit block diagram showing a voltage controlled oscillator according to Embodiment 3 of the present invention. 39 to 41 are graphs showing the relationship between the control bias voltage and the oscillation frequency in the third embodiment. Hereinafter, explanations are provided by referring to those drawings.

Embodiment 3 has the same structure as Embodiment 1, except that the NMOS transistor 2f (FIG. 26) of Embodiment 1 is replaced by a symmetrical load provided with NMOS transistors 2f, 2f', and the NMOS transistor 2g (FIG. 26 ) is replaced by a symmetrical load configured with NMOS transistors 2g, 2g'. Embodiment 3 also uses a current-limited inverter as an inverting-type delay element, that is, the delay generating section 11 a of FIG. 3 . An odd number (for example, 31) of delay generators 11 a forms a closed loop. As in the case of FIG. 2, the PMOS transistors 1f and 1g constitute a current mirror circuit. In addition, the PMOS transistor 1f and the NMOS transistor 2j convert current into voltage. A bias voltage B1 as a control bias voltage for adjusting the frequency is applied to the NMOS transistor 2f. A bias voltage B2 for compensating temperature characteristics is applied to the NMOS transistor 2g. This structure can provide a voltage-controlled oscillator that can change the oscillation frequency by controlling the control voltage applied to the current-limited inverter.

In Embodiment 3, NMOS transistors 2f', 2g' are added in a diode-connected form, thereby constituting a symmetrical load together with the NMOS transistors 2f and 2g. NMOS transistors 2f' and 2g' are added in order to obtain the performance that the current changes almost linearly with respect to the applied bias voltage.

Fig. 39 shows the relationship between the control bias voltage and the oscillation frequency in the third embodiment. Referring to FIG. 39 , corresponding to changes in the control bias voltage in the range of 1.5V to 4V, the oscillation frequency changes almost linearly. When the control bias is lower than 1.5V, or is 4V or more, the oscillation frequency hardly changes even if the control bias is changed. Compared with Embodiment 1 and Embodiment 2, Embodiment 3 is far different in that oscillation can be obtained even when the control bias voltage is small.

In Embodiment 3, there are some characteristic points different from Embodiment 1 and the like. The first characteristic point that will be specifically mentioned is that an oscillation signal can be obtained regardless of the value of the control bias voltage. That is, even if the control bias becomes small, oscillation can be obtained. Therefore, regardless of the value of the control bias voltage, an oscillation signal can be obtained so that stable operation can be performed. By the methods according to Example 1, Comparative Example 1, and Example 2, when the control bias voltage becomes smaller than a certain value, an oscillation signal cannot be obtained. Therefore, when the control bias deviates from the desired value for some reason, the voltage controlled oscillator loses its functionality. Meanwhile, with Embodiment 3, even if the control bias deviates from a desired value, an oscillation signal can be obtained, and therefore, the voltage-controlled oscillator can perform its function.

A second characteristic point to be specifically provided is that the variation of the oscillation frequency with respect to the variation of the control bias voltage is close to a linear form. That is, when the control bias voltage is in the range of 1.5V to 4V, the oscillation frequency changes almost linearly, and therefore, it is extremely easy to control the oscillation frequency by an external bias voltage. In other words, it is easy to linearly control the oscillation frequency. In the case where the oscillation frequency exhibits a complicated change with respect to the control bias, it is necessary to hold the relationship between the control bias and the oscillation frequency in a reference table (look-up table: LUT) or the like. Meanwhile, when the oscillation frequency varies approximately linearly as in Embodiment 3, no LUT or the like is required as long as the coefficients of the linear form are known.

A third characteristic point that will be specifically mentioned is that the gain of the change in the oscillation frequency is small with respect to the change in the control bias voltage. That is, with respect to the center frequency (for example, 6.1 MHz), the variation of the oscillation frequency caused by the control bias is slightly less than ±20%. This is extremely effective for adjustments where the oscillation frequency does not change significantly. In practice, voltage controlled oscillators are generally used where the oscillation frequency is changed by less than several times, for example, in the range of tens to several percent, rather than when the oscillation frequency is changed by 10 times.

Figure 27 shows the results obtained at room temperature (27 degrees Celsius). Next, the performance change with respect to temperature is investigated. 40 shows the relationship between the control bias (bias B1) and the oscillation frequency of Embodiment 3 when the temperature is changed from 0°C to 80°C at intervals of 20°C while fixing the bias (bias B2) for compensating the temperature characteristic. Relationship. As seen from Fig. 40, when the temperature is changed, the oscillation frequency is greatly changed between 2.5 MHz and 9.5 MHz. However, unlike the case of Embodiment 1, under a small control bias voltage, oscillation can still be obtained (ie, the above-mentioned first characteristic point can be ensured even if there is a change in temperature). As described, under the condition that temperature compensation is not performed, when there is a large temperature change, the oscillation frequency greatly changes. Therefore, it becomes difficult to use the oscillator stably.

To account for such temperature variations, the present invention applies a temperature compensating bias. As in the case of FIG. 40, FIG. 41 shows that when the temperature characteristic is compensated by using a bias voltage (bias B2) compensating for the temperature characteristic when the temperature is changed from 0 degrees Celsius to 80 degrees Celsius at intervals of 20 degrees, the control bias (bias B1 ) and the relationship between the oscillation frequency. In FIG. 41, the temperature compensation bias voltage is applied such that when the control bias voltage is 3V, an almost constant oscillation frequency can be provided even if the temperature varies. Therefore, the change in oscillation frequency when there is a temperature change becomes significantly smaller compared to FIG. 40 . In particular, when Example 1 shown in FIG. 29 is compared with Example 3 shown in FIG. 41, in FIG. 41, the variation of the oscillation frequency at each temperature with respect to the tendency of the control bias voltage is smaller . All frequencies fall almost in the range of 4.5MHz to 7.5MHz, except for the region of 0°C where the control bias is small. That is, according to the third embodiment, it is possible to realize a voltage-controlled oscillator that can be used regardless of temperature changes.

(Example 4)

Fig. 42 is a circuit block diagram showing a voltage controlled oscillator according to Embodiment 4 of the present invention. 43 to 46 are graphs showing the relationship between the control bias voltage and the oscillation frequency in the fourth embodiment. Hereinafter, explanations are provided by referring to those drawings.

The structure of Embodiment 4 is the same as that of Embodiment 1, except for the following, that is, the NMOS transistor 2f (FIG. 26) of Embodiment 1 is replaced by a symmetrical load equipped with NMOS transistors 2f, 2f', and the NMOS transistor 2g (FIG. 26 ) is replaced by a symmetrical load configured with NMOS transistors 2g, 2g', and the PMOS transistor 1g (Fig. 26) is replaced with a symmetrical load configured with PMOS transistors 1g, 1g'. Embodiment 4 also uses a current-limited inverter as an inverting-type delay element, that is, the delay generating section 11 a of FIG. 3 . An odd number (for example, 31) of delay generating sections 11 a forms a closed loop. As in the case of FIG. 2, the PMOS transistors 1f and 1g constitute a current mirror circuit. In addition, the PMOS transistor 1f and the NMOS transistor 2j convert current into voltage. A bias voltage B1 as a control bias voltage for adjusting the frequency is applied to the NMOS transistor 2f. A bias voltage B2 for compensating temperature characteristics is applied to the NMOS transistor 2g. This structure can provide a voltage-controlled oscillator that can change the oscillation frequency by controlling the control voltage applied to the current-limited inverter.

In Embodiment 4, NMOS transistors 2f' and 2g' are added in diode connection to constitute a symmetrical load together with NMOS transistors 2f and 2g, and a PMOS transistor 1g' is added in diode connection to constitute together with PMOS transistor 1g Symmetrical load. NMOS transistors 2f', 2g' and PMOS transistor 1g are added in order to obtain almost linear variation of performance with respect to applied bias current. In particular, when the PMOS transistor 1g' is added, the linearity of the junction between the closed loop and the bias voltage application part (NMOS transistors 2f, 2g) can be improved.

Fig. 43 shows the relationship between the control bias voltage and the oscillation frequency in the fourth embodiment. Referring to FIG. 43 , the oscillation frequency varies almost linearly in the range of 5.4MHz to 6.8MHz corresponding to the variation of the control bias voltage in the range of 2V to 4V. When the control bias voltage is less than 2V or 4V or greater than 4V, the oscillation frequency hardly changes even if the control bias voltage is changed. Unlike the cases of Embodiment 1 and Embodiment 2, even when the control bias voltage is small, oscillation can be obtained.

As in Embodiment 3, Embodiment 4 has some characteristic points far different from Embodiment 1 and the like. The first characteristic point specifically mentioned is that an oscillation signal can be obtained regardless of the value of the control bias voltage.

The second characteristic point specifically mentioned is that the variation of the oscillation frequency approaches a linear form with respect to the variation of the control bias voltage. That is, when the control bias is in the range of 2V to 4V, the oscillation frequency changes almost linearly, and therefore, it is extremely easy to control the oscillation frequency by the external bias. In other words, it is easy to linearly control the oscillation frequency. In particular, as can be seen from FIG. 43 , the linearity was improved compared to Example 3.

The third characteristic point specifically mentioned is that the gain of the change in the oscillation frequency is small with respect to the change in the control bias voltage. That is, the variation of the oscillation frequency caused by the control bias is about ±10% with respect to the center frequency (for example, 6.1 MHz), which is a smaller range. It is extremely effective in making adjustments without significant changes in the oscillation frequency.

Figure 43 shows the results obtained at room temperature (27 degrees Celsius). Next, changes in performance with respect to temperature were studied. 44 shows the control bias (bias B1) and oscillation of Embodiment 4 when the temperature is changed from 0°C to 80°C at intervals of 20°C while fixing the bias (bias B2) for compensating the temperature characteristic. relationship between frequencies. As seen from Fig. 44, the oscillation frequency greatly changes between 2 MHz and 10 MHz when the temperature changes. As in the case of Embodiment 3, oscillation can still be obtained even with a small control bias (ie, the above-mentioned first characteristic point can be ensured even if there is a change in temperature). As described, under the condition that temperature compensation is not performed, when there is a large temperature change, the oscillation frequency greatly changes. Therefore, it becomes difficult to use the oscillator stably.

To solve this temperature change, the present invention applies a temperature compensation bias. As in the case of FIG. 44 , FIG. 45 shows that the control bias (bias B1 ) and the relationship between the oscillation frequency. In FIG. 45, the temperature compensation voltage is applied such that when the control bias voltage is 3V, an almost constant oscillation frequency can be provided even if the temperature varies. Therefore, when there is a temperature change, the change in the oscillation frequency becomes significantly smaller compared to FIG. 44 . In particular, when Example 1 shown in FIG. 29 is compared with Example 4 shown in FIG. 45, in FIG. 45, the variation of the oscillation frequency at each temperature with respect to the tendency of the control bias voltage is smaller . All frequencies almost fall in the range of 5MHz to 7.5MHz, except for the region where the control bias is small at 0 degrees Celsius. That is, according to Embodiment 4, it is possible to realize a voltage-controlled oscillator that can be used almost without paying attention to temperature changes.

Fig. 46 shows the relationship between temperature and frequency with respect to the case of applying and not applying a temperature compensation bias when the control bias is fixed at 3V. As seen from FIG. 46 , when the temperature compensation bias was not applied, the oscillation frequency changed almost 2.5 times as the temperature was changed from 0°C to 80°C, and no oscillation was obtained at 0°C. Meanwhile, when a temperature compensation bias is applied, the oscillation frequency becomes stable at about 6 MHz even if there is a temperature change.

(Example 5)

FIG. 47 is a circuit block diagram showing a voltage controlled oscillator according to Embodiment 5. FIG. 48 and 49 are graphs showing the relationship between the control bias voltage and the oscillation frequency of the fifth embodiment. Hereinafter, explanations are provided by means of figures.

As described above, by the methods of Examples 1-4, compared with the case of Comparative Example 1, extremely good characteristics can be obtained. However, when the characteristics of a fabricated transistor differ from how it was designed (for example, when there is a variation in characteristics due to manufacturing variations or the like), the characteristics of the oscillation frequency become greatly different.

Embodiment 5 can provide voltage controlled oscillation that is also resistant to manufacturing variations. According to the inventor's estimation, Comparative Example 1 is more resistant to manufacturing variation than Example 1. The reason for this is considered as follows. That is, because the resistor used in Comparative Example 1 is likely to have smaller manufacturing variation than the transistor used in Example 1. This is due to differences in manufacturing conditions.

That is, polysilicon doped with a high concentration of carriers is generally used for a resistance element. At the same time, carriers are doped into the channel of the transistor at a lower concentration than the resistive element. Therefore, the channel of a transistor is relatively larger than that of a resistive element with respect to a change in doping concentration. Since this relative difference is promoted by the carrier activation process, it is considered that this change becomes more remarkable for transistors than for resistive elements.

Therefore, Example 5 was designed to increase resistance to manufacturing variation by adding resistance to Examples 1-4. FIG. 47 shows an example of a circuit obtained by adding a resistor 46 to the structure of Embodiment 4 (FIG. 47). Here, what is added is a resistor 46 having a resistance value at which the oscillation frequency of Example 4 under the conditions of a temperature compensation bias of 3 V and a control bias of 3 V is added. become half.

Fig. 48 shows the relationship between the control bias voltage and the oscillation frequency in the cases of Embodiment 4 (Fig. 42) and Embodiment 5 (Fig. 47). By adding the resistor 46, the oscillation frequency of Example 5 becomes about half of that of Example 4. However, the features described in Embodiment 4, which will be specifically mentioned below, are ensured: (1) an oscillation signal can be obtained regardless of the control bias voltage; (2) the change of the oscillation frequency is linear with respect to the change of the control bias voltage (3) Relative to the change of the control bias voltage, the gain of the change of the oscillation frequency is small.

Hereinafter, the performances of Embodiment 4 and Embodiment 5 when the characteristics of the transistor are greatly deteriorated will be shown. The deterioration of the transistors shown here is larger than usually measured and is considered as a special case. The resistance of each circuit to changes in transistor characteristics can be seen by observing the performance under such specific degradations. As deterioration of the transistor, in particular, a decrease in the threshold value of the PMOS transistor and an increase in the current in the peak region are observed.

After such deterioration, the performance in FIG. 48 changes to that shown in FIG. 49 . Fig. 49 shows the oscillation frequency obtained after deterioration as a performance shift. In the case of Example 4, the oscillation frequency after deterioration became about one-seventh of the initial oscillation frequency. Meanwhile, in the case of Example 5, the oscillation frequency after deterioration became about one-fifth of the initial oscillation frequency. Therefore, after deterioration, the difference between the frequencies of Example 4 and Example 5 is extremely small. In particular, for Example 4 and Example 5, although the ratio of frequencies at a control bias of 3V was 2:1, it became 1.26:1 after deterioration. As described, due to the use of resistors, Embodiment 5 does not face large performance changes even when there are deteriorations or changes in the characteristics of transistors.

The resistance connection method shown in Example 5 is only an example, and there are other various methods described below. Note here that the delay adjustment circuit is also referred to as a frequency control circuit. FIG. 50 shows an example of a circuit in which the resistor 46 is connected in parallel to the delay adjustment circuit 13 and the temperature compensation circuit 14 in series. FIG. 51 shows an example in which resistors 46a, 46b are respectively connected in series to delay adjustment circuit 13 and temperature compensation circuit 14 which are connected in parallel as a circuit. The resistors 46a, 46b can also be connected between the synthesis circuit 23 and the delay adjustment circuit 13 and between the synthesis circuit 23 and the temperature compensation circuit 14, respectively. FIG. 52 shows an example of a circuit in which the resistance 46 is connected in parallel to the delay adjustment circuit 13 and the temperature compensation circuit 14 in parallel.

Embodiment 2 can also be applied to the structures of Embodiments 3 to 5. That is, it is possible to adopt a structure using multi-gate transistors while using a symmetrical load. For example, multi-gate transistors can be used for transistors in symmetrical loads or diode-connected transistors. With this, the performance can be further improved.

(Example 6)

Fig. 53 is a circuit block diagram showing a part of a voltage controlled oscillator according to Embodiment 6 of the present invention. Hereinafter, description will be provided with reference to this figure.

With Embodiment 6, the frequency is controlled using two control biases so as to perform frequency control with a smaller unit using the control biases. In Embodiment 6, the voltage-controlled oscillator in the configuration shown in FIG. 18 is formed using a delay generating section 11g having a differential input. However, unlike the case of FIG. 18 , two kinds of bias voltages B11 and B12 are used as control bias voltages for controlling the oscillation frequency.

FIG. 53 is a diagram showing a delay adjustment circuit 11g capable of controlling the frequency by using two control bias voltages. This circuit is formed between a high-side power source Vdd and a low-side power source Vss (for example, may be ground). The left side of FIG. 53 is a delay generation unit having the same differential input unit as in FIG. 8 . However, there are differences regarding the following two points. The first point is to constitute the same symmetrical load as in Fig. 42 by adding PMOS transistors 1c', 1d' to PMOS transistors 1c, 1d. The second point is that in addition to the bias voltage B11 applied to the NMOS transistor 2e, there is a bias voltage B13 for frequency control and the like applied via the additional NMOS transistor 2n.

The bias voltage 13 is applied to the PMOS transistors 1o and 1p as a differential signal, and the bias voltage applied to the NMOS transistor 2n is determined by the constant current power supply 47, the PMOS transistors 1o, 1p and the NMOS transistors 2o, 2p. NMOS transistors 2o and 2p constitute a current mirror circuit. For example, the channel width of the NMOS transistor 2n is larger than Xm times the channel width of the NMOS transistor 2o. Through the current mirror circuit, the ratio of the current is changed according to the ratio of the dimensions. With this structure, the delay amount of the delay generating section 11 g is adjusted more precisely than the amount adjusted by the bias voltage 11 . That is, bias voltage 11 is used for coarse adjustment of frequency, and bias voltage 13 is used for fine adjustment of frequency. Bias 12 is used to compensate for temperature.

The structure of Embodiment 6 makes it possible to perform coarse adjustment and fine adjustment of frequency. The tuning width of the fine tuning is determined by the channel width ratio Xm, the current Itune flowing in the NMOS transistor, the current Ibias flowing in the constant current power supply, and the linearity of the current-voltage conversion. Usually, for a structure in which the frequency range is changed by two times or more by coarse adjustment, the value of Xm, etc. is set so as to adjust the frequency within ±10% or less by fine adjustment.

Although Embodiment 6 uses the delay generating section 11g having a differential input, a delay generating section of another structure may also be used.

(Example 7)

FIG. 54 is a circuit block diagram showing a voltage controlled oscillator according to Embodiment 7. FIG. Hereinafter, description will be provided by referring to the accompanying drawings.

Each of the embodiments has shown a method of controlling the frequency using a control bias voltage mainly through an analog signal. However, Embodiment 7 is a case in which the frequency is controlled by a digital signal. The voltage controlled oscillator of Embodiment 7 includes a coarse tuning stage 51 and a fine tuning stage 52 . The coarse tuning stage 51 determines the frequency roughly, and the fine tuning stage 52 determines the frequency in a fine manner. A part of each of these two stages is formed so as to constitute a closed loop so that an oscillating output can be obtained. Embodiment 7 is configured to form a closed loop when the enable signal 55 is applied. Therefore, when the enable signal 55 is not applied, no oscillating output is obtained. That is, during that time period, there is almost no power consumption. The blocks shown with dotted lines in the lower left side of FIG. 54 configured with the control bias voltage and the AD converter 58 are blocks added when Embodiment 7 is used with an analog signal. It is not used when the frequency is controlled by a digital signal.

Control by digital signals is performed as follows. That is, seven high-order bits of, for example, a 15-bit control signal are input to the decoder 57 of the coarse tuning stage 51 . For example, the lower-order 8 bits are input to the decoder 57 of the fine-tuning stage 52 . With this structure, coarse adjustment and fine adjustment are performed.

Attention is paid to the coarse adjustment stage 51, which constitutes a delay line by connecting a plurality of delay generating sections 11h (shown as inverters in the figure) in series. It is configured to take out the required amount of delay according to the control signal. For example, in the decoder 57, the 7-bit high-order signal used for coarse adjustment is decompressed into 128 bits. This can be accomplished by a 128:1 routing circuit connecting the paths with the amount of delay corresponding to the control bit.

The amount of delay taken from the coarse tuning stage 51 receives the small amount of delay added in the fine tuning stage 52 . The fine adjustment stage 52 is formed by serially connecting two delay generating sections 11i (hereafter, connecting one stage of the delay generating sections) to which capacitive loads are added. For capacitive loads, multiple capacitors according to the number of digits are arranged in parallel, and the range of capacitance is selected by switches. Through this, the first and second fine adjustment devices 53 and 54 are constituted.

A second fine-tuning device 54 in the fine-tuning stage 52 processes the high-order bits, and a first fine-tuning device 53 in the fine-tuning stage 52 processes the low-order bits. That is, dividing the fine-tuning stage into a first fine-tuning device and a second fine-tuning device serves to allow more precise selection of the delay amount. In the second fine adjustment device 54, for example, seven capacitors D0 to D6 are provided as capacitive loads of the upper 7 bits among the lower 8 bits of the division control signal. Meanwhile, in the first fine adjustment device 53, thirty-two capacitors D0 to D31 are provided as capacitive loads of bits obtained by, for example, dividing the lower 1 bit of the lower 8 bits of the control signal into 32 bits .

For example, the capacitance value ΔC2 of the capacitive load of the second fine-tuning device 54 is set to be thirty-two times the capacitance value ΔC1 of the capacitive load of the first fine-tuning device 53 . With this structure, by the first fine adjustment device 53, the delay amount can be controlled more precisely. To realize these operations, the decoder 57 in the fine adjustment stage 52 converts the input 8-bit signal into a signal of high-order 7 bits and a signal of 32 bits obtained by dividing the low-order 1 bit into 32 bits.

Such a delay device constructed in this manner is connected to form a closed loop with the enable signal 55 to output the oscillator output 56 as a voltage controlled oscillator. Even if not shown to avoid complexity, according to each of the above-described exemplary embodiments and embodiments, it is also possible to add a temperature compensation bias voltage. Through this, temperature compensation can also be performed. With the above structure, the oscillation frequency can be adjusted in an extremely precise manner as in the case of using an analog signal even when the oscillation frequency is controlled by a digital signal which is easier to generate than an analog signal.

(Embodiment 8)

FIG. 55 is a circuit block diagram showing a voltage controlled oscillator according to Embodiment 8. FIG. Hereinafter, description will be provided by referring to the accompanying drawings.

The voltage controlled oscillator of Example 8 has an inverter 43 and a Schmitt trigger 44 connected to the output terminal of the voltage controlled oscillator 42 according to the above-described exemplary embodiments and examples. Occasionally, the waveform of the output from the voltage controlled oscillator 42 may not be sufficiently shaped. Therefore, the output of the voltage controlled oscillator 42 is connected to an inverter 43 and a Schmitt trigger 44 for shaping the waveform. The Schmitt trigger 44 exhibits a response with a hysteretic characteristic. Therefore, with the circuit configuration of Embodiment 8, it is possible to shape the waveform of the output from the voltage-controlled oscillator 42 into a clock signal with a duty ratio of 50% or the like. In addition, by adjusting the hysteresis characteristic of the Schmitt trigger 44, the duty cycle of the output signal can be freely changed.

(Example 9)

The reference clock within the device can be generated using the voltage controlled oscillator according to one of the above-described exemplary embodiments and embodiments. For example, this reference clock can be used as the clock RCK of the circuit, as shown in Figure 57. With this configuration, a reference clock generation circuit can also be formed in the device, and therefore, it is not necessary to provide elements for a reference clock such as a quartz oscillator with a temperature compensator, which need to be provided externally for a conventional circuit.

(Example 10)

FIG. 56A is a plan view of a display device according to Embodiment 10. FIG. Hereinafter, description will be provided with reference to the accompanying drawings.

The display device 60 of Embodiment 10 is, for example, an LCD (Liquid Crystal Display) or OLED (Organic Light Emitting Diode) display, and has a functional circuit unit 62 and a display unit 63 integrally formed within a housing 61 . The voltage controlled oscillator 64 according to one of the above-described exemplary embodiments and embodiments is provided to the functional circuit unit 62 .

Through Embodiment 10, a required clock signal can be generated within the display device 60 . In addition, the duty ratio of the clock signal can be set to a value other than 50%, and a clocked inverter (Clocked Inverter) or the like generally used in the display device 60 can be stably driven. In addition, when the display unit 63 etc. of the display device 60 etc. has temperature dependence, a temperature control bias can be used so that the clock signal changes in the same manner according to the temperature dependence of the display unit 63, instead of controlling the clock signal so that A method that is not subject to changes in temperature. In that case, the frequency of the entire display device 60 becomes changed according to the change in the temperature of the display unit 62 .

In addition, a signal for compensating for the temperature dependence of the display unit 63 may be generated simultaneously with the generation of the clock signal. That is, the compensation bias voltage for the temperature dependence of the display unit 63 can be generated when generating the temperature compensation bias voltage for the voltage controlled oscillator 60 . As a method for generating the compensation bias voltage, a technique disclosed by the inventor of the present invention in Japanese Unexamined Patent Publication 2006-071564 (Patent Document 2) and the like can be utilized. Through this, the clock signal can be stabilized against changes in temperature while maintaining the frequency of the entire display device 60 . At the same time, it is also possible to alleviate the temperature dependence of the display unit 63 in order to stabilize the characteristics of the display and the like.

(Example 11)

FIG. 56B is a perspective view showing a system according to Embodiment 11. FIG. Hereinafter, description will be provided by referring to FIGS. 56A and 56B .

The system 70 of Embodiment 11 is, for example, a notebook type personal computer including the display device 60 according to Embodiment 10 as one of the structural modules. That is, the system 70 includes the display device 60 and the main body 71 . The main body 71 is a typical structure having a microcomputer, a hard disk, a keyboard, and the like.

The system 70 of Embodiment 11 loading a display device 60 with a voltage controlled oscillator 64 generally does not require an external reference clock. Therefore, it is not necessary to transmit the reference clock. In addition, when the reference clock has a small amplitude, amplification processing is not required. Therefore, the system 70 can have a simplified structure and have reduced power consumption. Furthermore, the reference clock can be connected only when calibrating the system 70 in order to correct the reference value of the oscillation frequency. A reference value for calibration is stored into a memory within the system 70, and after calibration is completed, the oscillation frequency is controlled based on the reference value stored into the memory for normal operation. That is, the control bias voltage is controlled based on the reference value so that the oscillation frequency can be within the calibrated value.

When there is a temperature change, a temperature compensation bias voltage is automatically generated, and the temperature is internally compensated. To generate the temperature compensation bias, for example, the technique disclosed by the inventors of the present invention in Patent Document 2 or other various techniques can be used as a temperature sensor for monitoring temperature. As in the case of the control circuit having the response speed of the temperature sensor disclosed in Patent Document 2, by using the output of the temperature sensor, the control circuit of the voltage controlled oscillator 64 can be configured. This system 70 is low power and can independently compensate for characteristics to stabilize the system.

(Example 12)

The above-described embodiments have exemplified structures in which transistors having two polarities are used as delay elements and voltage-controlled oscillators. In Embodiment 12, a structure using only transistors having either polarity will be exemplified. FIG. 57 shows an example of a circuit block diagram of a delay element using only transistors having either polarity. Here, an example using only PMOS is shown, but by paying attention to the potential relationship, it is easy to adopt a circuit using only NMOS.

The delay generation section shown in FIG. 57 includes five PMOS transistors 1q, 1r, 1s, 1t, and 1u. By inverting the polarity, this circuit has a structure similar to a circuit having a delay generation section as shown in FIG. 8 using a differential input. That is, the PMOS transistors 1r and 1s in FIG. 57 form a differential input pair, like the NMOS transistors 2c and 2d in FIG. 8 . The PMOS 1q in Fig. 57 corresponding to the NMOS 2e in Fig. 8 is controlled by the bias voltage B11 and acts as a current source. If one simply reverses the polarity of the circuit corresponding to PMOS 1c and 1d in Figure 8, two NMOSs are required. In Fig. 57, instead of NMOS, two PMOS 1t and 1u are used. A bias voltage 12B is applied to operate the PMOS 1t and 1u in the linear region (transistor region). Meanwhile, the PMOS 1t and 1u are made to operate in the linear region by setting the low-voltage side power supply potential Vx to ground or a negative power supply. In this structure, since a differential signal is used as in the case of FIG. 8 , the influence of noise is suppressed. Therefore, when a voltage-controlled oscillator is formed by using this structure, the stability of the oscillation frequency is high.

The adjustment of the delay amount and the compensation bias voltage is realized through the bias voltages B11 and B12. The connection method at the time of forming the voltage controlled oscillator can be performed like a voltage controlled oscillator using a differential signal.

(Example 13)

Here, like Embodiment 12, Embodiment 13 using only transistors having either polarity will be described. FIG. 58 shows a delay generation section according to Embodiment 13 including four PMOS transistors 1v, 1w, 1x, and 1y. In this structure, PMOS 1x and PMOS 1y form an inverter. At the same time, the operating point of the inverter is adjusted by bias voltage B1 applied to PMOS 1v and PMOS 1w. That is, when the bias voltage B1 is changed, the potential between the PMOS 1v and the PMOS 1w is also changed, and therefore, the changed potential is input to the gate of the PMOS 1y, and the operating point is changed. The amount of delay can be changed by adjusting the operating point of the inverter. By using a plurality of delay generators connected in a closed loop, a voltage controlled oscillator can be obtained. In Embodiment 13, compared with the case of Embodiment 12, the number of transistors arranged in series between the high-voltage side power supply Vdd and the low-voltage side power supply Vss is smaller (3 in Embodiment 12 and 2 in Embodiment 13). ). Therefore, the amount of divergence of the voltage from the output node of each source voltage is also small. For this reason, the ground voltage is adopted as the low-voltage side power supply voltage in FIG. 58 of Embodiment 13.

This Embodiment 13 is advantageous in that the number of transistors is small and the number of types of source voltages can be reduced as compared with Embodiment 12, because a new low-side power supply is not required.

(Example 14)

In FIG. 59, a configuration almost the same as that of Embodiment 13 in which the number of input bias voltages is two is shown.

In FIG. 58 of Embodiment 13, the input signals to the gate electrodes of PMOS 1v and PMOS 1w are equal. Meanwhile, in FIG. 59 of Embodiment 14, although the input signal is input to the PMOS 1x as shown in FIG. 58, the bias voltage B12 is applied to the PMOS 1v. In this structure, the operating point of the inverter configured with PMOS 1x and 1y can be adjusted by the respective bias voltages of PMOS 1v and PMOS 1W. By this, an operation of normal voltage control by one bias voltage, an operation of temperature compensation by another bias voltage, and the like become possible. By connecting the delay generators in a loop, a voltage controlled oscillator can be formed.

When the voltage controlled oscillator is constituted as shown in Embodiment 14 and Embodiment 13, and the bias voltage is adjusted so as to adjust the oscillation frequency, there are cases where the amplitude of the output voltage changes. To solve this situation, it is considered to provide a level shift circuit in the part where the oscillation output is obtained in order to adjust the output. Meanwhile, there is a method in which a level shift circuit is provided in each delay generation section to adjust the output at each step. An example of this method is shown in FIG. 60 . Connect the output of the inverter with PMOS 1x and 1y to the inverter with PMOS 1x' and 1y'. At the same time, the high side power supply of the inverter having the PMOS transistors 1x' and 1y' is set to V1x. With this structure, the amplitude of the output signal can be adjusted by changing the potential of V1x.

(Example 15)

A drawing showing the core part of the technology of the temperature sensor (FIG. 2A of Patent Document 2) disclosed by the inventors of the present invention in Patent Document 2 is shown in FIG. 61 . In FIG. 61, NMOS2q is a current-voltage conversion unit, and NMOS2r is a temperature detection unit. As is clear from this figure, only transistors of either polarity are used to form the core of the temperature sensor. Therefore, control, including temperature compensation bias, can be performed only by a transistor having either polarity used with the structure of Embodiment 12 or Embodiment 13. Here, the structure is Example 15. For example, FIG. 61 shows a structure using NMOS, but it is configured by PMOS, and only transistors having the same polarity as in FIG. 57 may be arranged. Through this, the advantage is that the manufacturing process of the transistor can be significantly reduced and the cost can be reduced. At the same time, it is also advantageous when using a transistor technology in which it is difficult to configure a transistor with two polarities.

In this embodiment, since the temperature sensor can be formed in the vicinity of the voltage controlled oscillator by using the same process, it is possible to measure the temperature change of the voltage controlled oscillator itself, and to provide feedback. This means that temperature control can be performed more precisely, and a stable oscillation frequency can be obtained, compared to the case of providing a temperature sensor externally. As described, there is an advantage in that the same process (insulating film of the same material and same film thickness, same doping concentration, same active layer, etc.) can be used for the temperature sensor and the voltage control oscillator.

(Example 16)

In each of the embodiments described above, a reference voltage source with weak temperature dependence is often required when generating the bias voltage applied to the delay element or the voltage controlled oscillator. Therefore, in this embodiment, an example of a reference voltage source constituted by transistors is described. FIG. 62 is a diagram showing an example of a reference voltage generation circuit constituted by transistors. The circuit includes three PMOS transistors, five NMOS transistors and two resistors. The NMOS 2s, 2t and 2u marked in the figure may be diodes or bipolar transistors (BJT) instead of NMOS transistors. In this case, a bipolar transistor is used so that the collector is the ground side, and the base and collector are connected. The reference voltage generating circuit shown in this figure is a circuit called a Band Gap Reference (BGR) circuit. The output of this circuit fluctuates very little with temperature. For example, if the circuit is configured with low-temperature polysilicon transistors, when the temperature changes about 100 degrees from room temperature (for example, from 25 degrees Celsius to 125 degrees Celsius), the output voltage fluctuates by about several hundred ppm for each degree Celsius. That is, in a temperature range of, for example, 100 degrees, the control bias required for 3V can be output from 2.9997V to 3.0003V in FIG. 41 . As shown in this embodiment, for controlling the bias voltage, it is preferable to use a circuit that can obtain a stable output in such a wide temperature range. At the same time, it can be used as a reference voltage that does not fluctuate with temperature when generating a compensation bias voltage for a temperature sensor. In addition, it can also be used as a reference voltage for a circuit described below that is fed back so that the source voltage and the like do not fluctuate with temperature. By including such a reference voltage circuit, the output of the voltage controlled oscillator can be extremely stabilized.

In the description of the embodiments of this specification, there are several examples where a polycrystalline silicon thin film transistor is used as a transistor. This is the case, for example, in FIGS. 23 and 24 showing the characteristics of a single transistor. However, it is obvious that the present invention is not limited to be applied only to polycrystalline silicon thin film transistors, but is applicable to various transistors. In particular, the exemplary embodiment using either polarity is preferably used for amorphous silicon thin film transistors, organic transistors, oxide transistors, and the like. Meanwhile, the exemplary embodiment using either polarity may be applied to polysilicon thin film transistors or bulk silicon transistors in order to reduce costs.

(supplementary explanation)

The structure, operation and effect of the present invention are also expressed as follows.

First, the structure of the present invention will be described. The first delay element of the present invention is a delay element whose delay can be controlled from the outside by a delay control section provided with a delay adjustment circuit and a temperature compensation circuit connected in series. In addition, the second delay element of the present invention is a delay element capable of externally controlling delay by a delay control section provided with a delay adjustment circuit, a temperature compensation circuit, and a synthesis circuit connected to those circuits.

By connecting in series a plurality of delay elements having a delay control section configured with a delay adjustment circuit and a temperature compensation circuit connected in series, or a plurality of delay elements configured with a delay adjustment circuit, a temperature compensation circuit, and a synthesis circuit connected to those circuits The delay elements of the control unit constitute the first variable delay line of the present invention. In addition, the second variable delay line of the present invention is constituted by connecting a plurality of delay generating sections in series, and a delay control section for externally controlling the delay amount of the delay generating sections is provided, which is common to all delay generating sections. The delay control section is configured with a delay adjustment circuit and a temperature compensation circuit connected in series, or with a delay adjustment circuit, a temperature compensation circuit, and a synthesis circuit connected to those circuits.

By serially connecting a plurality of delay elements having a delay control section configured with a delay adjustment circuit and a temperature compensation circuit connected in series, or a plurality of delay elements having a delay adjustment circuit configured with a delay adjustment circuit, a temperature compensation circuit, and a synthesis circuit connected to those circuits The delay element in the part forms the first voltage-controlled oscillator of the present invention into a closed loop. In addition, the second voltage controlled oscillator of the present invention is constituted by connecting a plurality of delay generation sections in series, and a delay control section for externally controlling the delay amount of the delay generation sections is provided, which is common to all delay generation sections. The delay control section is configured with a delay adjustment circuit and a temperature compensation circuit connected in series, or with a delay adjustment circuit, a temperature compensation circuit, and a synthesis circuit connected to those circuits.

Next, the operation of the present invention (action of the device for obtaining the effect) will be described. The first delay element of the present invention has a delay adjustment circuit and a temperature compensation circuit, so that the delay amount can be adjusted externally and the temperature characteristic can be compensated externally. The delay control section configured by connecting the delay adjustment circuit and the temperature compensation circuit in series can transmit a signal to the delay generation section. Since the control signal is transmitted from the delay control section constituted by connecting the delay adjustment circuit and the temperature compensation circuit in series to the delay generation section, the number of control signal lines directly connected to the delay generation section is small. That is, the control signal of the delay adjustment circuit and the compensation control signal of the temperature compensation circuit are synthesized into a new control signal for adjusting the delay amount in the delay control unit. Since the delay adjustment circuit and the temperature compensation circuit are connected in series, the control information transmitted to the delay control section acts on only a part of the delay elements. Therefore, it is not necessary to have a plurality of control sections in the delay control section, thereby simplifying the structure. Furthermore, since there is no need to have a plurality of control sections in the delay control section, various types can be used for the delay control section.

The second delay element of the present invention is controlled by a delay control section configured with a delay adjustment circuit, a temperature compensation circuit, and a synthesis circuit connected to those circuits. Therefore, the number of control signal lines is small, as in the case of the above-described delay control section in which the delay adjustment circuit and the temperature compensation circuit are connected in series. Furthermore, the control information only works on one part of the delay element.

By connecting in series a plurality of delay elements having a delay control section configured with a delay adjustment circuit and a temperature compensation circuit connected in series, or a plurality of delay elements configured with a delay adjustment circuit, a temperature compensation circuit, and a synthesis circuit connected to those circuits The delay elements of the control unit constitute the variable delay line of the present invention. Therefore, it is possible to obtain an arbitrary temperature compensation delay amount by selecting an arbitrary junction point.

By connecting in series a plurality of delay elements having a delay control section configured with a delay adjustment circuit and a temperature compensation circuit connected in series, or a plurality of delay elements configured with a delay adjustment circuit, a temperature compensation circuit, and a synthesis circuit connected to those circuits The delay element of the control unit forms the voltage controlled oscillator of the present invention into a closed loop. Therefore, it is possible to vary the frequency by controlling the bias voltage with the frequency, and to obtain a signal with a temperature-compensated frequency.

Next, effects of the present invention will be described. The first effect is that it is possible to provide a voltage-controlled oscillator whose central oscillation frequency is stable even if the temperature varies with a simple structure. In particular, with a simple structure, it is possible to provide a voltage-controlled oscillator capable of performing good temperature compensation without using external components such as a temperature-compensated quartz oscillator or the like.

The second effect is that it is possible to provide a voltage-controlled oscillator that satisfies the following three points particularly through the use of a symmetrical load. These three points are: (1) independent of the control bias voltage, the oscillation signal can be obtained; (2) relative to the change of the control bias voltage, the change of the oscillation frequency is in a linear form; (3) relative to the change of the control bias voltage, The gain of the change of the oscillation frequency is small. At the same time, it is possible to provide a voltage controlled oscillator with less frequency variation even in the presence of temperature variation.

A third effect is that it is possible to provide a voltage controlled oscillator that exhibits good characteristics even when the characteristics of the element greatly fluctuate from predetermined characteristics due to process conditions and the like.

A fourth effect is that it is possible to provide a delay element having a function of controlling the delay amount and compensating for a change in characteristics caused by temperature by acting on only one part of the delay element. In addition, it is possible to provide a variable delay line and a voltage controlled oscillator capable of adjusting frequency and compensating for temperature by using that delay element.

The fifth effect is that it is possible to provide delay elements having various structures for controlling the amount of delay and compensating for changes in characteristics caused by temperature by operating only one part of the delay element. In addition, a variable delay line and a voltage-controlled oscillator capable of adjusting frequency and compensating for temperature by using such a delay element can be provided.

A sixth effect is that it is possible to provide a display device in which a functional circuit unit and a display unit are integrally formed in which temperature characteristics are compensated. In addition, various devices and systems using the display device as one of the structural modules can be provided. In particular, it is possible to provide a system with low power consumption and independent compensation of characteristics.

Although the present invention has been described by referring to each of the exemplary embodiments and examples, the present invention is not limited to those exemplary embodiments and examples. Various changes and modifications that can occur to those skilled in the art can be applied to the structure and details of the present invention. In addition, it will be understood that the present invention includes a combination of a part or the whole part of the structures described in each of the exemplary embodiment and the examples.

Although the invention has been particularly shown and described with reference to exemplary embodiments thereof, the invention is not limited to these embodiments. It will be understood by those of ordinary skill in the art that various changes in form and details may be made without departing from the spirit and scope of the present invention as defined by the appended claims.

Claims (17)

1. delay element comprises postponing generation portion and postponing control part, and said delay generation portion generates the output signal through adding the specific delays amount to input signal, and said delay control part is used to control said retardation, wherein:

Said delay control part comprises that delay regulating circuit and output that output is used to regulate first control signal of said retardation are used to compensate the temperature-compensation circuit of second control signal of the characteristic variations that is caused by temperature; And will output to said delay generation portion through the 3rd control signal that synthetic said first control signal and said second control signal obtain; So that control said retardation

Wherein, said at least delay regulating circuit or said temperature-compensation circuit comprise one or more multi-gated transistors.

2. delay element as claimed in claim 1, wherein, said delay control part obtains said the 3rd control signal through be connected in series said delay regulating circuit and said temperature-compensation circuit.

3. delay element as claimed in claim 1, wherein, said delay generation portion disposes the current-starved inverter.

4. delay element as claimed in claim 3 wherein, adds the additional capacitor that causes owing to mirror capacity to said current-starved inverter.

5. delay element as claimed in claim 1, wherein, said delay generation portion comprises the differential input end that is used to import said input signal.

6. a vairable delay line comprises a plurality of delay elements in the claim 1 that is connected in series.

7. vairable delay line as claimed in claim 6 comprises being provided to be common to single said delay control part of said a plurality of delay elements, wherein,

Said single delay control part offers a plurality of said delay generation portion that offers said a plurality of delay elements respectively with said the 3rd control signal, so that control said retardation.

8. voltage-controlled oscillator; Dispose vairable delay line as claimed in claim 6; Comprise the closed-loop path, in said closed-loop path, one output of said a plurality of delay elements is connected to one input than the said delay element of this delay element previous stage.

9. voltage-controlled oscillator as claimed in claim 8, wherein, the output of the delay element of the afterbody in said a plurality of delay elements is connected to the input of the delay element of the first order.

10. voltage-controlled oscillator as claimed in claim 8, wherein, said a plurality of delay elements are odd number delay elements, and each of said delay element all disposes the voltage-controlled type negater.

11. voltage-controlled oscillator as claimed in claim 8, wherein, said delay element disposes the imported delay element of difference.

12. voltage-controlled oscillator as claimed in claim 8, wherein, said at least delay regulating circuit or said temperature-compensation circuit comprise the one or more elements that constitute through be connected in parallel transistor and diode-connected transistor.

13. voltage-controlled oscillator as claimed in claim 8; Wherein, be formed for said the 3rd control signal is outputed to from said delay control part the part of said delay generation portion by the element that constitutes through be connected in parallel transistor and diode-connected transistor.

14. voltage-controlled oscillator as claimed in claim 8, wherein, said the 3rd control signal is an analog signal.

15. voltage-controlled oscillator as claimed in claim 8, wherein, said the 3rd control signal is a digital signal.

16. a display apparatus comprises voltage-controlled oscillator as claimed in claim 8 and the functional circuit unit that comprises said voltage-controlled oscillator.

17. a system comprises display apparatus as claimed in claim 16 as construction module.

Images