CN102790174A - Capacitor device and method of manufacturing the same - Google Patents

Abstract

The embodiment of the invention discloses a capacitor device, which comprises: a lower electrode; a dielectric layer on the lower electrode, wherein the dielectric layer comprises an organic dielectric layer; and an upper electrode on the dielectric layer. By forming the dielectric layer including the organic dielectric layer, the organic dielectric layer has better electron capture capability, and can reduce the electric leakage of the capacitor device, thereby improving the performance of the capacitor device.

Description

Capacitive device and manufacturing method thereof

technical field

The present invention relates to a semiconductor device and its manufacturing technology, more specifically, to a capacitor device and its manufacturing method.

Background technique

With the rapid development of information technology, electronic products have been closely related to every aspect of people's life and work, so how to manufacture electronic products with low cost and good performance has become the focus of research. Integrated circuits and devices in electronic products are the core parts. Therefore, the research on the core units and various devices in integrated circuits is increasingly diversified.

Traditional semiconductor devices (such as FETs, field effect transistors) are formed by gate dielectric stack structures on semiconductor materials, but the manufacturing cost is relatively high. In recent years, organic materials such as organic transistors and organic memory devices have been actively researched and developed, and devices using organic materials are favored due to their low cost, good flexibility, and light weight.

At present, the structure of the capacitor device is mostly compatible with the gate dielectric stack structure, usually including: a lower electrode, a dielectric layer of a gate dielectric material, and an upper electrode, and a gate dielectric material such as silicon dioxide.

However, the capacitive device formed with a dielectric layer of gate dielectric material such as silicon dioxide has the problem of leakage, which will affect the reliability and performance of the device.

Contents of the invention

Embodiments of the present invention provide a capacitive device and a manufacturing method thereof to form an organic capacitive device and improve the performance of the capacitive device.

In order to achieve the above object, the embodiment of the present invention provides the following technical solutions:

A capacitive device comprising:

lower electrode

a dielectric layer on the lower electrode, wherein the dielectric layer includes an organic dielectric layer;

The upper electrode on the dielectric layer.

Optionally, the lower electrode is a doped semiconductor substrate, and the dielectric layer includes an inorganic dielectric layer and an organic dielectric layer on the inorganic dielectric layer.

Optionally, the lower electrode is formed on an amorphous substrate, and the lower electrode is a conductive layer.

Optionally, the organic medium layer is selected from the group consisting of the following materials: TiOPc, Alq3, PVP, pentacene or polyfluorene.

In addition, the present invention also provides a manufacturing method for forming the above capacitive device, including:

provide the substrate;

forming a lower electrode on the substrate;

forming a dielectric layer on the lower electrode, wherein the dielectric layer includes an organic dielectric layer;

An upper electrode is formed on the dielectric layer.

Optionally, the substrate is a semiconductor substrate, wherein the step of forming the lower electrode is: doping the semiconductor substrate to form the lower electrode; the step of forming the dielectric layer is: forming the lower electrode An inorganic medium layer is formed on the inorganic medium layer, and an organic medium layer is formed on the inorganic medium layer.

Optionally, the substrate is an amorphous substrate, wherein the step of forming the lower electrode includes: forming a lower electrode of a conductive layer on the substrate.

Optionally, the organic medium layer is selected from the group consisting of the following materials: TiOPc, Alq3, PVP, pentacene or polyfluorene.

Optionally, the method for forming the upper electrode is: using a hollowed-out mask to form the upper electrode on the dielectric layer.

Compared with the prior art, the above-mentioned technical solution has the following advantages:

In the capacitive device and its manufacturing method according to the embodiment of the present invention, a dielectric layer including an organic dielectric layer is formed. The organic dielectric layer has a better electron capture capability, which can reduce the leakage of the capacitive device and improve the reliability of the device, thereby improving the reliability of the capacitive device. performance.

In addition, in order to be better compatible with other FET devices, a dielectric layer including an inorganic dielectric layer and an organic dielectric layer is formed, and the inorganic dielectric layer is optimized through the organic dielectric layer, which improves the reliability of the device while reducing the leakage of the capacitor device. It is also easier to be compatible in the manufacturing process, and the integration degree is improved.

Description of drawings

The above and other objects, features and advantages of the present invention will be more clearly illustrated by the accompanying drawings. Like reference numerals designate like parts throughout the drawings. The drawings are not intentionally scaled according to the actual size, and the emphasis is on illustrating the gist of the present invention.

1 is a schematic structural view of a capacitive device according to an embodiment of the present invention;

Fig. 2 is the manufacturing method flowchart of capacitive device according to the present invention;

3-5 are schematic diagrams of various manufacturing stages of a capacitor device according to Embodiment 1 of the present invention;

6-8 are schematic diagrams of various manufacturing stages of a capacitive device according to Embodiment 2 of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, specific implementations of the present invention will be described in detail below in conjunction with the accompanying drawings.

In the following description, a lot of specific details are set forth in order to fully understand the present invention, but the present invention can also be implemented in other ways different from those described here, and those skilled in the art can do it without departing from the meaning of the present invention. By analogy, the present invention is therefore not limited to the specific examples disclosed below.

Secondly, the present invention is described in detail in combination with schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of the present invention. In addition, the three-dimensional space dimensions of length, width and depth should be included in actual production.

As described in the background technology, traditional semiconductor devices are developing towards organic material devices. In order to better improve the performance of capacitive devices, the present invention proposes organic capacitive devices. Referring to FIG. 1, FIG. 1 is a capacitive device according to an embodiment of the present invention A schematic diagram of the capacitive device comprising:

lower electrode;

A dielectric layer 102 on the lower electrode, wherein the dielectric layer includes an organic dielectric layer 102-2;

The upper electrode 110 on the dielectric layer.

In the present invention, the dielectric layer 102 is a one-layer or multilayer structure including at least an organic dielectric layer 102-2, and the organic dielectric layer 102-2 may be: Alq ₃ (octahydroxyquinoline aluminum, 8-hydroquinolinealuminum ), PVP (poly 4-vinylphenol, poly (4-vinylphenol)), pentacene (pentacene), TiOPc (titanium phthalocyanine, oxotitanium phthalocyanine) or polyfluorene (polyfluorene), etc.

In the present invention, the lower electrode 100 or the upper electrode 110 may be doped semiconductor, metal material or other suitable electrode materials.

In some embodiments, the lower electrode 100 may be a conductive base formed by doping a semiconductor substrate, for example, a highly doped Si substrate is the lower electrode 100, and the semiconductor substrate may also include But not limited to other elemental or compound semiconductors, such as germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide or indium phosphide. In these embodiments, preferably, the dielectric layer 102 may be a multilayer structure including an organic dielectric layer 102-1 and an organic dielectric layer 102-2, wherein the organic dielectric layer 102-1 may be a gate dielectric material, for example Silicon dioxide, silicon oxynitride or high-k dielectric materials (eg, materials with a high dielectric constant compared to silicon oxide), high-k dielectric materials such as hafnium-based oxides, HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO etc., the organic dielectric layer 102-2 can be a one-layer or multi-layer structure, and this dielectric layer including the organic dielectric layer 102-1 and the organic dielectric layer 102-2 can better match the gate dielectric structure of the FET device (Field Effect Transistor) compatible.

In some other embodiments, the lower electrode 100 may also be a metal layer or other doped semiconductor layers, such as Cr, Au or polysilicon.

In some other embodiments, the lower electrode 100 can be formed on an amorphous substrate, such as plastic, glass or other amorphous materials, etc., and the lower electrode 100 can be any suitable conductive layer. In the bottom embodiment, the flexibility of the capacitive device can be better improved.

Through the dielectric layer including the organic dielectric layer, the electron trapping capability is enhanced, thereby improving the performance of the capacitive device.

The capacitive device of the present invention has been described in detail above. In order to better understand the present invention, the manufacturing method of the capacitive device embodiment of the present invention will be described in detail below in conjunction with the flowchart of the manufacturing method of the capacitive device and the schematic diagrams of each manufacturing stage.

As shown in FIG. 2 , FIG. 2 is a flow chart of the manufacturing method of the capacitive device of the present invention, and different embodiments will be described in detail below in conjunction with the flow chart.

Embodiment one

In step S1, a substrate 200 is provided, refer to FIG. 3 .

In this embodiment, the substrate 200 may be a semiconductor substrate, and in one embodiment, the substrate 200 includes a Si substrate. In other embodiments, the substrate may also include but not limited to other elemental semiconductors or compound semiconductors, such as germanium, silicon germanium, silicon carbide, gallium arsenide, indium arsenide or indium phosphide. The substrate 200 can also be a stacked semiconductor structure, such as Si/SiGe, silicon-on-insulator (SOI) or silicon-germanium-on-insulator (SGOI). In addition, other devices may also be included in the substrate.

In step S2 , the lower electrode 100 is formed on the substrate 200 .

In some embodiments, the substrate 200 may be doped by a conventional doping process to form the lower electrode 100 , as shown in FIG. 4 .

In some other embodiments, a doped semiconductor layer (not shown) may also be formed by epitaxial growth on the substrate 200 to form the lower electrode.

In some other embodiments, the lower electrode may also be formed by forming a metal layer or other suitable electrode materials (not shown) on the substrate 200 .

The method for forming the lower electrode here is only an example, and any other suitable method may be used to form the lower electrode 100 in the present invention, which is not limited in the present invention.

In step S3 , a dielectric layer 102 is formed on the lower electrode 100 , wherein the dielectric layer 102 includes an organic dielectric layer 102 - 2 , as shown in FIG. 5 .

In this embodiment, the dielectric layer 102 may be an organic dielectric layer 102-2 including one or more layers of structure, and the dielectric layer 102 may also be an organic dielectric layer 102 including an inorganic dielectric layer 102-1 and one or more layers of structure The multilayer structure of the organic medium layer 102-2, wherein the organic medium layer 102-2 can be: Alq ₃ (octahydroxyquinoline aluminum, 8-hydroquinoline aluminum), PVP (poly 4-vinylphenol, poly (4-vinylphenol)), pentacene (pentacene), TiOPc (oxotitaniumphthalocyanine) or polyfluorene (polyfluorene), etc.

The inorganic dielectric layer 102-1 may be a gate dielectric material, such as silicon dioxide, silicon oxynitride, or a high-k dielectric material (for example, a material with a high dielectric constant compared with silicon oxide), and the high-k dielectric material is, for example, Hafnium-based oxides, HfO ₂ , HfSiO, HfSiON, HfTaO, HfTiO, etc., including the dielectric layer structure of the inorganic dielectric layer 102-1, can be better compatible with the manufacturing process of FET devices (field effect transistors) with gate dielectric structure.

In some embodiments, specifically, the inorganic dielectric layer 102-1 can be formed on the lower electrode 100 by thermal oxidation or chemical vapor deposition, such as silicon dioxide, silicon oxynitride or a high-k dielectric material, such as by thermal oxidation Form an inorganic dielectric layer 102-1 of silicon dioxide with a thickness of 30 nm, and then, vacuum thermal evaporation or spin coating or other suitable methods can be used to form one or more layers of organic dielectric layer 102-1 on the inorganic dielectric layer 102-1. For the dielectric layer 102-2, for example, the organic dielectric layer 102-2 of Alq ₃ with a thickness of 35 nm is formed by vacuum thermal evaporation. In these embodiments, a dielectric layer including an inorganic dielectric layer and an organic dielectric layer is formed, and the inorganic dielectric layer is optimized through the organic dielectric layer. While reducing the leakage of the capacitor device, the reliability of the device is improved, and the manufacturing process is more advanced. Easy compatibility and improved integration.

In other embodiments, one or more layers of organic medium layer 102 - 2 may be directly formed on the lower electrode 100 .

In step S4 , an upper electrode 110 is formed on the dielectric layer 102 , as shown in FIG. 5 .

Evaporation technology, magnetron sputtering technology or inkjet printing technology can be used to form the upper electrode of metal or organic conductor or other suitable electrode materials, for example, the upper electrode of Al with a thickness of 200 nm can be formed on the dielectric layer 102 by evaporation technology 110. Other suitable methods can also be used to form the upper electrode of other materials. Preferably, the upper electrode can be prepared by using a hollowed-out mask. The hollowed-out mask is a mask with a pattern. Through the mask The plate can directly form a patterned upper electrode, thereby avoiding the damage caused by the photoresist to the organic molecular material during the patterning process of deposition and etching in the traditional process, and further improving the performance of the device.

Then, reactive ion etching (RIE) can be used to etch and remove the excess dielectric layer, thereby forming a capacitive device with an organic dielectric layer.

Embodiment two

The following will only describe the aspects that the third embodiment differs from the first embodiment. The parts not described should be considered to be performed by the same steps, methods or processes as those in Embodiment 1, and thus will not be repeated here.

In step S1, a substrate 200 is provided, refer to FIG. 6 .

In this embodiment, the substrate 200 can be an amorphous substrate, such as plastic, glass or other amorphous substrate materials. For the embodiment of the plastic substrate, the capacitor device has better flexibility and more light weight.

In step S2 , the lower electrode 100 is formed on the substrate 200 .

The lower electrode 100 can be formed by forming a conductive layer on the substrate, the conductive layer can be a doped semiconductor or metal layer or other suitable electrode materials, such as doped polysilicon, Cr, Au, Al and so on.

In step S3 , a dielectric layer 102 is formed on the lower electrode 100 , wherein the dielectric layer 102 includes an organic dielectric layer 102 - 2 , as shown in FIG. 7 .

It is the same as that of Embodiment 1 and will not be repeated here.

In step S4 , an upper electrode 110 is formed on the dielectric layer 102 , as shown in FIG. 8 .

Thus, a capacitive device having an organic dielectric layer is formed.

It is the same as that of Embodiment 1 and will not be repeated here.

The above descriptions are only preferred embodiments of the present invention, and do not limit the present invention in any form.

Although the present invention has been disclosed above with preferred embodiments, it is not intended to limit the present invention. Any person familiar with the art, without departing from the scope of the technical solution of the present invention, can use the methods and technical content disclosed above to make many possible changes and modifications to the technical solution of the present invention, or modify it into an equivalent implementation of equivalent changes example. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments according to the technical essence of the present invention, which do not deviate from the technical solution of the present invention, still fall within the protection scope of the technical solution of the present invention.

Claims (9)

1. a capacitor element is characterized in that, comprising:

Bottom electrode

Dielectric layer on the bottom electrode, wherein, said dielectric layer comprises organic dielectric layer;

Top electrode on the dielectric layer.

2. capacitor element according to claim 1 is characterized in that, the Semiconductor substrate of said bottom electrode for mixing, and said dielectric layer comprises the organic dielectric layer on inorganic medium layer and the inorganic medium layer.

3. capacitor element according to claim 1 is characterized in that, said bottom electrode is formed on the amorphous substrate, and said bottom electrode is a conductive layer.

4. according to each described capacitor element among the claim 1-3, it is characterized in that said organic dielectric layer is selected to form: TiOPc, Alq3, PVP, pentacene or polyfluorene from the group that comprises following material.

5. the manufacturing approach of a capacitor element is characterized in that, comprising:

Substrate is provided;

On said substrate, form bottom electrode;

On said bottom electrode, form dielectric layer, wherein, said dielectric layer comprises organic dielectric layer;

On said dielectric layer, form top electrode.

6. manufacturing approach according to claim 5 is characterized in that, said substrate is a Semiconductor substrate, wherein,

The step that forms bottom electrode is: said Semiconductor substrate is mixed to form bottom electrode;

The step that forms said dielectric layer is: on said bottom electrode, form the inorganic medium layer, and on the inorganic medium layer, form organic dielectric layer.

7. manufacturing approach according to claim 5 is characterized in that, said substrate is the amorphous substrate, and wherein, the step that forms said bottom electrode is: the bottom electrode that on said substrate, forms conductive layer.

8. according to each described manufacturing approach among the claim 5-7, it is characterized in that said organic dielectric layer is selected to form: TiOPc, Alq3, PVP, pentacene or polyfluorene from the group that comprises following material.

9. according to each described manufacturing approach among the claim 5-7, it is characterized in that the method that forms said top electrode is: utilize the mask plate of hollow out on said dielectric layer, to form top electrode.

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