CN102820252B - Preparation method of high mobility ratio double channel material based on bonding process - Google Patents
Preparation method of high mobility ratio double channel material based on bonding process Download PDFInfo
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- CN102820252B CN102820252B CN201110151804.8A CN201110151804A CN102820252B CN 102820252 B CN102820252 B CN 102820252B CN 201110151804 A CN201110151804 A CN 201110151804A CN 102820252 B CN102820252 B CN 102820252B
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- 239000000463 material Substances 0.000 title claims abstract description 38
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000002360 preparation method Methods 0.000 title claims abstract description 19
- 229910000577 Silicon-germanium Inorganic materials 0.000 claims abstract description 48
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 239000010703 silicon Substances 0.000 claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 15
- 238000000137 annealing Methods 0.000 claims abstract description 13
- 230000003647 oxidation Effects 0.000 claims abstract description 4
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 4
- 238000005516 engineering process Methods 0.000 claims description 21
- 238000002513 implantation Methods 0.000 claims description 18
- 238000007596 consolidation process Methods 0.000 claims description 10
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 9
- 229920002120 photoresistant polymer Polymers 0.000 claims description 8
- 230000003014 reinforcing effect Effects 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 6
- 238000012546 transfer Methods 0.000 claims description 4
- 230000007797 corrosion Effects 0.000 claims description 3
- 238000005260 corrosion Methods 0.000 claims description 3
- 238000000407 epitaxy Methods 0.000 claims description 3
- 238000000227 grinding Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 4
- 230000005669 field effect Effects 0.000 abstract 2
- 230000000295 complement effect Effects 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
- 239000012212 insulator Substances 0.000 description 5
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- 230000015572 biosynthetic process Effects 0.000 description 2
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- 241000894007 species Species 0.000 description 1
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Abstract
The invention discloses a preparation method of a high mobility ratio double channel material based on a bonding process. A silicon substrate extension compressive strain SiGe layer is used, and the SiGe layer is transferred onto a thermal oxidation silicon chip by means of the bonding process, and the SiGe layer is used as a p-metal-oxide-semiconductor field-effect transistor (PMOSFET) channel material; and silicon is continuously extended on the SiGe material, methods of ion implantation, annealing and the like are used to relax parts of strained SiGe, and simultaneously, strain is transmitted in an upper Si layer to form a strain Si material to be used as an n-metal-oxide-semiconductor field-effect transistor (NMOSFET) channel material. The preparation method is simple in process, easy to implement and capable of providing the high mobility ratio channel materials for PMOSFET and NMOSFET, meeting requirements of simultaneously improving performances of the PMOSFET and the NMOSFET and providing potential channel materials for a next generation of complementary metal-oxide-semiconductor transistor (CMOS) processes.
Description
Technical field
The present invention relates to a kind of preparation method of the double channel material for cmos device, relate in particular to a kind of preparation method of the high mobility double channel material based on bonding technology, belong to microelectronics and solid electronics technical field.
Background technology
Along with the development of integrated circuit technology, the characteristic size of device is constantly dwindled, and the electronics that body silicon materials are lower and hole mobility have become the bottleneck that improves device performance.Strained silicon (strained silicon), by be different from epitaxial silicon on the material of silicon in lattice constant, or other processes cause the stretching of silicon lattice structure or compressive deformation and form.Because it can effectively improve carrier mobility, become candidate's backing material of Next Generation semiconductor technology node.SiGe substrate has the lattice constant not identical with Si, on SiGe substrate, between epitaxially grown Si and SiGe substrate, can have lattice mismatch, and this lattice mismatch makes the Si layer of extension have strain.Strained silicon materials is due to the distortion of its lattice structure, can improve the mobility in electronics and hole simultaneously, and strained-silicon-on-insulator (sSOI, strained silicon on insulator) there is silicon-on-insulator (SOI simultaneously, silicon on insulator) and the advantage of strained silicon, more wide application prospect in integrated circuit technology, there is.
Strained-silicon-on-insulator material can be also strain Si and the combination of (strain) SiGe, forms double channel layer structure (strain Si as top layer, SiGe as buried regions) taking strain Si/ (strain) SiGe.In the band structure of double channel uniqueness, electronics is limited in, in strain Si layer, can obtaining high electron mobility, and hole is limited in, in (strain) SiGe layer, can obtaining high hole mobility.
Given this, the present invention will propose a kind of preparation technology of the strain Si/SiGe double channel material based on bonding technology, adopt this technique can be simultaneously to provide the channel material of high mobility for NMOS and PMOS.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of preparation method of the high mobility double channel material based on bonding technology.
In order to solve the problems of the technologies described above, the present invention adopts following technical scheme: a kind of preparation method of the high mobility double channel material based on bonding technology, comprises the following steps:
Step 1, on body silicon substrate epitaxial growth SiGe layer, as device sheet;
Step 2, another body surface of silicon is carried out to thermal oxidation, make its surface form SiO
2layer, as support chip;
Step 3, there are the surface of SiGe layer and support chip to be formed with SiO device sheet epitaxy
2the surface bond of layer, the line unit of going forward side by side closes consolidation process, forms bonding pad;
Device sheet part in step 4, para-linkage sheet is carried out grinding back surface, and the body silicon substrate at the device sheet back side is thinned to 1-10 micron, then utilizes the method for chemical corrosion to remove the remaining body silicon substrate of attenuate, exposes SiGe layer;
Step 5, on the SiGe layer exposing epitaxial growth Si block layer;
Step 6, on described Si block layer, form photoresist, utilize chemical wet etching technique that part Si block layer is exposed;
Step 7, on the Si block layer exposing, continue epitaxial growth Si layer;
Step 8, carry out Implantation, make the ion distribution of injecting at SiO
2in layer;
Step 9, carry out annealing process, make the stress in part SiGe layer produce relaxation, thereby stress transfer is formed to strained silicon in the Si material of its top extension; The strained silicon forming is used to form NMOSFET raceway groove, and the SiGe layer below photoresist overlay area is used to form PMOSFET raceway groove.
As preferred version of the present invention, in the epitaxially grown SiGe layer of step 1, Ge content is 10%-50%.
As preferred version of the present invention, the thickness of the epitaxially grown SiGe layer of step 1 is 5-200nm.
As preferred version of the present invention, the SiO that step 2 forms
2the thickness of layer is 10-500nm.
As preferred version of the present invention, the reinforcing temperature of step 3 bonding consolidation process is 300-800 DEG C, and the time is 5-60 minute.
As preferred version of the present invention, the thickness of the epitaxially grown Si block of step 5 layer is 2-5nm.
As preferred version of the present invention, the thickness of the epitaxially grown Si layer of step 7 is 5-20nm.
As preferred version of the present invention, the ion that step 8 is injected is one or more of H, He, N, Si, C.
As preferred version of the present invention, the dosage of step 8 Implantation is 1E13-1E18/cm
2.
As preferred version of the present invention, the temperature of step 9 annealing is 300-1000 DEG C, and the time is 1 minute to 2 hours.
Beneficial effect of the present invention is:
The present invention has adopted bonding technology, utilizes the means such as extension, Implantation, annealing having SiO
2on the substrate of layer, form strain Si/SiGe double channel material, its processing step is simple, be easy to realize, can be simultaneously provide the channel material of high mobility for NMOSFET and PMOSFET, meet the requirement that simultaneously improves NMOSFET and PMOSFET device performance, for follow-on CMOS technique provides potential channel material.
Brief description of the drawings
Fig. 1-8 are the process flow diagram of the inventive method.
Embodiment
Further illustrate specific embodiment of the invention step below in conjunction with accompanying drawing, for the accompanying drawing that facilitates illustrating is not proportionally drawn.
Embodiment mono-
Refer to Fig. 1-8, the preparation method that the present embodiment provides, comprises the following steps:
Step 1, on body silicon substrate 10 epitaxial growth SiGe layer 20, as device sheet, as shown in Figure 1, the Ge content of SiGe layer 20 can be preferably 10%-50%, thickness is preferably 5-200nm.For the SiGe layer 20 that ensures growth has compression, the thickness of SiGe material should be controlled in critical thickness, and in the present embodiment, the Ge content of epitaxially grown SiGe layer 20 is 20%, and its THICKNESS CONTROL is in 100nm left and right.
Step 2, thermal oxidation is carried out in another body silicon substrate 30 surfaces, make its surface form SiO
2layer 40, as support chip.The SiO forming
2the thickness of layer is preferably 10-500nm.In the present embodiment, SiO
2the thickness of layer 40 is 500nm.
Step 3, as shown in Figure 2, has the surface of SiGe layer 20 and support chip to be formed with SiO device sheet epitaxy
2the surface bond of layer 40, the line unit of going forward side by side closes consolidation process, forms bonding pad as shown in Figure 3.The reinforcing temperature of bonding consolidation process is preferably 300-800 DEG C, and the time is preferably 5-60 minute.In the present embodiment, reinforcing temperature is 500 DEG C, and the time is 40 minutes.
Device sheet part in step 4, para-linkage sheet is carried out grinding back surface, until stop apart from 20 several microns of place of SiGe layer, body silicon substrate 10 by the device sheet back side is thinned to 1-10 micron, then utilize the method for chemical corrosion, optionally erode the remaining body silicon substrate 10 of attenuate, automatically stop to SiGe layer 20, expose SiGe layer 20, obtain structure as shown in Figure 4.
Step 5, on SiGe layer 20, continue epitaxial growth Si material, as Si block layer 50.The thickness of Si block layer 50 is 2-5nm, is used for contacting with high-k (H-K) gate medium, thereby avoids the formation of boundary defect state in the time of follow-up makings MOS device.
Step 6, according to the requirement of CMOS technique, on described Si block layer 50, form photoresist 60; Then utilize chemical wet etching technique to form corresponding figure, expose a part of Si block layer 50, as shown in Figure 5.The part that is designed to PMOSFET can be protected with photoresist thus, and the part that is designed to NMOSFET is exposed so that subsequent technique forms strained silicon in this region.
Step 7, as shown in Figure 6 continues epitaxial growth Si layer 70 on the Si block layer 50 exposing.Epitaxially grown Si layer 70, thickness is preferably 5-20nm so that after follow-up SiGe Stress Release, completely by stress transfer in Si, thereby form strained silicon.In the present embodiment, epitaxially grown Si layer 70, thickness is 10nm.
Step 8, as shown in Figure 7, carries out Implantation, makes the ion distribution of injecting at SiO
2in layer 40.The ion injecting is preferably one or more of H, He, N, Si, C, and the dosage of injection is preferably 1E13-1E18/cm
2, and the energy injecting is determined according to the thickness of the Si of different ionic speciess and SiGe layer 20 and top thereof (Si block layer 50 and Si layer 70), thus make the range of Implantation be distributed in SiO
2in layer 40.In the present embodiment, adopt H Implantation, implantation dosage is 1E15/cm
2.
Step 9, carry out annealing process, the temperature of annealing is preferably 300-1000 DEG C, and the time is 1 minute to 2 hours.Due to the damage that Implantation causes, make the stress in part SiGe layer 40 produce relaxation, thereby stress transfer is formed to strained silicon 80 in the Si material of its top extension.In the present embodiment, annealing temperature is 600 DEG C, and the time is 50 minutes.As shown in Figure 8, the strained silicon 80 of formation is used to form NMOSFET raceway groove, and the SiGe layer 40 below photoresist 60 overlay areas is used to form PMOSFET raceway groove.
Remove after photoresist, utilize this double channel material, can on the SiGe of strain material, design PMOSFET, on the Si of strain material, design NMOSFET, thereby can realize the integrated of CMOS technique.
Embodiment bis-
Adopt the processing step similar with embodiment mono-, difference is:
In step 1, epitaxially grown SiGe layer Ge content is 10%, and its THICKNESS CONTROL is at 200nm; The SiO forming in step 2
2layer thickness is 200nm; In step 3, the reinforcing temperature of bonding consolidation process is 300 DEG C, and the time is 60 minutes; Epitaxially grown Si layer in step 7, thickness is 5nm; In step 8, adopt He Implantation, implantation dosage is 1E13/cm
2; Annealing temperature in step 9 is 1000 DEG C, and the time is 1 minute.
Embodiment tri-
Adopt the processing step similar with embodiment mono-, difference is:
In step 1, epitaxially grown SiGe layer Ge content is 30%, and its THICKNESS CONTROL is at 80nm; The SiO forming in step 2
2layer thickness is 100nm; In step 3, the reinforcing temperature of bonding consolidation process is 800 DEG C, and the time is 5 minutes; Epitaxially grown Si layer in step 7, thickness is 10nm; In step 8, adopt N Implantation, implantation dosage is 1E15/cm
2; Annealing temperature in step 9 is 800 DEG C, and the time is 5 minutes.
Embodiment tetra-
Adopt the processing step similar with embodiment mono-, difference is:
In step 1, epitaxially grown SiGe layer Ge content is 40%, and its THICKNESS CONTROL is at 50nm; The SiO forming in step 2
2layer thickness is 50nm; In step 3, the reinforcing temperature of bonding consolidation process is 600 DEG C, and the time is 10 minutes; Epitaxially grown Si layer in step 7, thickness is 15nm; In step 8, adopt Si Implantation, implantation dosage is 1E16/cm
2; Annealing temperature in step 9 is 400 DEG C, and the time is 90 minutes.
Embodiment five
Adopt the processing step similar with embodiment mono-, difference is:
In step 1, epitaxially grown SiGe layer Ge content is 50%, and its THICKNESS CONTROL is at 5nm; The SiO forming in step 2
2layer thickness is 10nm; In step 3, the reinforcing temperature of bonding consolidation process is 400 DEG C, and the time is 20 minutes; Epitaxially grown Si layer in step 4, thickness is 20nm; In step 5, adopt C Implantation, implantation dosage is 1E18/cm
2; Annealing temperature in step 6 is 300 DEG C, and the time is 120 minutes.
Above-described embodiment just lists expressivity principle of the present invention and effect is described, but not for limiting the present invention.Any person skilled in the art person all can without departing from the spirit and scope of the present invention, modify to above-described embodiment.Therefore, the scope of the present invention, should be as listed in claims.
Claims (9)
1. a preparation method for the high mobility double channel material based on bonding technology, is characterized in that, comprises the following steps:
Step 1, on body silicon substrate epitaxial growth SiGe layer, as device sheet;
Step 2, another body surface of silicon is carried out to thermal oxidation, make its surface form SiO
2layer, as support chip;
Step 3, there are the surface of SiGe layer and support chip to be formed with SiO device sheet epitaxy
2the surface bond of layer, the line unit of going forward side by side closes consolidation process, forms bonding pad;
Device sheet part in step 4, para-linkage sheet is carried out grinding back surface, and the body silicon substrate at the device sheet back side is thinned to 1-10 micron, then utilizes the method for chemical corrosion to remove the remaining body silicon substrate of attenuate, exposes SiGe layer;
Step 5, on the SiGe layer exposing epitaxial growth Si block layer;
Step 6, on described Si block layer, form photoresist, utilize chemical wet etching technique that part Si block layer is exposed;
Step 7, on the Si block layer exposing, continue epitaxial growth Si layer;
Step 8, carry out Implantation, make the ion distribution of injecting at SiO
2in layer;
Step 9, carry out annealing process, make the stress in part SiGe layer produce relaxation, thereby stress transfer is formed to strained silicon in the Si material of its top extension; The strained silicon forming is used to form NMOSFET raceway groove, and the SiGe layer below photoresist overlay area is used to form PMOSFET raceway groove.
2. the preparation method of the high mobility double channel material based on bonding technology according to claim 1, is characterized in that: the thickness of the epitaxially grown SiGe layer of step 1 is 5-200nm.
3. the preparation method of the high mobility double channel material based on bonding technology according to claim 1, is characterized in that: the SiO that step 2 forms
2the thickness of layer is 10-500nm.
4. the preparation method of the high mobility double channel material based on bonding technology according to claim 1, is characterized in that: the reinforcing temperature of step 3 bonding consolidation process is 300-800 DEG C, the time is 5-60 minute.
5. the preparation method of the high mobility double channel material based on bonding technology according to claim 1, is characterized in that: the thickness of the epitaxially grown Si block of step 5 layer is 2-5nm.
6. the preparation method of the high mobility double channel material based on bonding technology according to claim 1, is characterized in that: the thickness of the epitaxially grown Si layer of step 7 is 5-20nm.
7. the preparation method of the high mobility double channel material based on bonding technology according to claim 1, is characterized in that: the ion that step 8 is injected is one or more of H, He, N, Si, C.
8. the preparation method of the high mobility double channel material based on bonding technology according to claim 1, is characterized in that: the dosage of step 8 Implantation is 1E13-1E18/cm
2.
9. the preparation method of the high mobility double channel material based on bonding technology according to claim 1, is characterized in that: the temperature of step 9 annealing is 300-1000 DEG C, and the time is 1 minute to 2 hours.
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