CN102830563B - Panel periphery connection structure and display device - Google Patents

Abstract

The invention discloses a peripheral connection structure of a panel, which comprises two signal output layers formed on a substrate, an insulating layer located on each signal output layer, and a second electrode layer arranged on the uppermost insulating layer. The two electrode layers are respectively conductively connected to the two signal output layers through conductive via holes, and the peripheral connection structure of the panel also includes a first electrode layer located under one layer of the signal output layer, and the first electrode layer has a lateral Protruding from the outer edge of the upper signal output layer layer, the second electrode layer is conductively connected to the outer edge of the first electrode layer through peripheral conductive via holes. The invention also discloses a display device comprising the connection structure. The invention can improve the green phenomenon of the screen of the display device caused by poor connection.

Description

Panel Peripheral Connection Structure and Display Device

technical field

The invention relates to the field of display technology, in particular to a panel peripheral connection structure and a display device.

Background technique

In order to produce high-quality products, the current Thin Film Transistor-Liquid Crystal Display (TFT-LCD) technology needs to introduce high-precision operations and new technologies, and the process and design between layers are also more complicated. Therefore, the design margin in the process is insufficient, and it is easy to produce defective products and affect the quality of the products. For example, the peripheral connection structure of the TFT-LCD panel in the current Advanced Super Dimension Switch (Advanced super Dimension Switch, ADS) mode (as shown by the dotted circle in Figure 1, the peripheral connection structure is mainly located at the four outer corners of the panel. Realize the position where the gate layer common electrode connection part and the source drain layer common electrode connection part are connected), as shown in Figure 2 and Figure 3, the peripheral connection structure includes the gate layer common electrode connection part 102 on the substrate 101, The gate insulating layer 103, the source-drain layer common electrode connection part 104, the insulating layer (passivation layer) 105 and the electrode layer 106, use the via hole 107 (Via Hole) to make the electrode layer 106 and the gate layer common electrode connection part 102 is electrically connected to the source-drain layer common electrode connection portion 104 to output the signal to the peripheral circuit. However, since the structure of this kind of TFT-LCD is relatively complicated, and the structure between its layers is different from that of the existing TN (Twisted Nematic) TFT-LCD, the above-mentioned defects in the connection part (such as the large area of the panel lead to Low uniformity and profile abnormalities, which make the electrode layer missing and disconnected) are quite likely to occur. Due to the existence of the above-mentioned defects, when the finished product is inspected later, phenomena such as greenish on the screen that affect the screen level will be induced, which becomes one of the reasons for reducing product quality.

Of course, this problem can be solved by improving the process, but due to the large size of the panel and the balance of the process, it is quite difficult to completely solve the problem only by improving the process.

Contents of the invention

(1) Technical problems to be solved

The technical problem to be solved by the present invention is: to provide an array substrate and a display device, so as to improve the green phenomenon of the screen of the display device caused by poor connection.

(2) Technical solution

In order to solve the above problems, the present invention provides a panel peripheral connection structure, which includes two signal output layers formed on the substrate, an insulating layer on each signal output layer, and a second electrode on the uppermost insulating layer layer, the second electrode layer is conductively connected to the two signal output layers respectively through conductive via holes, and the peripheral connection structure of the panel also includes a first electrode layer located under one layer of the signal output layer. An electrode layer has an outer edge protruding laterally beyond the upper layer of the signal output layer, and the second electrode layer is conductively connected to the outer edge of the first electrode layer through a peripheral conductive via hole.

Preferably, the two signal output layers include a gate layer common electrode connection part and a source drain layer common electrode connection part.

Preferably, the first electrode layer is located below the common electrode connection part of the gate layer.

Preferably, the first electrode layer is located below the common electrode connecting portion of the source-drain layer.

Preferably, the first electrode layer and the second electrode layer are indium tin oxide semiconductor film layers.

On the other hand, the present invention also provides a display device, including a display panel, wherein the display panel includes the above panel peripheral connection structure.

Preferably, the two signal output layers include a gate layer common electrode connection part and a source drain layer common electrode connection part.

(3) Beneficial effects

The present invention can effectively prevent poor peripheral contact caused by missing electrode layers, thereby reducing the possibility of greening of the display and improving the picture quality of the display;

When the present invention is applied to TFT-LCDs of ADS and HADS modes, it can be realized without additional technological process.

Description of drawings

Figure 1 is a schematic diagram of the position of the peripheral connection structure of the panel on the entire panel;

FIG. 2 is a schematic plan view of a peripheral connection structure of a panel in the prior art;

Fig. 3 is the sectional view of the sectional structure at A-A place in Fig. 2;

4 is a schematic plan view of a peripheral connection structure of a panel according to an embodiment of the present invention;

5 is a cross-sectional view of a peripheral connection structure of a panel according to an embodiment of the present invention;

6 is a cross-sectional view of the peripheral connection structure of the second panel of the embodiment of the present invention;

Among them: 101: substrate; 102: gate layer common electrode connection part; 103: gate insulating layer; 104: source drain layer common electrode connection part; 105: insulating layer; 106: electrode layer; 107: via hole;

201: substrate; 202: gate layer common electrode connection part; 203: insulating layer; 204: source drain layer common electrode connection part; 205: second electrode layer; 206: conductive via hole; 207: first electrode layer; 207a: the outer edge of the first electrode layer; 208: peripheral conductive vias;

301: substrate; 302: gate layer common electrode connection part; 303: insulating layer; 304: source drain layer common electrode connection part; 305: second electrode layer; 306: conductive via hole; 307: first electrode layer; 307a: the outer edge of the first electrode layer; 308: peripheral conductive vias.

Detailed ways

The present invention will be described in detail below in conjunction with the accompanying drawings and embodiments.

Embodiment one:

As shown in Figure 4 and Figure 5, this embodiment describes a panel peripheral connection structure, including two signal output layers formed on the substrate 201, an insulating layer 203 on each signal output layer, and an uppermost layer The second electrode layer 205 on the insulating layer 203, the second electrode layer 205 is electrically connected to the two signal output layers respectively through conductive vias 206, and is used for signal transmission between the panel and the peripheral circuit. The connection structure also includes a first electrode layer 207 located below the signal output layer, the first electrode layer 207 has an outer edge 207a protruding laterally beyond the level of the signal output layer above, and the second electrode layer 205 It is electrically connected to the outer edge 207 a of the first electrode layer 207 through the peripheral conductive via hole 208 .

In this embodiment, the two signal output layers include a gate layer common electrode connection portion 202 and a source drain layer common electrode connection portion 204 .

In this embodiment, the first electrode layer 207 is located below the gate layer common electrode connection portion 202 .

In this embodiment, the first electrode layer 207 and the second electrode layer 205 are indium tin oxide semiconductor film layers.

In this embodiment, even if the conductive via hole 206 part of the second electrode layer 205 directly connected to the gate layer common electrode connection part 202 is defective, the second electrode layer 205 can pass through the peripheral conductive via hole 208 and the first electrode layer 207. It is electrically connected to the gate layer common electrode connection portion 202 , therefore, poor picture quality such as greenishness caused by poor contact between the second electrode layer 205 and the gate layer common electrode connection portion 202 can be prevented.

Embodiment two:

The peripheral connection structure of the panel in this embodiment is basically the same as the structure of the first embodiment, and also includes the gate layer common electrode connection part 302 and the source-drain layer common electrode connection part 304 formed on the substrate 301, located on the gate layer The insulating layer 303 on the common electrode connecting portion 302 and the source-drain layer common electrode connecting portion 304, the second electrode layer 305 and the first electrode layer 307 disposed on the uppermost insulating layer 303, the second electrode layer 305 passes through The conductive vias 306 are conductively connected to the gate layer common electrode connection portion 302 and the source-drain layer common electrode connection portion 304 respectively, and the first electrode layer 307 has an outer edge protruding laterally beyond the upper signal output layer layer 307a, the second electrode layer 305 is conductively connected to the outer edge 307a of the first electrode layer 307 through the peripheral conductive via hole 308 .

The difference from Embodiment 1 is that, as shown in FIG. 6 , in this embodiment, the first electrode layer 307 is located below the source-drain layer common electrode connection portion 304 .

In this embodiment, even if the portion of the conductive via hole directly connected to the source-drain layer common electrode connection portion 304 is defective, the second electrode layer 305 can pass through the peripheral conductive via hole 308 and the first electrode layer 307. It is electrically connected to the source-drain layer common electrode connection portion 304 , so poor picture quality such as greenishness caused by poor contact can be prevented.

Of course, in addition to the structures shown in Embodiment 1 and Embodiment 2, all other structures that partially overlap the two signal transmission layers and connect with the second electrode layer are applicable, as long as there is space to use the first electrode layer for design That's it.

Embodiment three:

This embodiment describes a display device, which includes a display panel, and the display panel includes the peripheral connection structure of the panel described in the first embodiment.

In this embodiment, the display panel is an ADS mode liquid crystal panel, and the first electrode layer is a common electrode layer located below the common electrode connection portion of the gate layer.

Embodiment four:

This embodiment describes a display device, which includes a display panel, and the display panel includes the peripheral connection structure of the panel described in the second embodiment.

In this embodiment, the display panel is a HADS mode liquid crystal panel, and the first electrode layer is a pixel electrode layer located below the common electrode connecting portion of the source-drain layer.

It can be seen from Embodiment 3 and Embodiment 4 that the present invention is particularly suitable for being applied to TFT-LCDs of ADS and HADS modes, because in the peripheral connection structure of TFT-LCDs of ADS modes, the common electrodes of the gate layer are originally connected The bottom is provided with an electrode layer as a common electrode, and in the peripheral connection structure of the TFT-LCD of the HADS mode, an electrode layer is also provided with an electrode layer as a pixel electrode under the common electrode connection part of the source-drain layer, so for the present invention, no need for processing The first electrode layer can be formed by adding a process flow.

The above embodiments are only used to illustrate the present invention, but not to limit the present invention. Those of ordinary skill in the relevant technical field can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, all Equivalent technical solutions also belong to the category of the present invention, and the scope of patent protection of the present invention should be defined by the claims.

Claims (6)

1. A panel peripheral connection structure, comprising two layers of signal output layers formed on the substrate, an insulating layer positioned on each layer of signal output layer and a second electrode layer arranged on the uppermost insulating layer, the second electrode Layers are conductively connected to the two signal output layers respectively through conductive via holes, and it is characterized in that the peripheral connection structure of the panel further includes a first electrode located under any signal output layer of the two signal output layers layer, the first electrode layer has an outer edge protruding laterally beyond the upper signal output layer layer, and the second electrode layer is electrically connected to the outer edge of the first electrode layer through a peripheral conductive via hole so as to be connected to the The one signal output layer above the first electrode layer is conductively connected. 2 . The peripheral connection structure of the panel according to claim 1 , wherein the two signal output layers comprise a gate layer common electrode connection part and a source drain layer common electrode connection part. 3 . 3 . The peripheral connection structure of the panel according to claim 2 , wherein the first electrode layer is located below the common electrode connection portion of the gate layer. 4 . 4 . The panel peripheral connection structure according to claim 2 , wherein the first electrode layer is located below the common electrode connecting portion of the source-drain layer. 5. The panel peripheral connection structure according to any one of claims 1-4, characterized in that, the first electrode layer and the second electrode layer are indium tin oxide semiconductor film layers. 6 . A display device, comprising a display panel, characterized in that the display panel comprises the panel peripheral connection structure according to any one of claims 1 to 5 .