CN102832232B - Silicon-controlled rectifier lateral double diffused metal oxide semiconductor with high maintaining voltage - Google Patents

Abstract

A silicon controlled silicon lateral double-diffused metal oxide semiconductor transistor with high sustain voltage, comprising: N-type substrate, buried oxygen is arranged on the N-type substrate, N-type epitaxial layer is arranged on the buried oxygen, and N-type The epitaxial layer is provided with an N-type buffer well and a P-type body region, a P-type anode region and an N-type body contact region are arranged in the N-type buffer well, and an N-type cathode region and a P-type body region are arranged in the P-type body region. In the body contact region, a gate oxide layer and a field oxide layer are provided on the surface of the N-type epitaxial layer, a shallow P-type well region is provided on the surface of the N-type cathode region and the P-type body contact region, and polysilicon is provided on the surface of the gate oxide layer. The gate is characterized in that a deep N-type well region is provided directly below the P-type anode region and an N-type body contact region, and a deep P-type well region is provided directly below the shallow P-type well region. Both regions can effectively The carrier double-injection effect is effectively suppressed, so that the number of free carriers neutralized in the drift region is reduced, thereby increasing the device sustaining voltage and reducing the risk of latch-up during the discharge of static electricity.

Description

A High Sustain Voltage Thyristor Lateral Double-Diffused Metal Oxide Semiconductor Transistor

technical field

The invention mainly relates to the reliability field of high-voltage power semiconductor devices, specifically, a high-maintenance voltage thyristor lateral double-diffused metal oxide semiconductor transistor with high sustain voltage and strong anti-latch capability. It is suitable for electrostatic protection of driving chips in plasma flat panel display equipment, half bridge driving circuits and automobile production fields.

Background technique

With the increasing demand for energy saving, the performance of high-voltage power integrated circuit products has received more and more attention, and the reliability of the circuit has also attracted more and more attention from circuit design engineers. Electrostatic discharge is a very important reliability issue, and it is also one of the main causes of failure of many electronic products. With the continuous shrinking of process feature size, electronic products are more vulnerable to electrostatic discharge damage, so the demand for electrostatic protection becomes more and more intense.

At present, in the problem of electrostatic protection, it is generally on the input and output ports of the circuit to use electrostatic protection devices to form an electrostatic protection circuit. When there is electrostatic discharge, the protection circuit can be turned on first, release the electrostatic discharge current, and clamp the electrostatic discharge voltage, so that the electrostatic discharge will not cause damage to the internal circuit. When the internal circuit is working normally, the electrostatic protection circuit should not work and cannot affect or interfere with the internal circuit. Among them, in order to play an effective electrostatic protection role, the trigger voltage of the protection device should be lower than the breakdown voltage of the protected circuit, and in order to reduce the risk of latch-up, the maintenance voltage of the protection device should be higher than the power supply voltage of the circuit.

Lateral double diffused metal oxide semiconductor (LDMOS) has been widely used in electrostatic protection of high-voltage power integrated circuits because of its simple design and good process compatibility. However, when a large electrostatic current is discharged, a serious base widening effect occurs in the lateral double-diffused metal-oxide-semiconductor transistor body, resulting in a significant reduction in its electrostatic discharge capability. In order to overcome this shortcoming, people have optimized the structure of the lateral double diffused metal oxide semiconductor transistor, and proposed the Silicon-controlled rectifier lateral double diffused metal oxide semiconductor (SCR-LDMOS) ), which combines a silicon-controlled rectifier (SCR) and a lateral double-diffused metal-oxide-semiconductor transistor in the same device. When the thyristor lateral double-diffused metal oxide semiconductor transistor discharges electrostatic current, there is a double injection effect of carriers in its anode and cathode, which not only can effectively suppress the base widening effect, but also has a stronger electrostatic discharge. release ability. Therefore, the thyristor lateral double-diffused metal oxide semiconductor transistor has gradually become a very attractive electronic component in the field of electrostatic protection of high-voltage power integrated circuits.

However, the thyristor lateral double-diffused metal oxide semiconductor tube is facing a very serious reliability risk when discharging static electricity. The main problem is that there is a double injection of carriers in its anode and cathode when discharging static electricity. Effect, so that a quasi-neutral region is formed in the drift region due to the large amount of neutralization of electrons and holes, so the maintenance voltage of the thyristor lateral double-diffused metal oxide semiconductor transistor is very low, far lower than the power supply voltage of the circuit, There is a great hidden danger of latch-up, which causes great restrictions on the design and application of the thyristor lateral double-diffused metal oxide semiconductor transistor in the electrostatic protection of high-voltage power integrated circuits. Therefore, in order to use silicon controlled silicon lateral double-diffused metal oxide semiconductor transistors as electrostatic protection devices, it is necessary to improve the device structure to solve the problem that the design can realize the electrostatic discharge protection function without the risk of latch-up on a smaller area .

Surrounding the electrostatic protection of high-voltage process to the requirements of high sustain voltage, low latch-up risk and lower cost, the present invention proposes a thyristor lateral double-diffused metal oxide with high sustain voltage and effective latch-up resistance Compared with the general SCR lateral double-diffused metal-oxide-semiconductor structure under the same size, the semiconductor tube structure has a significantly higher sustain voltage, which reduces the risk of latch-up.

Contents of the invention

The invention provides a high sustaining voltage thyristor lateral double-diffused metal oxide semiconductor transistor.

The present invention adopts the following technical scheme: a silicon controlled silicon lateral double-diffused metal oxide semiconductor transistor with high sustaining voltage, comprising: an N-type substrate with embedded oxygen on the N-type substrate, and an N-type substrate on the buried oxygen. Type epitaxial layer, N-type buffer well and P-type body region are arranged inside the N-type epitaxial layer, P-type anode region and N-type body contact region are arranged in the N-type buffer well, and P-type body region is provided with The N-type negative region and the P-type body contact region are provided with a gate oxide layer and a field oxide layer on the surface of the N-type epitaxial layer, and one end of the gate oxide layer is opposed to one end of the field oxide layer, and the other end of the gate oxide layer faces The N-type negative region extends and ends at the boundary of the N-type negative region, and the other end of the field oxide layer extends toward the P-type positive region and ends at the boundary of the P-type positive region, in the N-type negative region and the P-type body contact region A shallow P-type well region is provided on the surface, and the shallow P-type well region extends below the gate oxide layer. A polysilicon gate is provided on the surface of the gate oxide layer and the polysilicon gate extends to the upper surface of the field oxide layer. In the field oxide layer, P-type A passivation layer is provided on the surface of the body contact region, the N-type cathode region, the polysilicon gate, the P-type anode region and the N-type body contact region, and a first metal layer is connected to the surface of the P-type anode region and the N-type body contact region 19, A second metal layer is connected to the surface of the polysilicon gate, a third metal layer is connected to the surface of the P-type body contact region and the N-type cathode region, and a deep N-type well is provided directly below the P-type anode region and the N-type body contact region region, the deep N-type well region is located in the N-type buffer well. The doping concentration of the deep N-type well region is five to ten times that of the N-type buffer well, and the implantation energy of the deep N-type well region is two to three times that of the N-type buffer well.

Compared with prior art, the present invention has following advantage:

(1), the device of the present invention is provided with a deep N-type well region 18 below the P-type anode region 5 and the N-type body contact region 19, which effectively reduces the emission efficiency of the parasitic PNP transistor and reduces the injection rate from the P-type anode region 5. The number of holes in the N-type epitaxial layer 3, thereby reducing the amount of space charge neutralization in the N-type epitaxial layer 3, thus increasing the sustaining voltage of the device, so that the device will fail due to the low sustaining voltage when discharging static electricity. The resulting latch failure risk is greatly reduced.

(2), the device of the present invention is provided with a deep P-type well region 17 below the N-type cathode region 15 and the P-type body contact region 14, which effectively reduces the emission efficiency of the parasitic NPN transistor and reduces the injection rate from the N-type cathode region 15. The number of electrons to the N-type epitaxial layer 3, thereby reducing the number of space charge neutralization in the N-type epitaxial layer 3, thus increasing the sustain voltage of the device, so that the device is caused by the low sustain voltage when discharging static electricity. The risk of latch failure is greatly reduced. Referring to Fig. 3, V _h1 is the holding voltage of the general structure, and V _h2 is the holding voltage of the structure of the present invention. It can be seen that compared with the general structure, the holding voltage of the structure of the present invention has been significantly improved.

(3), the device of the present invention adopts a high-voltage Silicon-On-Insulator (SOI) process, and the shallow P-type well region 13 used in this process for adjusting the threshold value of the high-voltage device and the deep P-type well for raising the sustain voltage Area 17 shares the same photoresist plate, and the two implantation windows are exactly the same, but the implantation energy and dose are different, and there is no need to add a new mask, so no additional cost will be added.

(4) The device of the present invention increases the holding voltage and reduces the risk of latch-up while not changing the original layout area of the device. At the same time, the manufacturing process of the device of the invention can be compatible with the existing CMOS process and is easy to prepare.

(5) The device of the present invention can not only effectively increase the sustain voltage, but also not affect other performance parameters of the device. For example, since the deep N-type well region 18 is located in the N-type buffer well 4, and the deep P-type well region 17 is located in the P-type body region 16, the trigger voltage of the device will not be changed due to the adoption of the device structure of the present invention. As a result, Refer to accompanying drawing 3.

Description of drawings

Figure 1 shows the device cross-sectional structure of a silicon controlled silicon lateral double-diffused metal oxide semiconductor transistor with a general structure.

FIG. 2 shows the cross-sectional device structure of the improved high sustain voltage thyristor lateral double-diffused metal oxide semiconductor transistor of the present invention.

FIG. 3 is a comparison diagram of transmission line pulse (Transmission line pulse, TLP) test results of the device of the present invention and the device of a silicon controlled silicon lateral double-diffused metal-oxide-semiconductor device with a general structure. It can be clearly seen from the figure that the maintenance voltage V _h2 of the device after the improvement is significantly higher than the maintenance voltage V _h1 of the device with the general structure. There is little difference in the trigger voltage of the devices.

Detailed ways

Below in conjunction with accompanying drawing 2, the present invention is described in detail, a kind of high sustaining voltage thyristor lateral double-diffused metal oxide semiconductor transistor, comprises: N-type substrate 1, is provided with buried oxygen 2 on N-type substrate 1, An N-type epitaxial layer 3 is arranged on the buried oxygen 2, an N-type buffer well 4 and a P-type body region 16 are arranged inside the N-type epitaxial layer 3, and a P-type positive region 5 and a P-type positive region 5 are arranged in the N-type buffer well 4. The N-type body contact region 19 is provided with the N-type negative region 15 and the P-type body contact region 14 in the P-type body region 16, and the gate oxide layer 11 and the field oxide layer 8 are arranged on the surface of the N-type epitaxial layer 3 and the gate One end of the oxide layer 11 is opposed to one end of the field oxide layer 8, the other end of the gate oxide layer 11 extends toward the N-type negative region 15 and ends at the boundary of the N-type negative region 15, and the other end of the field oxide layer 8 Extending to the P-type positive region 5 and ending at the boundary of the P-type positive region 5, a shallow P-type well region 13 is arranged on the surface of the N-type negative region 15 and the P-type body contact region 14, and the shallow P-type well region 13 extends to Below the gate oxide layer 11, a polysilicon gate 10 is provided on the surface of the gate oxide layer 11 and the polysilicon gate 10 extends to the upper surface of the field oxide layer 8. In the field oxide layer 8, the P-type body contact region 14, the N-type cathode region 15, The surfaces of the polysilicon gate 10, the P-type anode region 5 and the N-type body contact region 19 are provided with a passivation layer 7, and the surfaces of the P-type anode region 5 and the N-type body contact region 19 are connected with a first metal layer 6. The surface of 10 is connected to the second metal layer 9, and the third metal layer 12 is connected to the surface of the P-type body contact region 14 and the N-type negative region 15. It is characterized in that the P-type positive region 5 and the N-type body contact region 19 A deep N-type well region 18 is provided directly below, and the deep N-type well region 18 is located in the N-type buffer well 4 .

The doping concentration of the deep N-type well region 18 is five to ten times that of the N-type buffer well 4, and the implantation energy of the deep N-type well region 18 is two to three times that of the N-type buffer well 4. .

The doping dose of the N-type buffer well 4 is 1e13cm ^-2 , the implantation energy is 80Kev, the doping dose of the deep N-type well region 18 is 1.0e14cm ^-2 , and the implantation energy is 180Kev.

The deep N-type well region 18 overlaps with the projection of the field oxide layer 8 at the bottom of the device, and the range of the overlapping part is 0-1um.

There is also a deep P-type well region 17 directly below the shallow P-type well region 13, the deep P-type well region 17 is located in the P-type body region 16, and is located below the N-type cathode region 15 and the P-type body contact region 14, It completely coincides with the projection of the shallow P-type well region 13 on the bottom of the device.

The doping concentration of the deep P-type well region 17 is ten to twenty times that of the shallow P-type well region 13, and the implantation energy of the deep P-type well region 17 is twice that of the shallow P-type well region 13. to triple.

The doping dose of the shallow P-type well region 13 is 1.0e12cm ^-2 , the implantation energy is 80Kev, the doping dose of the deep P-type well region 17 is 1.5e13cm ^-2 , and the implantation energy is 180Kev.

The deep P-type well region 17 overlaps with the projection of the gate oxide layer 11 at the bottom of the device, and the range of the overlapping portion is 1-2 μm.

The present invention adopts following method to prepare:

The first is SOI fabrication, in which the epitaxial layer 3 is doped with N type. Next is the fabrication of silicon controlled silicon lateral double-diffused metal oxide semiconductor tubes, including forming an N-type buffer layer 4 on the N-type epitaxy 3 by implanting phosphorus ions, and the doping dose of the N-type buffer layer 4 is ^{1.e13cm- 2.} The implantation energy is 80Kev. Boron ions are implanted to form a P-type body region 16, and then implanted at high energy to form a deep N-type well region 18. The doping dose of the deep N-type well region 18 is 1e14cm ^-2 , and the implantation energy is 180Kev . Then the field oxide layer 8 is implanted with boron ions at low energy to form the shallow P-type well region 13. The doping dose of the shallow P-type well region 13 is 1.0e12cm ^-2 and the implantation energy is 80Kev. Immediately afterwards, the same photolithography plate is used to implant boron ions at high energy to form a deep P-type well region 17. The doping dose of the deep P-type well region 17 is 1.5e13cm ^-2 , and the implantation energy is 180Kev, followed by the gate oxide layer 11 After that, polysilicon 10 is deposited, etched to form a gate, and heavily doped anode region 5, cathode region 15, P-type body contact region 14 and N-type body contact region 19 are fabricated. Deposit silicon dioxide, etch the electrode contact area, deposit metal, etch the metal and lead out the electrode, and finally perform passivation treatment.

Claims (8)

1. A thyristor lateral double-diffused metal oxide semiconductor transistor with high sustaining voltage, comprising: N-type substrate (1), on which buried oxygen (2) is arranged, and buried oxygen (2) is provided with an N-type epitaxial layer (3), and an N-type buffer well (4) and a P-type body region (16) are provided inside the N-type epitaxial layer (3), and an N-type buffer well (4) A P-type anode area (5) and an N-type body contact area (19) are provided inside, and an N-type cathode area (15) and a P-type body contact area (14) are arranged in the P-type body area (16). A gate oxide layer (11) and a field oxide layer (8) are provided on the surface of the type epitaxial layer (3), and one end of the gate oxide layer (11) is offset against one end of the field oxide layer (8), and the gate oxide layer (11 ) extends to the N-type cathode region (15) and ends at the boundary of the N-type cathode region (15), and the other end of the field oxide layer (8) extends to the P-type anode region (5) and ends at the P On the boundary of the N-type anode region (5), a shallow P-type well region (13) is provided on the surface of the N-type cathode region (15) and the P-type body contact region (14), and the shallow P-type well region (13) extends to the gate Below the oxide layer (11), a polysilicon gate (10) is provided on the surface of the gate oxide layer (11), and the polysilicon gate (10) extends to the upper surface of the field oxide layer (8). In the field oxide layer (8), P-type A passivation layer (7) is provided on the surface of the body contact region (14), the N-type cathode region (15), the polysilicon gate (10), the P-type anode region (5) and the N-type body contact region (19). The first metal layer (6) is connected to the surface of the anode region (5) and the N-type body contact region (19), the second metal layer (9) is connected to the surface of the polysilicon gate (10), and the P-type body contact region (14) and the surface of the N-type cathode region (15) are connected with a third metal layer (12), which is characterized in that a deep N-type Well region (18), the deep N-type well region (18) is located in the N-type buffer well (4). 2. The silicon controlled silicon lateral double-diffused metal oxide semiconductor transistor with high sustaining voltage according to claim 1, characterized in that the doping concentration of the deep N-type well region (18) is that of the N-type buffer well (4) The implantation energy of the deep N-type well region (18) is two to three times that of the N-type buffer well (4). 3. The thyristor lateral double-diffused metal oxide semiconductor transistor with high sustaining voltage according to claim 2, characterized in that the doping dose of the N-type buffer well (4) is 1e13cm ^-2 , and the implantation energy is 80Kev , the doping dose of the deep N-type well region (18) is 1.0e14cm ^-2 , and the implantation energy is 180Kev. 4. The silicon controlled silicon lateral double-diffused metal oxide semiconductor transistor with high sustaining voltage according to claim 1, characterized in that the projection of the deep N-type well region (18) and the field oxide layer (8) on the bottom of the device Overlap, the range of the overlapping part is 0-1μm. 5. The silicon controlled silicon lateral double-diffused metal oxide semiconductor transistor with high sustaining voltage according to claim 1, characterized in that a deep P-type well region (17) is provided directly below the shallow P-type well region (13), The deep P-type well region (17) is located in the P-type body region (16), and is located below the N-type cathode region (15) and the P-type body contact region (14), and the shallow P-type well region (13) is in the The projections on the bottom of the device are completely coincident. 6. The silicon controlled silicon lateral double-diffused metal oxide semiconductor transistor with high sustaining voltage according to claim 5, characterized in that the doping concentration of the deep P-type well region (17) is that of the shallow P-type well region (13) The doping concentration is ten to twenty times, and the implantation energy of the deep P-type well region (17) is two to three times that of the shallow P-type well region (13). 7. The silicon controlled silicon lateral double-diffused metal oxide semiconductor transistor with high sustaining voltage according to claim 6, characterized in that the doping dose of the shallow P-type well region (13) is 1.0e12cm ^-2 , and the implanted energy is 80Kev, the doping dose of the deep P-type well region (17) is 1.5e13cm ^-2 , and the implantation energy is 180Kev. 8. The silicon controlled silicon lateral double-diffused metal oxide semiconductor transistor with high sustaining voltage according to claim 5, characterized in that the projection of the deep P-type well region (17) and the gate oxide layer (11) on the bottom of the device Overlap, the range of the overlapping part is 1-2μm.