CN102833201A

CN102833201A - Highway addressable remote transducer (HART) modem based on singlechip, and implementation method thereof

Info

Publication number: CN102833201A
Application number: CN2012102696225A
Authority: CN
Inventors: 张平; 谢翔; 朱爱松
Original assignee: BEIJING WISDOM XINYI TECHNOLOGY CO LTD
Current assignee: BEIJING WISDOM XINYI TECHNOLOGY CO LTD
Priority date: 2012-07-30
Filing date: 2012-07-30
Publication date: 2012-12-19
Anticipated expiration: 2032-07-30
Also published as: CN102833201B

Abstract

The invention discloses a highway addressable remote transducer (HART) modem and an implementation method of the HART modem. According to the HART modem, a data receiving module, a parallel to series conversion module and a modulation module are sequentially connected with one another and are connected with a buffering or filtration or blocking module through a first gating switch together with a half duplex control module; a data sending module, a series to parallel conversion module and a demodulation module are sequentially connected with one another; a period module and a threshold module are connected with the demodulation module through a second gating switch; a filtration or biasing module is respectively connected with the period module and the threshold module; and an isolation module is respectively connected with the buffering or filtration or blocking module and the filtration or biasing module and then connected with an input/output module. The HART modem can be implemented based on a singlechip, so that the problems of relatively high cost, single commodity supply way and the like in the prior art are solved.

Description

HART modem based on single chip microcomputer and implementation method thereof

Technical Field

The invention relates to a modem which is realized based on a single chip microcomputer and can support an HART (highway addressable Remote Transducer) protocol, and also relates to a method for realizing demodulation of the HART modem, belonging to the technical field of industrial automation.

Background

With the rapid development of industrial automation, automatic Control devices such as a PLC (Programmable logic controller), a DCS (Distributed Control System), and the like are applied in large scale in an industrial field. This puts increasing demands on the communication assurance capabilities of industrial sites. On one hand, peripheral equipment represented by a transmitter in an industrial field needs to communicate with control equipment anytime and anywhere; on the other hand, addressing means are required in the communication process so as to greatly simplify the connection mode of the control device and the peripheral device.

In the prior art, the HART protocol is recognized as an effective technical solution to meet the above requirements. The HART protocol, which was introduced by ROSEMOUNT corporation, usa in 1985, is a protocol for solving the problem of communication between field smart meters and control devices, and has become one of the industry standards for global smart meters. At present, a measurement control mode represented by a 4-20 mA current loop occupies a mainstream position in the field of industrial automation, and is delayed for a long time. The HART protocol is a communication protocol compatible with a traditional 4-20 mA current loop, and has vigorous vitality and wide market prospect.

The HART protocol has the following technical features:

1. an FSK (frequency shift keying) signal based on the Bell202 standard is adopted, an audio digital signal with the amplitude of 0.5mA is superposed on a low-frequency 4-20 mA analog signal to carry out bidirectional digital communication, and the data transmission rate can be 1.2 Mbps. The average value of the FSK signal is 0, so that the size of the analog signal transmitted to the control equipment is not influenced, and the compatibility with the existing analog system is ensured.

2. The method adopts a half-duplex communication mode to realize digital signal communication on the existing analog signal transmission line. The HART protocol is a transitional product in the process of converting an analog system into a digital system, and thus has strong market competitiveness in the current transitional period. However, due to the analog-digital mixed signal system, it is difficult to develop a communication interface chip that can meet the requirements of various companies.

3. A uniform device description language DDL is used. The field device developer describes the characteristics of the field device by using a DDL language, the HART foundation is responsible for registering and managing the device descriptions and compiling the device descriptions into a device description dictionary, and the master device uses the DDL language to understand the characteristic parameters of the field device.

The core technology for realizing the HART protocol is the modem, however, the dedicated HART modem has only a few chip manufacturers to supply, the price is high, and the supply period is not easy to be guaranteed. On the other hand, the single chip microcomputer is a general-purpose device, and through the rapid development of nearly one or two decades, the single chip microcomputer is greatly developed in the aspects of high integration level, high performance, low power consumption, low cost and the like, and particularly after analog peripherals such as an ADC (analog to digital converter), a DAC (digital to analog converter), a comparator and the like are integrated, a typical timer, an M SART (simple analog transmitter) and a GPIO (general purpose input/output) device are matched, so that a complete small system can be realized on the single chip microcomputer. If the HART modem is regarded as a small system, a proper single chip microcomputer is selected to realize the small system, so that higher cost performance can be realized.

Therefore, the chinese invention patent No. ZL 02160544.0 provides a modem based on a single chip and a method for implementing HART protocol signal transmission. The HART modem comprises a singlechip, a HART signal demodulation unit, a HART signal modulation unit, an I/O output port register, an asynchronous serial receiving module and a HART protocol signal link analysis and command processor, wherein the HART signal demodulation unit and the HART signal modulation unit are arranged in the singlechip. The corresponding method comprises the following steps: a. the HART sine wave signal is firstly subjected to band-pass filtering and then converted into a frequency shift keying signal, and then the frequency shift keying signal is input into the HART signal modulation unit from a pin of the single chip microcomputer; b. the signals of logic '0' and '1' are output to an I/O output port register after being demodulated by the HART signal modulation unit; c. the logic '0' and '1' signals are input to the asynchronous serial receiving module through the pins of the single chip microcomputer; d. the asynchronous serial receiving module receives the demodulated HART communication frame, and then sends the HART communication frame to the HART protocol signal link analysis and command processor to perform link analysis and command processing on the communication frame, and obtains logic '0' and '1' signals which are sent to the signal modulation unit to perform signal modulation; e. the demodulated square wave is output from the pin of the single chip microcomputer, and the HART sine wave signal is output after waveform shaping and transmitted.

Disclosure of Invention

The invention provides a HART modem. The HART modem is realized based on a single chip microcomputer, and can solve the problems of high cost, single supply channel and the like in the prior art.

Another technical problem to be solved by the present invention is to provide a specific method for implementing demodulation of the HART modem.

In order to achieve the purpose, the invention adopts the following technical scheme:

a HART modem, characterized in that:

the HART modem comprises a half-duplex control module, a modulation module, a demodulation module, a parallel-serial conversion module, a serial-parallel conversion module, a data receiving module, a data sending module, a buffering/filtering/blocking module, a period module, a threshold module, a filtering/biasing module, an isolation module and an input/output module; wherein,

the data receiving module, the parallel-serial conversion module and the modulation module are sequentially connected and are connected with the half-duplex control module through a first gating switch and the buffering/filtering/blocking module;

the data sending module, the serial-parallel conversion module and the demodulation module are sequentially connected, the period module and the threshold module are connected with the demodulation module through a second gating switch, and the filtering/biasing module is respectively connected with the period module and the threshold module;

the isolation module is connected with the buffering/filtering/blocking module and the filtering/biasing module respectively on one hand, and is connected with the input and output module on the other hand.

Preferably, the half-duplex control module, the modulation module, the demodulation module, the parallel-to-serial conversion module, the serial-to-parallel conversion module, the data receiving module and the data sending module are implemented by inherent modules in a single chip microcomputer.

Preferably, the singlechip is STM8L15x series singlechip.

Preferably, the modulation module is composed of a digital-to-analog converter, a direct memory access device and a timer, wherein the timer is connected with the direct memory access device, and the direct memory access device is connected with the digital-to-analog converter.

Preferably, the direct memory access device returns to the beginning of the array after traversing the sine array in the FLASH region in the chip and continues to generate the waveform of the next period.

Preferably, the demodulation module comprises a monostable trigger, a pulse width timer, a decision unit and a demodulation algorithm submodule, wherein a threshold signal passes through the monostable trigger to form an enable signal of the demodulation algorithm submodule; and inputting the periodic signal into the pulse width timer, converting the periodic signal into a symbol sequence after the periodic signal is processed by the decision unit, entering the demodulation algorithm submodule for processing, and finally outputting 0/1 data segments.

Preferably, the periodic signal is connected to a capture pin of a timer in the single chip microcomputer, the threshold signal is connected to an IO pin of the single chip microcomputer, and the PWM capture function of the timer in the single chip microcomputer is used to perform pulse width timing on the high and low level time of the periodic signal.

Preferably, the outermost side of the input/output module is provided with a transient suppression diode and a self-recovery fuse.

A method for realizing demodulation of HART modem is realized based on the HART modem, wherein a demodulation algorithm sub-module is arranged in a demodulation module; the method is characterized in that:

in the demodulation algorithm sub-module, an enabling signal is used as a gate control signal to control whether a symbol sequence is transmitted to a subsequent unit, then a symbol U which does not influence subsequent processing in the symbol sequence is filtered, and meanwhile, a falling edge detection unit is connected in parallel to monitor LS and LMS which appear in the symbol sequence;

the filtered symbol sequence and the output signal of the falling edge detection unit are input into a demodulation algorithm state machine together;

the demodulation algorithm state machine adopts a ping-pong buffer to process data, outputs effective symbol segments, converts the symbol segments into 0/1 data segments by a decision unit, and converts the data segments into bytes by a serial-parallel conversion module.

Preferably, the demodulation algorithm state machine includes four states: idle, head acknowledge, receive and post-process;

waiting for a falling edge signal while in an idle state; when the falling edge detection unit gives a falling edge signal, entering a head confirmation state;

in the head confirmation state, confirming whether the bit 0 of one complete code element period is behind the falling edge, confirming that the receiving state is successfully entered, and returning to the idle state after the confirmation failure;

maintaining a timer in a receiving state, restarting the timer when entering the receiving state, receiving complete symbol data in the period of time, and directly returning to an idle state only when an abnormal condition is detected;

after the timer is overtime, the timer enters a post-processing state, and the post-processing state maintains a soft timer; when receiving continuous data, finding a falling edge in a post-processing state, crossing an idle state, entering a head confirmation state, switching a ping-pong buffer and informing processing; and when receiving the discontinuous data or the end of the continuous data, if the soft timer is overtime, returning to an idle state, switching a ping-pong buffer and informing for processing.

The HART modem provided by the invention can be realized based on a single chip microcomputer, so that the problems of high cost, single supply channel and the like in the prior art are solved. The modulation module and the demodulation module of the HART modem are optimally designed, so that the computing capability is high, the debugging is convenient, and the application range is wide.

Drawings

Fig. 1 is an overall system block diagram of a HART modem provided in the present invention;

fig. 2 is a schematic block diagram of the modulation module in the HART modem;

FIG. 3 is a schematic circuit diagram of a buffer/filter/dc blocking module;

FIG. 4 is a schematic circuit diagram of a period module, a threshold module, and a filter/bias module;

FIG. 5 is a schematic diagram of the operation of the demodulation module;

FIG. 6 is a schematic diagram of a decision criterion for simplifying the period duration into a symbol stream;

FIG. 7 is a schematic diagram of a decision criterion for simplifying the period duration into a symbol stream;

FIG. 8 is a functional block diagram of a sub-module of the demodulation algorithm;

FIG. 9 is a schematic diagram of the operating state of the demodulation algorithm state machine;

fig. 10 is a schematic circuit diagram of the isolation module and the input/output module.

Detailed Description

The invention is described in further detail below with reference to the figures and the detailed description.

In one embodiment of the invention, the modem supporting the HART protocol is realized by adopting an STM8L15x series single chip microcomputer. The STM8L15x series single chip microcomputer is an 8-bit Microcontroller (MCU) derived from an ideological semiconductor, a 12-bit DAC (digital-to-analog converter) is arranged in the single chip microcomputer, a DMA (direct memory access) with a circulation mode and a TIMER (TIMER) used as a DMA time reference can form a modulation module. Of course, the present invention can be implemented by using other general-purpose single-chip microcomputers with similar functions, such as STM8L10x series or STM8L16x series, which are not illustrated herein.

Fig. 1 is an overall system block diagram of a HART modem provided in the present invention. The HART modem comprises an RTS (request to send)/automatic half-duplex control module (half-duplex control module for short), a modulation module, a demodulation module, a parallel-serial conversion module, a serial-parallel conversion module, an RXD (received data) module, a TXD (transmitted data) module, a buffering/filtering/blocking module, a period module, a threshold module, a filtering/biasing module, an isolation module and an input and output module. The RTS/automatic half-duplex control module, the modulation module, the demodulation module, the parallel-serial conversion module, the serial-parallel conversion module, the RXD module and the TXD module can be realized by inherent modules in an STM8L15x series single chip microcomputer. In the single chip microcomputer, an RXD module, a parallel-serial conversion module and a modulation module are sequentially connected and are connected with an RTS/automatic half-duplex control module and a buffering/filtering/blocking module through a gating switch. The modulation module is composed of a DAC, a DMA and a timer, and the technical characteristics of the invention are that. On the other hand, the TXD module, the serial-parallel conversion module and the demodulation module are sequentially connected, and the period module and the threshold module are connected with the demodulation module through the gating switch. Outside the single chip microcomputer, a filtering/biasing module is respectively connected with a period module and a threshold module. The isolation module is respectively connected with the buffer/filter/blocking module and the filter/bias module on one hand, and is connected with the input and output module on the other hand.

The data link of the HART modem in operation is such that: when modulation is carried out, after bytes to be modulated enter a single chip microcomputer through a pin of an RXD module, 0/1 code streams are obtained through a parallel-serial conversion module, the code streams are modulated into 1200Hz and 2200Hz continuous phase sine waves through a modulation module consisting of a DAC (digital-to-analog converter), a DMA (direct memory access) and a timer in the single chip microcomputer, and then the code streams are buffered/filtered/isolated outside the single chip microcomputer and loaded to an external current loop through an isolation module and an input/output module; during demodulation, a carrier wave on an external current loop enters the interior of the HART modem through the isolation module and the input and output module, is processed by the filtering/biasing module, the period module, the threshold module and the like, converts an analog waveform into a digital waveform, inputs the digital waveform into the single chip microcomputer, passes through a zero detection demodulation algorithm and a serial-parallel conversion link, and is finally output by a pin of a TXD module in the single chip microcomputer.

The HART protocol is a half-duplex protocol that can only take one of the transmit and receive states at a time. In one embodiment of the present invention, half-duplex control of the HART modem may be implemented by external RTS module pins, or may be automatically controlled by internal software. For example, the HART modem can be set to manual mode, and half-duplex control is performed through the RTS module pin of UART, or it can be changed to automatic mode by internal software, and only when there is data, it is switched to modulation mode, and at other times, it automatically returns to demodulation mode.

As mentioned above, the modulation module in the present invention is composed of DAC, DMA and timer. Fig. 2 is a schematic block diagram of the modulation module, in which the timer is connected to the DMA and the DMA is connected to the DAC. In an embodiment of the invention, the 12-bit DAC, the DMA and the timer are arranged inside and outside a chip of an STM8L15x series single chip microcomputer, all modulation operations are completed inside the single chip microcomputer, and a DAC analog output pin is used as an output end of a modulation module. In the modulation link, firstly, a UART peripheral receiving part (generally a pin of an RXD module) of the single chip microcomputer receives bytes to be modulated in an interrupt mode, then, an 0/1 code stream (1200 baud rate and odd check in HART protocol) is formed through a parallel-serial conversion module according to information such as specified baud rate and parity check, and a DAC, DMA and a timer in the single chip microcomputer jointly complete a modulation process, wherein 0 in the code stream is modulated into 2200Hz, and 1 in the code stream is modulated into 1200 Hz.

In STM8L15x series single-chip microcomputer, the conversion speed of DAC is 1-10 mus magnitude, and the access efficiency of the on-chip and the off-chip can be greatly improved by using on-chip DMA. In addition, the DMA in the chip supports a circulation mode, and after the sine array is traversed, the DMA can automatically return to the beginning of the array to continue generating the waveform of the next period. Thus, not only does kernel intervention not be required during a single waveform period, but also kernel intervention is not required for the generation of the entire continuous waveform. Since the interrupt response processing speed of the kernel is often in the order of μ s, this characteristic ensures the continuity and smoothness of the sine waveform generation.

In the modulation module shown in fig. 2, the sine table is a 12-bit read-only array in the FLASH area in the chip, and is used for outputting the sine array to the DMA so as to realize the function of generating the sine waveform. By setting the DMA, the digital quantity in the sine array can be directly input into the DAC at equal intervals, and an analog sine waveform is formed at the output end of the DAC. Obviously, the larger sine array is beneficial to reducing the step effect of the sine wave output by the DAC, but the DMA can not move the data faster than the conversion speed of the DAC. On this premise, the period of the DMA transfer data determines the frequency of the output sine wave. In an STM8L15x series single chip microcomputer, a timer is used for controlling the period of DMA transfer data. When the timer works in the periodic mode, in order to output the analog sine waveforms of 1200Hz and 2200Hz, the register parameters of the timer used as the DMA time reference can be calculated in advance, and the register parameters of the timer are switched, so that the analog sine waveforms of 1200Hz and 2200Hz can be output.

The HART protocol uses the Bell202 modulation and demodulation method, and an important characteristic of the modulation is the continuity of the waveform, i.e. the initial phase of the symbol period is required to be equal to the end phase of the previous symbol period. At the logical 0 output of 2200Hz, the symbol period and waveform period do not coincide because of the existence of this inconsistency, and specifically to a certain symbol period, the initial phase is not a definite value but depends on the previous symbol period. By using the implementation manner of the modulation module shown in fig. 2, when switching is performed between symbols, only the register parameter of the timer needs to be updated, and no operation is performed on the DMA and the DAC, the DMA still introduces the next continuous data of the sine array into the DAC to form a continuous output level, thereby satisfying the requirement of the HART protocol on waveform continuity.

The modulation module in the present invention has an enable port for implementing half-duplex control in addition to the 0/1 data stream input port. The enable port acts directly on the DAC and its output pins. When the HART modem is in a signal receiving state, the output pin of the DAC is in a high-impedance state, which is beneficial to the detection of input signals. To improve the accuracy of waveform reception, a default logic 1 (high) of 1200Hz may be generated before and after the official 0/1 data stream.

In the modulation module provided by the present invention, the DAC has an optional on-chip Buffer (Buffer), and since the on-chip Buffer has a significantly larger operating current than the off-chip low power consumption op-amp, when the modulation module has a special requirement for low power consumption, such as a HART modem, the on-chip Buffer should be disabled and the off-chip low power consumption op-amp should be used as much as possible. In addition, reducing the main frequency, shortening the sine data, properly increasing the step effect of the output waveform, and the like are also important technical measures for reducing the overall power consumption of the modulation module.

The waveform generated by modulation is sent out through a DAC output pin and is a sinusoidal signal with a step effect between 0 and a reference voltage, and the driving capability of the waveform is weak when an on-chip buffer is forbidden. From a spectral point of view, the signal has, in addition to the required 1200Hz and 2200Hz, a dc component and a high frequency component that produces a "step effect". The signal is processed by a buffering/filtering/blocking module to obtain modulation and then output.

Fig. 3 is a schematic circuit diagram of the buffering/filtering/blocking module. The buffering/filtering/blocking module comprises a first voltage follower which mainly plays a role of buffering, a second voltage follower which mainly plays a role of filtering and a capacitor which plays a role of blocking, wherein the forward input end of the first voltage follower is connected with the output end of the modulation module, the output end of the first voltage follower is connected with the forward input end of the second voltage follower after passing through an RC filter circuit, and the output end of the second voltage follower is connected with the capacitor and an isolation transformer which play a role of blocking. The working principle of the buffering/filtering/blocking module is as follows: considering that the output impedance of a DAC in the modulation module is high, buffering is achieved through the first voltage follower, the driving capability is improved, and waveform distortion is reduced. The step effect in the output waveform of the DAC can be regarded as high-frequency noise in a frequency spectrum, the RC filter circuit and the subsequent second voltage follower form a first-order low-pass filter circuit, and the first-order filter circuit can also play a good filter effect to obtain a smooth sine waveform due to the fact that the high-frequency noise of the step effect is far away from the frequency of the sine wave. In the single chip microcomputer, a DAC receives an unsigned 12-bit integer in a range of 0-4095. The sine array takes 2047 as the oscillation center, and the waveform thereafter is always a sine waveform with direct current offset, so that the direct current component is isolated by a capacitor at the end of the buffering/filtering/isolating module and before the isolating transformer. The circuit design is that although the isolation transformer also has the function of blocking, the capacitor blocking can prevent direct current components from passing through the isolation transformer, reduce loss to improve efficiency, prevent the magnetic core of the isolation transformer from being saturated, and improve the transmission performance of the isolation transformer.

In the demodulation chain, firstly, the analog signal sent by the isolation module is filtered and biased. The filtering is to reduce the high frequency noise, the bias is to provide a direct current component for the signal after the transformer blocking, and the signal amplitude is controlled in the effective level range of the peripheral circuit of the single chip microcomputer. The zero-crossing period information of the signal waveform and the amplitude information of the signal waveform are obtained through the processing of the period module and the threshold module, the two information are digital quantities, and the two information can be sent to the single chip microcomputer through the I/O port to be processed.

Fig. 4 is a circuit schematic of the period module, the threshold module, and the filter/bias module. In the filtering/biasing module, an alternating current signal from an isolation transformer enters a first-stage in-phase amplification operational amplifier circuit after passing through an RC (resistor-capacitor) filtering circuit. The operational amplifier is a single-power operational amplifier, and in order to control an alternating current signal in an effective level interval of the operational amplifier, a 100K resistor connected to Vref is added behind an RC filter circuit, and a DC blocking capacitor is added in front of the RC filter circuit. The Vref can be half or slightly less than half of the VCC voltage (which is a technical characteristic of a single power supply operational amplifier), for example, when 5V is supplied, the Vref can be 2-2.5V. The added 100K resistor and the blocking capacitor provide bias for the input pure alternating current signal, and normal work of the first-stage in-phase amplifying circuit is guaranteed. The gain of the first-stage in-phase amplifying circuit is determined by the ratio of a pair of resistors below, and generally only 1-4 times is needed.

As shown in fig. 4, the waveform processed by the first stage in-phase amplifying circuit is further processed by a dc blocking bias and enters the two following comparators. The upper period comparator (i.e. period module) is directly compared with the bias level Vref, at this time, the operational amplifier is in an open-loop working state, and a sine waveform can be processed into a square wave with the same period and the same phase. So far, the analog signal becomes a 0/1 digital signal carrying input waveform period information, and can be sent to a common IO pin of a singlechip or a timer capture pin for subsequent processing. The lower threshold comparator (i.e., threshold module) compares with a reference level slightly below Vref, and outputs a continuous high level when there is no waveform input or insufficient waveform amplitude, and outputs a series of low levels only when the input waveform amplitude is greater than a certain threshold. The threshold value can be adjusted by changing the value of the voltage dividing resistor. The series of low level or falling edge with input waveform amplitude information can be sent to a common IO pin of the singlechip for subsequent processing.

Fig. 5 is a schematic diagram illustrating the operation of the demodulation module. The demodulation module comprises a monostable trigger, a pulse width timer, a judgment unit and a demodulation algorithm submodule, wherein a threshold signal passes through the monostable trigger to form an enabling signal of the demodulation algorithm submodule; the periodic signal is input into a pulse width timer, processed by a decision unit and converted into a symbol stream (i.e. a symbol sequence), and enters a demodulation algorithm submodule for processing, and finally, an effective 0/1 data segment is output. The time delay of the monostable trigger is 1-4 code element periods, and the monostable trigger is triggered by low level, namely, only the waveform with large enough amplitude executes a demodulation algorithm. This is consistent with the specifications of the HART protocol.

In an embodiment of the invention, the periodic signal is connected with a capture pin of a timer in a singlechip, the threshold signal is connected with a common IO pin of the singlechip, and the pulse width timing of the high and low level time of the periodic signal is carried out by utilizing the PWM capture function of the timer in an STM8L15x series singlechip. The timer capture function does not need the intervention of a kernel, is irrelevant to a currently executed program, does not need operations such as interrupt response and the like, does not have the problems of interrupt nesting and the like, can be accurate to a single clock cycle, and can obtain higher accuracy than the timing of IO interrupt + a timer.

The pulse width obtained by the timer is the duration of two adjacent edges, including a rising edge and a falling edge, and is generally a 16-bit value. For an 8-bit single chip machine such as STM8L15x, the subsequent processing is relatively complex. In order to simplify the subsequent processing, the 16-bit time duration information is converted into a symbol stream through a decision unit. The specific conversion rule is shown in fig. 6, since one sine cycle corresponds to two pulse widths, ideally the pulse widths of 1200Hz and 2200Hz should be 0.5 × 1200Hz-1 and 0.5 × 2200Hz-1, which are denoted by the symbols L (long) and S (short), and the symbols L and S allow a certain range of errors in consideration of uncertainty of the initial phase, input offset of the comparator, and jitter caused by noise, as shown by the shaded portion in fig. 6.

The initial phase uncertainty also causes a larger variation, as in fig. 7 where the initial phase of 2200Hz bit 0 is 3/2 pi, and the pulse width in the middle is exactly the median of L and S, and it is more appropriate to determine that bit 0 and bit 1 each account for half, here denoted by the symbol m (middle), as in fig. 6 where the space between L and S is blank. The region below the symbol S is identified as u (under), which is generally the case when the comparator flips and the jitter caused by the high frequency noise remaining in the filtering is much smaller than the pulse width represented by the symbol S. The region above the symbol L is judged to be o (over), which is typically the case where wiring or amplitude instability results in a local absence of the waveform, resulting in a timeout.

The demodulation algorithm sub-module is a core component of the demodulation module, and is used for receiving the symbol sequence from the decision unit and outputting a valid 0/1 data segment. In the UART protocol, the idle state without data corresponds to all-1, and the HART modem remains in this all-1 state for a significant portion of time, which the demodulation algorithm sub-module considers as invalid data. Also according to the UART protocol, the start of the data is low level of 1 symbol period, it can be considered that valid data must be guided by a falling edge, and the demodulation algorithm sub-module only outputs such valid data segment.

The single chip microcomputer sends the obtained waveform period information and amplitude information to the demodulation algorithm submodule for demodulation and judgment, and an effective 0/1 code stream is obtained. Referring to fig. 2, the serial-to-parallel conversion module combines these code streams into bytes according to a certain rule, and performs parity check. If errors such as error correction and the like occur, error prompt information is output, the bytes after serial-parallel conversion are correctly transmitted through a UART peripheral transmitting part (generally a base pin of a TXD module) of the single chip microcomputer.

The functional block diagram of the sub-module of the demodulation algorithm is shown in fig. 8, where an enable signal is used as a gate control signal to control whether a symbol sequence is transmitted to a subsequent unit, then U which does not affect subsequent processing in the symbol sequence is filtered out (the symbol U is generally caused by jitter when a comparator crosses zero, and does not affect sequence decision after filtering), and meanwhile, a falling edge detection unit is connected in parallel to monitor "LS" and "LMS" appearing in the symbol sequence, and if yes, a falling edge signal is given. And the filtered symbol sequence and the output signal of the falling edge detection unit are jointly input into a demodulation algorithm state machine.

The demodulation algorithm state machine takes byte as unit, not only has certain time delay at output, but also needs to occupy a buffer area during processing. Therefore, the demodulation algorithm state machine employs a ping-pong Buffer (Buffer) to process the data. The ping-pong buffer switches the buffered data stream to the subsequent judgment unit for operation and processing without stopping through input data selection and output data selection in a beat and mutually matched manner, and can effectively solve the problems of front-back overlapping of data, parallel receiving and subsequent processing and the like in the continuous data process. The effective data segment detected by the demodulation algorithm state machine is still a symbol segment when being output by the ping-pong buffer, and the symbol segment is converted into 0/1 data segment by the subsequent decision unit and converted into bytes by the serial-parallel conversion module. The sequence of demodulation algorithm state machine outputs consists of only S, M, L, M must occur between L and S, and the switching criteria of the decision unit are as follows:

● direct switching of L and S or switching of M is symbol interval mark, which is used to divide symbol segment into subsegment and count the number of continuous symbols;

● when counting the number of continuous L and S, M is converted into 1/2L and 1/2S, as shown in FIG. 7, two types of sub-segments composed of L or S are obtained, and L sub-segment and S sub-segment are not formed;

● for L subsegments, if the number of symbols L is X, then converting into X/2 consecutive 1;

● for S subsegments, if the number of symbols S is Y, then switching to Y/3.667 consecutive 0S, where 3.667 ═ 2 × 2200Hz/1200 Hz;

fig. 9 is a schematic diagram of a demodulation algorithm state machine, which has four states: idle, header acknowledgement, receive, and post-processing. Waiting for a falling edge while in an idle state; when the falling edge detection unit gives a falling edge signal, a data head confirmation state is entered. In this state, it is confirmed whether the trailing edge is followed by bit 0 of a complete one symbol period, it is confirmed that the data reception state is successfully entered, and the idle state is returned after the confirmation failure.

The receiving state maintains a soft timer, the duration of the timer is the duration of one byte in the HART protocol. And restarting the timer when entering a receiving state, receiving the complete symbol data in the period of time, and only directly returning to the idle state when abnormal conditions such as symbol 0 and the like are detected.

The receiving timer enters a post-processing state after being overtime, and the state maintains a soft timer with the duration of a plurality of code element periods. When receiving continuous data, the 1 or 2 bit stop bit is followed by a falling edge and prompts the start of the next data, i.e. the falling edge is found in the post-processing state, the head confirmation state is entered by crossing the idle state, the ping-pong buffer is switched and the processing is informed. When receiving the end of the discontinuous data or the continuous data, the post-processing soft timer is overtime, returns to an idle state, switches the ping-pong buffer and informs processing.

In the HART protocol, the main variables and control information are transmitted by a 4-20 mA current loop. As a HART modem, the HART modem needs to be capable of being connected in a 4-20 mA current loop in a spanning mode and carrying out carrier communication under the condition that the current loop is not influenced. Therefore, after the modulation output, an isolation module and an input-output module are added. The isolation module mainly comprises an audio transformer, and the input/output module comprises a TVS (transient suppression diode), a self-recovery fuse and the like, and mainly plays a role in protection. The isolation module and the input-output module are bidirectional modules, and a sinusoidal signal to be demodulated also returns from the link.

Fig. 10 is a schematic circuit diagram of an isolation module and an input/output module of the HART modem, which has an isolation transformer and a dc blocking capacitor as the core. Since 1200Hz and 2200Hz are both in the middle of the audio, the isolation transformer can adopt the 600: the 600 audio frequency transformer, this kind of transformer number of turns is many, and the line footpath is thin, can select to use the paster type to reduce the volume. The DC blocking capacitor is used for ensuring that only the modulated and demodulated alternating current component is connected with the 4-20 mA current loop circuit and the direct current signal of the current loop is not influenced. The blocking capacitor cannot be a polar capacitor, a common 0.1u patch capacitor is adopted, and the withstand voltage is generally over 36V.

For the consideration of electromagnetic compatibility and safety, a TVS (transient suppression diode) and a self-recovery fuse are added on the outermost side of the input and output interface. Considering the 24V DC power supply used in large quantity, the withstand voltage of TVS can be 36V, which does not affect the normal use and can protect the DC blocking capacitor. The self-recovery fuse and the TVS can ensure that large voltage and large current caused by surge or misoperation enter the input and output module, and the isolation transformer is protected from being burnt.

The HART modem based on the single chip microcomputer and the implementation method thereof provided by the present invention have been explained in detail above. Any obvious modifications to the invention, which would occur to those skilled in the art, without departing from the true spirit of the invention, would constitute a violation of the patent rights of the invention and would carry a corresponding legal responsibility.

Claims

1. A HART modem, characterized in that:

2. The HART modem of claim 1, wherein:

the half-duplex control module, the modulation module, the demodulation module, the parallel-serial conversion module, the serial-parallel conversion module, the data receiving module and the data sending module are realized by inherent modules in a single chip microcomputer.

3. The HART modem of claim 2, wherein:

the singlechip is STM8L15x series singlechip.

4. The HART modem according to any of claims 1-3, wherein:

the modulation module is composed of a digital-to-analog converter, a direct memory access device and a timer, wherein the timer is connected with the direct memory access device, and the direct memory access device is connected with the digital-to-analog converter.

5. The HART modem of claim 4, wherein:

and after traversing the sine array in the FLASH area in the chip, the direct memory access device returns to the head of the array to continuously generate the waveform of the next period.

6. The HART modem according to any of claims 1-3, wherein:

the demodulation module comprises a monostable trigger, a pulse width timer, a judgment unit and a demodulation algorithm submodule, wherein a threshold signal passes through the monostable trigger to form an enabling signal of the demodulation algorithm submodule; and inputting the periodic signal into the pulse width timer, converting the periodic signal into a symbol sequence after the periodic signal is processed by the decision unit, entering the demodulation algorithm submodule for processing, and finally outputting 0/1 data segments.

7. The HART modem of claim 6, wherein:

the periodic signal is connected with a capture pin of a timer in the singlechip, the threshold signal is connected with an IO pin of the singlechip, and the pulse width timing is carried out on the high and low level time of the periodic signal by utilizing the PWM capture function of the timer in the singlechip.

8. The HART modem according to any of claims 1-3, wherein:

and the outermost side of the input and output module is provided with a transient suppression diode and a self-recovery fuse.

9. A method for implementing demodulation of HART modem based on the HART modem implementation as claimed in claim 1, wherein a demodulation algorithm sub-module is provided in the demodulation module; the method is characterized in that:

10. The method of claim 9, wherein the HART modem performs demodulation by:

the demodulation algorithm state machine includes four states: idle, head acknowledge, receive and post-process;