CN102842570A - Multiple chip packaging piece based on nickel-palladium alloy or nickel-palladium tin layer and packaging method thereof - Google Patents
Multiple chip packaging piece based on nickel-palladium alloy or nickel-palladium tin layer and packaging method thereof Download PDFInfo
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- CN102842570A CN102842570A CN2012103065475A CN201210306547A CN102842570A CN 102842570 A CN102842570 A CN 102842570A CN 2012103065475 A CN2012103065475 A CN 2012103065475A CN 201210306547 A CN201210306547 A CN 201210306547A CN 102842570 A CN102842570 A CN 102842570A
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 20
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 title claims description 17
- 229910001252 Pd alloy Inorganic materials 0.000 title 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims abstract description 43
- 229910052751 metal Inorganic materials 0.000 claims abstract description 28
- 239000002184 metal Substances 0.000 claims abstract description 28
- 238000003466 welding Methods 0.000 claims abstract description 19
- 239000003292 glue Substances 0.000 claims abstract description 18
- 239000010931 gold Substances 0.000 claims abstract 10
- 229910052737 gold Inorganic materials 0.000 claims abstract 10
- 229910000679 solder Inorganic materials 0.000 claims abstract 9
- 238000007747 plating Methods 0.000 claims description 18
- 238000005476 soldering Methods 0.000 claims description 11
- 238000002844 melting Methods 0.000 claims description 5
- 230000008018 melting Effects 0.000 claims description 5
- 238000007639 printing Methods 0.000 claims description 5
- 238000000926 separation method Methods 0.000 claims description 5
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 3
- 229910052802 copper Inorganic materials 0.000 claims description 3
- 239000010949 copper Substances 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 claims 5
- 239000000853 adhesive Substances 0.000 claims 3
- 230000001070 adhesive effect Effects 0.000 claims 3
- 239000002313 adhesive film Substances 0.000 claims 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims 1
- 238000007689 inspection Methods 0.000 claims 1
- 238000011417 postcuring Methods 0.000 claims 1
- 238000003825 pressing Methods 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
- 239000005028 tinplate Substances 0.000 claims 1
- 230000001681 protective effect Effects 0.000 abstract description 3
- 238000005516 engineering process Methods 0.000 description 15
- 238000012856 packing Methods 0.000 description 11
- 241000218202 Coptis Species 0.000 description 6
- 235000002991 Coptis groenlandica Nutrition 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 5
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000005538 encapsulation Methods 0.000 description 4
- 238000007650 screen-printing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
- 230000003319 supportive effect Effects 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000017525 heat dissipation Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 238000011017 operating method Methods 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- KDLHZDBZIXYQEI-UHFFFAOYSA-N palladium Substances [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Abstract
本发明涉及一种基于镍钯金或镍钯、锡层的多芯片封装件及其封装方法，属于集成电路封装技术领域。塑封体包围了框架内引脚、上层IC芯片、下层IC芯片、粘片胶、金属凸点、锡层、焊料、焊线构成了电路整体，对上层IC芯片、下层IC芯片、焊线起到了支撑和保护作用的塑封体包围了框架内引脚、锡层、焊料、金属凸点、上层IC芯片构成了电路的整体，上层IC芯片、下层IC芯片、焊线、金属凸点、焊料、锡层和框架内引脚构成了电路的电源和信号通道。本发明采用不同于以往的镀金属凸点，同时，利用焊料将芯片各凸点与框架管脚焊接，压焊时，不用打线，直接完成了芯片与管脚间的导通、互连，具有低成本、高效率的特点。
The invention relates to a multi-chip packaging part based on nickel-palladium-gold or nickel-palladium-tin layer and a packaging method thereof, belonging to the technical field of integrated circuit packaging. The plastic package surrounds the pins in the frame, the upper IC chip, the lower IC chip, the glue, the metal bump, the tin layer, the solder, and the welding wire to form the whole circuit, which plays a role in the upper IC chip, the lower IC chip, and the welding wire. The supporting and protective plastic package surrounds the pins, tin layer, solder, metal bumps, and upper IC chip in the frame to form the whole circuit. The upper IC chip, lower IC chip, bonding wire, metal bump, solder, tin Layers and pins within the frame form the circuit's power and signal paths. The present invention adopts metal-plated bumps different from the past, and at the same time, uses solder to weld the bumps of the chip and the frame pins. During pressure welding, the conduction and interconnection between the chip and the pins are directly completed without wire bonding. It has the characteristics of low cost and high efficiency.
Description
Technical field
The present invention relates to a kind of multicore chip package and method for packing thereof, belong to integrated circuit encapsulation technology field based on NiPdAu or nickel palladium, tin layer.
Background technology
The fast development of microelectric technique; The increase of integrated circuit complexity; The most function of an electronic system all possibly be integrated in (being SOC(system on a chip)) in the single-chip, and this just correspondingly requires microelectronics Packaging to have higher performance, more lead-in wire, closeer intraconnections, littler size or bigger chip chamber, bigger heat dissipation function, better electrical property, higher reliability, lower single lead-in wire cost etc.Chip package process is changed to wafer level packaging by Chip Packaging one by one, and wafer chip level chip encapsulation technology---WLCSP has just in time satisfied these requirements, has formed noticeable WLCSP technology.
Wafer chip level chip-scale package (Wafer Level Chip Scale Packaging; Be called for short WLCSP), promptly the wafer stage chip packaged type is different from (the envelope survey again of cutting earlier of traditional Chip Packaging mode; And increase the volume of former chip 20% after the encapsulation at least); This kind state-of-the-art technology is on the full wafer wafer, to carry out packaging and testing earlier, just cut into IC particle one by one then, so volume after being encapsulated promptly is equal to the life size of the naked crystalline substance of IC.The packaged type of WLCSP, shorten product sizes significantly not only, and meet the high density demand of running gear for the body space; In the performance of usefulness, more promoted the speed and stability of transfer of data on the other hand.In traditional WLCSP technology, adopt sputter, photoetching, electroplating technology or silk screen printing on wafer, to carry out the mint-mark of circuit.Following flow process is the operating procedure of the wafer of accomplishing preceding road technology being carried out the WLCSP encapsulation:
(1) separator flow process (Isolation Layer)
(2) contact hole flow process (Contact Hole)
(3) pad lower metal layer flow process (UBM Layer)
(4) for electroplating the photoetching flow process (Photolithography for Plating) of preparing
(5) electroplate flow process (Plating)
(6) flow process (Resist Romoval) is removed on the barrier layer
Tradition WLCSP complex manufacturing process, high to the accuracy requirement of plating and photoetching, and cost is higher.
Summary of the invention
The present invention be directed to above-mentioned existing WLCSP defective workmanship; A kind of multicore chip package and method for packing thereof based on NiPdAu or nickel palladium, tin layer proposed; Adopt the plating salient point of chemical plating metal salient point, sputter, photoetching, plating or silk-screen printing technique different from the past, simultaneously, utilize scolder each salient point of chip and the welding of framework pin; During pressure welding; Without routing, directly accomplished conducting, interconnection between chip and pin, this multi-chip stacking packaging part has low cost, high-efficiency characteristics.
The technical scheme that the present invention adopts: a kind of multicore chip package based on NiPdAu or nickel palladium, tin layer comprises bonding wire 8, the plastic-sealed body 9 of 1 of tin layer 2 on frame inner pin 1, the frame inner pin, scolder 3, metal salient point 4, upper strata IC chip 5, bonding die glue or glue film 6, the IC of lower floor chip 7, the IC of lower floor chip 7 and frame inner pin; It is whole that plastic-sealed body 9 has surrounded frame inner pin 1, upper strata IC chip 5, the IC of lower floor chip 7, bonding die glue 6, metal salient point 4, tin layer 2, scolder 3, bonding wire 8 has constituted circuit; Plastic-sealed body 9 that upper strata IC chip 5, the IC of lower floor chip 7, bonding wire 8 have been played support and protective effect has surrounded the integral body that frame inner pin 1, tin layer 2, scolder 3, metal salient point 4, upper strata IC chip 5 have constituted circuit, and upper strata IC chip 5, the IC of lower floor chip 7, bonding wire 8, metal salient point 4, scolder 3, tin layer 2 and frame inner pin 1 have constituted the power supply and the signalling channel of circuit.
Described bonding die glue 6 usefulness glue films replace; Bonding wire 8 is gold thread or copper cash.
A kind of method for packing of the multicore chip package based on NiPdAu or nickel palladium, tin layer, can carry out according to following steps:
The first step, wafer attenuate;
The thickness of wafer attenuate is 50 μ m～200 μ m, roughness Ra 0.10mm～0.30mm;
Second step, plating salient point;
Chip nip metallic nickel porpezite or nickel palladium surface plating 2～50um metal salient point 4 on the full wafer wafer;
The 3rd step, scribing;
The above wafer of 150 μ m adopts common scribing process; The wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer of one deck 2～50um on frame inner pin 1;
The 5th goes on foot, goes up core
During last core, the IC of lower floor chip 7 turns around, adopts the technology of Flip-Chip, utilizes scolder that each salient point of chip and framework pin are welded; Upper strata IC chip 5 adopts bonding die glue 6 and lower floor's chip 7 to bond together;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together gold thread on IC chip 5 nips and frame inner pin 1 through melting tin;
The 7th step, pressure welding;
Be connected pressure welding between upper strata chip 7 and the frame inner pin with bonding wire 8;
The 8th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 9th step, tinization.
Described framework adopts the NiPdAu framework then need not do the tin processing.
Beneficial effect of the present invention:
(1) adopt the plating salient point, chemical plating metal salient point, sputter, photoetching, plating or silk-screen printing technique different from the past have low cost, high-efficiency characteristics.
(2) technology of employing Flip-Chip does not use the DAF film bonding, but adopts scolder with each salient point of chip and the welding of framework pin, during pressure welding, without routing, in last core, has just accomplished conducting, interconnection between chip and pin.
Description of drawings
Fig. 1 is a structural representation of the present invention;
Among the figure: tin layer, 3-scolder, 4-metal salient point, 5-IC chip, 6-bonding die glue, 7-IC chip, 8-bonding wire, 9-plastic-sealed body on 1-frame inner pin, the 2-frame inner pin.
Embodiment
Below in conjunction with accompanying drawing and embodiment the present invention is further specified, understand to make things convenient for the technical staff.
As shown in Figure 1: a kind of multicore chip package based on NiPdAu or nickel palladium, tin layer comprises bonding wire 8, the plastic-sealed body 9 of 1 of tin layer 2 on frame inner pin 1, the frame inner pin, scolder 3, metal salient point 4, upper strata IC chip 5, bonding die glue or glue film 6, the IC of lower floor chip 7, the IC of lower floor chip 7 and frame inner pin; It is whole that plastic-sealed body 9 has surrounded frame inner pin 1, upper strata IC chip 5, the IC of lower floor chip 7, bonding die glue 6, metal salient point 4, tin layer 2, scolder 3, bonding wire 8 has constituted circuit; Plastic-sealed body 9 that upper strata IC chip 5, the IC of lower floor chip 7, bonding wire 8 have been played support and protective effect has surrounded the integral body that frame inner pin 1, tin layer 2, scolder 3, metal salient point 4, upper strata IC chip 5 have constituted circuit, and upper strata IC chip 5, the IC of lower floor chip 7, bonding wire 8, metal salient point 4, scolder 3, tin layer 2 and frame inner pin 1 have constituted the power supply and the signalling channel of circuit.
Described bonding die glue 6 usefulness glue films replace; Bonding wire 8 is gold thread or copper cash.
Embodiment 1
A kind of method for packing of the multicore chip package based on NiPdAu or nickel palladium, tin layer, can carry out according to following steps:
The first step, wafer attenuate;
The thickness of wafer attenuate is 50 μ m, roughness Ra 0.10mm;
Second step, plating salient point;
Chip nip metallic nickel porpezite surface plating 2um metal salient point 4 on the full wafer wafer;
The 3rd step, scribing;
The wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer of one deck 2um on frame inner pin 1;
The 5th goes on foot, goes up core
During last core, the IC of lower floor chip 7 turns around, adopts the technology of Flip-Chip, utilizes scolder that each salient point of chip and framework pin are welded; Upper strata IC chip 5 adopts bonding die glue 6 and lower floor's chip 7 to bond together;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together gold thread on IC chip 5 nips and frame inner pin 1 through melting tin;
The 7th step, pressure welding;
Be connected pressure welding between upper strata chip 7 and the frame inner pin with bonding wire 8;
The 8th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 9th step, tinization.
A kind of multicore chip package based on NiPdAu or nickel palladium, tin layer, can carry out according to following steps:
The first step, wafer attenuate;
The thickness of wafer attenuate is 130 μ m, roughness Ra 0.20mm;
Second step, plating salient point;
Chip nip metallic nickel palladium surface plating 25um metal salient point 4 on the full wafer wafer;
The 3rd step, scribing;
The wafer of thickness below 150 μ m adopts double-pole scribing machine and technology thereof;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer of one deck 25um on frame inner pin 1;
The 5th goes on foot, goes up core
During last core, the IC of lower floor chip 7 turns around, adopts the technology of Flip-Chip, utilizes scolder that each salient point of chip and framework pin are welded; Upper strata IC chip 5 adopts bonding die glue 6 and lower floor's chip 7 to bond together;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together gold thread on IC chip 5 nips and frame inner pin 1 through melting tin;
The 7th step, pressure welding;
Be connected pressure welding between upper strata chip 7 and the frame inner pin with bonding wire 8;
The 8th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 9th step, tinization.
Embodiment 3
A kind of method for packing of the multicore chip package based on NiPdAu or nickel palladium, tin layer, can carry out according to following steps:
The first step, wafer attenuate;
The thickness of wafer attenuate is 200 μ m, roughness Ra 0.30mm;
Second step, plating salient point;
Chip nip metallic nickel porpezite or nickel palladium surface plating 50um metal salient point 4 on the full wafer wafer;
The 3rd step, scribing;
The above wafer of 150 μ m adopts common scribing process;
The 4th step, the framework corresponding region is zinc-plated;
The PAD corresponding region plates the tin layer of one deck 50um on frame inner pin 1;
The 5th goes on foot, goes up core
During last core, the IC of lower floor chip 7 turns around, adopts the technology of Flip-Chip, utilizes scolder that each salient point of chip and framework pin are welded; Upper strata IC chip 5 adopts bonding die glue 6 and lower floor's chip 7 to bond together;
The 6th step, Reflow Soldering;
Adopt SMT reflow soldering process afterwards, handle, weld together gold thread on IC chip 5 nips and frame inner pin 1 through melting tin;
The 7th step, pressure welding;
Be connected pressure welding between upper strata chip 7 and the frame inner pin with bonding wire 8;
The 8th step, plastic packaging, back curing, printing, product separation, check, packing etc. are all identical with common process;
The 9th step, tinization.
Embodiment 4
A kind of method for packing of the multicore chip package based on NiPdAu or nickel palladium, tin layer is coated with NiPdAu or NiPdAu and belongs to salient point 4 and tin layer 2, if then it goes without doing the tin processing of NiPdAu framework.
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103065475A CN102842570A (en) | 2012-08-21 | 2012-08-21 | Multiple chip packaging piece based on nickel-palladium alloy or nickel-palladium tin layer and packaging method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2012103065475A CN102842570A (en) | 2012-08-21 | 2012-08-21 | Multiple chip packaging piece based on nickel-palladium alloy or nickel-palladium tin layer and packaging method thereof |
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| CN102842570A true CN102842570A (en) | 2012-12-26 |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030160316A1 (en) * | 2002-02-26 | 2003-08-28 | Wen-Lo Shieh | Open-type multichips stack packaging |
| CN102263078A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | WLCSP (Wafer Level Chip Scale Package) packaging component |
| CN102263070A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | Wafer level chip scale packaging (WLCSP) piece based on substrate packaging |
| CN202564322U (en) * | 2012-05-09 | 2012-11-28 | 江苏长电科技股份有限公司 | Single-island embedded type single-circle multi-chip flip-mounting up-mounting package structure |
-
2012
- 2012-08-21 CN CN2012103065475A patent/CN102842570A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030160316A1 (en) * | 2002-02-26 | 2003-08-28 | Wen-Lo Shieh | Open-type multichips stack packaging |
| CN102263078A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | WLCSP (Wafer Level Chip Scale Package) packaging component |
| CN102263070A (en) * | 2011-06-13 | 2011-11-30 | 西安天胜电子有限公司 | Wafer level chip scale packaging (WLCSP) piece based on substrate packaging |
| CN202564322U (en) * | 2012-05-09 | 2012-11-28 | 江苏长电科技股份有限公司 | Single-island embedded type single-circle multi-chip flip-mounting up-mounting package structure |
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Application publication date: 20121226 |