CN102855213B - A kind of instruction storage method of network processing unit instruction storage device and the device - Google Patents

Abstract

The invention discloses a network processor instruction storage device and an instruction storage method of the device, which can save hardware resources. The network processor includes more than two microengine groups, and each microengine group includes N microengines, and the N microengines include more than two microengine groups, and the instruction storage device includes: Qmem, Cache, the first low-speed instruction memory and the second low-speed instruction memory, wherein: each microengine corresponds to a Qmem and a cache, Qmem is set to be connected to the microengine, and the cache is connected to Qmem; each microengine group corresponds to a first low-speed Instruction memory, the cache corresponding to each microengine in the microengine group is connected to the first low-speed instruction memory; each microengine large group corresponds to a second low-speed instruction memory, and the cache corresponding to each microengine in the microengine large group is connected to the first low-speed instruction memory The two low-speed instruction memories are connected. Adopting this solution saves a lot of hardware storage resources.

Description

A network processor instruction storage device and the instruction storage method of the device

technical field

The invention relates to the Internet field, in particular to a network processor instruction storage device and an instruction storage method of the device.

Background technique

With the rapid development of the Internet (Internet), the interface rate of the core router used for backbone network interconnection has reached 100Gbps. This rate requires the line card of the core router to be able to quickly process the messages passing through the line card. Currently, most industries use multi-core networks. The structure of the processor. The fetching efficiency of instructions is a key factor affecting the performance of multi-core network processors.

In a network processor system with a multi-core structure, the same group of micro engines (Micro Engine, ME for short) has the same instruction requirements. Due to the limitation of chip area and process, it is impossible to equip each micro engine with an exclusive storage space to Store these instructions. Therefore, it is necessary to design a corresponding scheme to realize the sharing of a piece of instruction storage space by a group of microengines, and at the same time, it can have higher instruction fetch efficiency.

Some traditional multi-core network processors use a multi-level cache structure. For example, each micro-engine is equipped with a separate first-level cache, and a group of micro-engines share a second-level cache structure to share storage space, as shown in Figure 1. . These caches have a large space to ensure the hit rate, but due to the randomness of network packets, the locality of instructions is not strong, so large-capacity caches cannot guarantee the efficiency of instruction fetching, and also cause a lot of waste of resources.

Some other network processors adopt a polling instruction storage scheme, and store the instructions required by a group of micro-engines in the same amount of RAM as the micro-engines, as shown in Figure 2, in which 4 micro-engines pass an arbitration The module polls the instructions in the 4 RAMs. Each microengine accesses all RAMs sequentially, and their accesses are always in different "phases", so there will be no collision between different microengines accessing the same RAM, and the sharing of storage space is realized. However, because there are a large number of jump instructions in the instructions, assuming that for a micro-engine with a pipeline structure, it takes n clocks from the start of fetching the jump instruction to the completion of the jump, in order to ensure that the target of a certain jump instruction is within the In the n+1th RAM behind the RAM where the jump instruction is located, some empty instructions must be inserted when writing the instruction to ensure that the jump target position is correct. When jump instructions account for a large proportion, a large number of empty instructions need to be inserted, which causes a lot of waste of instruction space, and also increases the complexity of compiler implementation. This scheme requires that all RAMs can return data within one clock cycle, which must be implemented with SRAM, but the use of a large number of SRAMs also causes a large amount of resource overhead.

Contents of the invention

The technical problem to be solved by the present invention is to provide a network processor instruction storage device and an instruction storage method of the device, which can save hardware resources.

In order to solve the above-mentioned technical problems, the present invention provides a network processor instruction storage device, the network processor includes more than two large groups of micro-engines, each large group of micro-engines includes N micro-engines, and the N micro-engines include More than two microengine groups, the instruction storage device includes: fast memory (Qmem), cache (cache), first low-speed instruction memory and second low-speed instruction memory, wherein:

Each microengine corresponds to a Qmem and a cache, Qmem is set to be connected to the microengine, and the cache is connected to Qmem;

Each microengine group corresponds to a first low-speed instruction memory, and the cache corresponding to each microengine in the microengine group is connected to the first low-speed instruction memory;

Each large group of microengines corresponds to a second low-speed instruction memory, and the cache corresponding to each microengine in the large group of microengines is connected to the second low-speed instruction memory.

Further, the Qmem is used to judge whether the Qmem has the instruction data after receiving the instruction data request sent by the microengine, and if so, return the instruction data to the microengine, and if not, send the instruction data to the cache ask.

Further, the Qmem stores an instruction of an address segment that requires the highest processing quality.

Further, the cache includes two Cache Lines, each Cache Line stores a plurality of consecutive instructions, and the Cache Line is used to determine whether the cache has the instruction data after receiving the instruction data request sent by Qmem, if If yes, return the instruction data to the microengine through Qmem, if not, send the instruction data request to the first low-speed instruction memory or the second low-speed instruction memory.

Further, the two Cache Lines adopt a ping-pong operation and are synchronized with the ping-pong operation of the message memory.

Further, the device further includes a first arbitration module, a second arbitration module and a third arbitration module, wherein:

Each microengine corresponds to a first arbitration module, and the first arbitration module is connected to the cache of each microengine;

Each microengine group corresponds to a second arbitration module, one end of the second arbitration module is connected to the first arbitration module of each microengine in the microengine group, and the other end is connected to the first low-speed instruction memory;

Each large microengine group corresponds to a third arbitration module, one end of the third arbitration module is connected to the first arbitration module of each microengine, and the other end is connected to the second low-speed instruction memory.

Further, the first arbitration module is used for judging whether the requested instruction is located in the first low-speed instruction memory or in the second low-speed instruction memory when cache requesting instruction data, and sending the request to the first low-speed instruction memory or the second low-speed instruction memory Sending a request for instruction data; and receiving instruction data returned by the first low-speed instruction memory or the second low-speed instruction memory, and returning the instruction data to the cache;

The second arbitration module is configured to select an instruction data request and send it to the first low-speed instruction memory for processing when receiving one or more instruction data requests sent by the first arbitration module, and after fetching the first low-speed instruction memory Get the command data and return it to the corresponding first arbitration module;

The third arbitration module is configured to select an instruction data request and send it to the second low-speed instruction memory for processing when receiving one or more instruction data requests sent by the first arbitration module, and fetch instructions from the second low-speed instruction memory The obtained command data is returned to the corresponding first arbitration module.

Further, the cache is also used to update cache contents and tags after receiving the instruction data returned by the first arbitration module.

Further, each large microengine group includes 32 microengines, the 32 microengines include 4 microengine groups, and each microengine group includes 8 microengines.

In order to solve the above technical problems, the present invention also provides an instruction storage method of an instruction storage device, the instruction storage device is the above-mentioned instruction storage device, and the method includes:

After receiving the instruction data request sent by the micro-engine, the fast memory (Qmem) judges whether the Qmem has the instruction data, and if so, returns the instruction data to the micro-engine, and if not, sends the instruction data request to the cache;

A Cache Line in the cache memory, after receiving the command data request sent by Qmem, judges whether this cache has the command data, if there is, then the command data is returned to the microengine by Qmem, if not, then to the first low-speed The instruction memory or the second low-speed instruction memory sends an instruction data request;

After receiving the instruction data request sent by the cache, the first low-speed instruction memory searches for the instruction data, and returns the found instruction data to the cache;

After the second low-speed instruction memory receives the instruction data request sent by the cache, it searches for the instruction data, and returns the found instruction data to the cache.

Further, the method also includes:

When a Cache Line in the cache judges that the cache does not have the instruction data, it sends the instruction data request to the first arbitration module, and if the first arbitration module judges that the requested instruction is located in the first low-speed instruction memory, it sends the instruction data to the first low-speed instruction memory. A low-speed instruction memory sends an instruction data request, and if the requested instruction is located in the second low-speed instruction memory, request instruction data from the second low-speed instruction memory.

Further, the method also includes:

If the first arbitration module judges that the requested instruction is located in the first low-speed instruction memory, it sends an instruction data request to the second arbitration module, and the second arbitration module receives the instruction data sent by one or more first arbitration modules When requesting, select an instruction data request and send it to the first low-speed instruction memory;

If the first arbitration module judges that the requested instruction is located in the second low-speed instruction memory, it sends an instruction data request to the third arbitration module, and the third arbitration module receives the instruction data sent by one or more first arbitration modules When requesting, select an instruction data request and send it to the second low-speed instruction memory.

The fast memory and cache-based instruction storage solution suitable for multi-core network processors provided by the embodiment of the present invention combines fast memory, small-capacity cache with ping-pong operation, and low-speed DRAM memory, wherein the memory adopts hierarchical grouping strategy. Adopting this kind of instruction storage scheme can effectively guarantee the high fetching efficiency and high average fetching efficiency of some instructions, and save a lot of hardware storage resources, and the implementation of the compiler is also very simple.

Description of drawings

Fig. 1 is a schematic structural diagram of a traditional two-level Cache;

Fig. 2 is a schematic structural diagram of an instruction storage scheme in a polling mode;

3 is a schematic structural diagram of an instruction storage device in Embodiment 1;

FIG. 4 is a schematic structural diagram of a specific instruction storage device;

Fig. 5 is the schematic diagram of message memory and icache ping-pong operation;

Fig. 6 is a flow chart of instruction storage device processing;

Fig. 7 is a detailed processing flowchart of an instruction storage device;

Fig. 8 is a working process diagram of a Cache Line in the Cache module in the present invention.

detailed description

The present invention considers combining a fast memory (Quick Memory, Qmem for short) with a small-capacity cache (Cache) using ping-pong operations, and a low-speed RAM memory (such as a low-speed instruction memory (IMEM for short)) as a micro-engine cache .

In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

Example 1

The instruction memory of this embodiment is shown in Figure 3, adopts the following structure:

A large group of N microengines is divided into two or more groups, each microengine corresponds to a Qmem and a Cache, and each group of microengines corresponds to a first low-speed instruction memory (hereinafter referred to as IMEM). The engine corresponds to a second low-speed instruction memory (hereinafter referred to as IMEM_COM), as shown in Figure 3, Qmem is set to be connected to the micro-engine, and the cache is connected to Qmem; the cache corresponding to each micro-engine in the micro-engine group is connected to the first low-speed instruction memory connected; the cache corresponding to each microengine in the large group of microengines is connected to the second low-speed instruction memory, wherein:

The Qmem is used to judge whether the Qmem has the instruction data after receiving the instruction data request sent by the microengine, and if so, return the instruction data to the microengine, and if not, send the instruction data request to the cache. The Qmem preferably stores instructions of an address segment that requires the highest processing quality, and is preferably implemented by an SRAM with a fast read and write speed. The content in Qmem will not be updated during the message processing process. When the micro-engine needs this part of the instruction, Qmem can return the instruction data required by the micro-engine within one clock cycle, which greatly improves the efficiency of instruction fetching;

The Cache has two Cache Lines (no common Chinese technical terms), each Cache Line can store multiple consecutive instructions, and the Cache Line is used to determine whether the cache has the instruction data after receiving the instruction data request sent by Qmem , if there is, return the instruction data to the microengine through Qmem, if not, send the instruction data request to IMEM or IMEM_COM. The two Cache Lines adopt the form of ping-pong operation and are synchronized with the ping-pong operation of the message memory;

The above-mentioned IMEM and IMEM_COM are respectively used to store a piece of instructions located in different address segments, and search for and return instruction data based on instruction data requests.

The above four storage locations: Qmem, Cache, IMEM, IMEM_COM, the access speed also decreases in turn. The use of hierarchical memory can effectively utilize the difference in the probability of instruction execution, thereby optimizing the efficiency of the microengine to fetch instructions. Since more low-speed memories are used, hardware resources are saved.

Preferably, the device further includes a first arbitration module (arbiter1), a second arbitration module (arbiter2) and a third arbitration module (arbiter3). Each microengine corresponds to an arbiter1, and the arbiter1 is connected to the cache of each microengine; each microengine group corresponds to an arbiter2, and one end of the arbiter2 is connected to the arbiter1 of each microengine in the microengine group, and the other end is connected to IMEM ; Each microengine group corresponds to an arbiter3, one end of the arbiter3 is connected to the arbiter1 of each microengine, and the other end is connected to IMEM_COM.

The arbiter1 is used to determine whether the requested instruction is located in IMEM or IMEM_COM when the cache requests instruction data, and sends an instruction data request to IMEM or IMEM_COM; and is used to receive the instruction data returned by IMEM or IMEM_COM, and return the instruction data to the cache ;

The arbiter2 is used to select an instruction data request and send it to the IMEM for processing when receiving one or more instruction data requests sent by the arbiter1, and return the instruction data obtained after the IMEM fetches the instruction to the corresponding arbiter1;

The arbiter3 is used to select an instruction data request and send it to IMEM_COM for processing when receiving one or more instruction data requests sent by arbiter1, and return the instruction data obtained after fetching the instruction from IMEM_COM to the corresponding arbiter1.

Taking N=32 as an example, each group of 32 microengines can be divided into 4 groups, and each group has 8 microengines. As shown in Figure 4, each microengine corresponds to a Qmem and a Cache (including two instruction caches (icache)), each group of 8 microengines shares an IMEM, and each group of 32 microengines shares an IMEM_COM. In Figure 4, A1 represents arbiter1, A2 represents arbiter2, and A3 represents arbiter3. As shown in Figure 5, the two icaches correspond to the two message memories in the ME one by one, and they work in turn to cover the delay of message storage and instruction fetching.

Example 2

Corresponding to the instruction storage device shown in Figure 3, the corresponding instruction storage method is shown in Figure 6, including:

Step 1, after receiving the instruction data request sent by the microengine, Qmem judges whether the Qmem has the instruction data, if so, returns the instruction data to the microengine, and if not, sends the instruction data request to the cache;

Step 2, after a Cache Line in the cache receives the command data request sent by Qmem, it judges whether the cache has the command data, if so, returns the command data to the microengine through Qmem, and if not, sends the command data to IMEM or IMEM_COM sends instruction data request;

Step 3: After receiving the instruction data request sent by the cache, IMEM searches for the instruction data and returns the found instruction data to the cache; after receiving the instruction data request sent by the cache, IMEM_COM searches for the instruction data and returns the found instruction data to the cache command data.

Specifically, for any microengine, the process of fetching instructions is shown in Figure 7, including the following steps:

Step 110, the microengine sends the required instruction address and address enable to the Qmem of the microengine;

Specifically, when the message memory in the microengine receives the message, it sends the instruction header address and address enable in the message to the instruction storage device, that is, the Qmem corresponding to the microengine.

Step 120, Qmem judges whether the instruction address is within the address range of its stored instruction, if so, then execute step 130, otherwise execute step 140;

Step 130, use the instruction address and the address to enable fetching instruction data to return to the microengine, and this instruction fetching process ends;

Step 140, transmit the instruction address and address enable to the Cache of the microengine;

Step 150, Cache judges whether the instruction address is within the address range of its stored instruction, if yes, execute step 160, otherwise execute step 170;

Since each part of the Cache has only one Cache Line, the tag (Tag) of the Cache has only one tag information. When the address request is sent to the Cache, it can be judged immediately according to the tag whether the required data is in the Cache, that is, the The corresponding bit of the instruction address is compared with the tag corresponding to the currently working CacheLine. If they are the same, it means that the instruction is in the Cache; otherwise, it means that the instruction is not in the Cache.

Step 160, based on the address enabling, the instruction data corresponding to the position in the Cache Line is taken out and sent to the microengine through Qmem, and the fetching process ends;

Step 170, Cache sends the instruction address and address enable to the first arbitration module (arbiter1);

Step 180, arbiter1 judges whether the instruction address is in the IMEM corresponding to the group where the microengine is located, or in the IMEM_COM corresponding to the microengine group where the microengine is located, if it is in IMEM, then execute step 190, if it is in IMEM_COM, then Execute step 210;

Specifically, arbiter1 judges whether the instruction is in IMEM or in IMEM_COM according to the instruction address;

Step 190, arbiter1 sends the instruction address and address enable to the second arbitration module (arbiter2);

Step 200, arbiter2 selects an instruction request and sends it to IMEM, and IMEM enables fetching instruction data according to the instruction address and address in the request, returns it to Cache through arbiter1, and executes step 230;

When arbiter1 corresponding to multiple micro-engines sends an instruction fetch request to arbiter2, arbiter2 processes the requests of each cache through polling, selects an instruction fetch request and sends it to IMEM for processing. Since the data return requires multiple clock cycles, it has already sent The requested branch will no longer be polled;

Step 210, arbiter1 sends the instruction address and address enable to the third arbitration module (arbiter3);

Step 220, arbiter3 selects an instruction request and sends it to IMEM_COM, and IMEM_COM enables fetching instruction data according to the instruction address and address in the request, returns it to Cache through arbiter1, and executes step 230;

The function of the arbiter corresponding to each microengine is the same as that of arbiter1, and the function of arbiter3 is the same as that of arbiter2.

Step 230, updating the contents of Cache Line and tag, and returning the instruction data to the microengine through Qmem, and this fetching process ends.

Figure 8 is a schematic diagram of the structure of the icache in Figure 5. After the icache receives the instruction address sent by Qmem, it compares it with the tag to determine whether it is a hit. If it is a hit, after decoding, the physical storage location of the slave icache is enabled according to the address. Fetch the instruction content and output it through the multiplexer. If it misses, it will continue to fetch the instruction data from the low-speed instruction memory, and the returned instruction data will be output through the multiplexer.

Only one of the Cache Lines is used to work when processing the same packet. When the Cache Line1 used by the current message finds the corresponding instruction data in the Cache and does not issue a read request to the lower-level low-speed memory (IMEM or IMEM_COM), at this time, if Cache Line2 detects that there is an address of the first address in the next message request, use the instruction header address contained in the next message to send a read request to the lower-level low-speed memory, so as to obtain the required instruction data of the next message. After the current Cache Line 1 packet is processed, the Cache switches to the other half of the Cache Line 2 to prepare for processing the next packet. In this way, the use of ping-pong operations to process messages can effectively cover up the time of message storage and the delay in fetching instructions from the low-speed instruction memory, and the required instructions can be fetched immediately when the microengine switches to the next message. The instruction fetching efficiency is improved, so that the processing efficiency of the micro-engine is improved.

Those skilled in the art can understand that all or part of the steps in the above method can be completed by instructing relevant hardware through a program, and the program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk or an optical disk, and the like. Optionally, all or part of the steps in the foregoing embodiments may also be implemented using one or more integrated circuits. Correspondingly, each module/unit in the foregoing embodiments may be implemented in the form of hardware, or may be implemented in the form of software function modules. The present invention is not limited to any specific combination of hardware and software.

Of course, the present invention can also have other various embodiments, and those skilled in the art can make various corresponding changes and deformations according to the present invention without departing from the spirit and essence of the present invention, but these corresponding Changes and deformations should belong to the scope of protection of the appended claims of the present invention.

Claims (12)

1. a kind of network processing unit instruction storage device, network processing unit includes big group of more than two micro engines, each micro- to draw Holding up big group includes N number of micro engine, and N number of micro engine is divided into more than two micro engine groups, the instruction storage device bag Include：Fast storage Qmem, caching cache, the first low speed instruction memory and the second low speed instruction memory, wherein：

Each one Qmem and caching of micro engine correspondence, Qmem is set to be connected with micro engine, and caching is connected with Qmem；

The corresponding caching of each micro engine in one the first low speed instruction memory of each micro engine group correspondence, micro engine group It is connected with the first low speed instruction memory；

The corresponding caching of each micro engine in one the second low speed instruction memory of each big group of correspondence of micro engine, big group of micro engine It is connected with the second low speed instruction memory.

2. device as claimed in claim 1, it is characterised in that：

The Qmem is used for after the director data request of micro engine transmission is received, and judges whether this Qmem has the instruction number According to if so, director data then is returned into micro engine, if it is not, sending director data request to caching.

3. device as claimed in claim 1 or 2, it is characterised in that：

The instruction to handling one address field of quality requirement highest is stored in the Qmem.

4. device as claimed in claim 1, it is characterised in that：

The caching includes two Cache Line, each Cache Line and deposits a plurality of continuous instruction, the Cache Line is used for after the director data request of Qmem transmissions is received, and judges whether this caching has the director data, if so, then Director data is returned into micro engine by Qmem, if it is not, to the first low speed instruction memory or the second low speed instruction Memory sends director data request.

5. device as claimed in claim 4, it is characterised in that：

Described two Cache Line use ping-pong operation form, and synchronous with the ping-pong operation of packet storage device.

6. the device as described in claim 1 or 2 or 4 or 5, it is characterised in that：

Described device also includes the first arbitration modules, the second arbitration modules and the 3rd arbitration modules, wherein：

One the first arbitration modules of each micro engine correspondence, first arbitration modules are connected with the caching of each micro engine；

It is each in one the second arbitration modules of each micro engine group correspondence, one end of second arbitration modules and micro engine group First arbitration modules of micro engine are connected, and the other end is connected with the first low speed instruction memory；

One the 3rd arbitration modules of each big group of correspondence of micro engine, one end of the 3rd arbitration modules and the first of each micro engine Arbitration modules are connected, and the other end is connected with the second low speed instruction memory.

7. device as claimed in claim 6, it is characterised in that：

First arbitration modules, in cache request director data, judging that asked instruction refers to positioned at the first low speed Make memory still be located at the second low speed instruction memory, sent out to the first low speed instruction memory or the second low speed instruction memory Director data is sent to ask；And for receiving the instruction number that the first low speed instruction memory or the second low speed instruction memory are returned According to the director data is returned into caching；

Second arbitration modules, during for being asked in the director data for receiving one or more first arbitration modules transmissions, One director data request of selection is sent to the processing of the first low speed instruction memory, will be obtained after the first low speed instruction memory fetching Corresponding first arbitration modules are returned to director data；

3rd arbitration modules, during for being asked in the director data for receiving one or more first arbitration modules transmissions, One director data request of selection is sent to the processing of the second low speed instruction memory, will be obtained after the second low speed instruction memory fetching Corresponding first arbitration modules are returned to director data.

8. device as claimed in claim 7, it is characterised in that：

The caching is additionally operable to after the director data of the first arbitration modules return is received, and updates cache contents and label.

9. the device as described in claim 1,2,4,5,7 or 8, it is characterised in that：

Each big group of micro engine includes 32 micro engines, and 32 micro engines are divided into 4 micro engine groups, and each micro engine is small Group includes 8 micro engines.

10. a kind of instruction storage method of instruction storage device, the instruction storage device is instruction as claimed in claim 1 Storage device, methods described includes：

Fast storage Qmem judges whether this Qmem has the instruction number after the director data request of micro engine transmission is received According to if so, director data then is returned into micro engine, if it is not, sending director data request to caching；

A Cache Line in the caching judge whether this caching has after the director data request of Qmem transmissions is received The director data, if so, director data then is returned into micro engine by Qmem, if it is not, to the first low speed instruction Memory or the second low speed instruction memory send director data request；

The first low speed instruction memory is after the director data request that caching is sent is received, look-up command data, Xiang Huan Deposit the director data for returning and finding；

The second low speed instruction memory is after the director data request that caching is sent is received, look-up command data, Xiang Huan Deposit the director data for returning and finding.

11. method as claimed in claim 10, it is characterised in that：

Methods described also includes：

Director data request is sent to by the Cache Line in the caching when judging this caching without the director data First arbitration modules, first arbitration modules judge asked instruction if located in the first low speed instruction memory, then to the One low speed instruction memory sends director data request, and the instruction asked is if located in the second low speed instruction memory, to the Two low speed instruction memory requests director datas.

12. method as claimed in claim 11, it is characterised in that：

Methods described also includes：

First arbitration modules judge asked instruction if located in the first low speed instruction memory, then to the second arbitration mould Block sends director data request, and the director data that second arbitration modules receive one or more first arbitration modules transmissions please When asking, one director data request of selection is sent to the first low speed instruction memory；

First arbitration modules judge asked instruction if located in the second low speed instruction memory, then to the 3rd arbitration mould Block sends director data request, and the director data that the 3rd arbitration modules receive one or more first arbitration modules transmissions please When asking, one director data request of selection is sent to the second low speed instruction memory.