CN102867843B - Isolated transistors and diodes and isolation and termination structures for semiconductor die - Google Patents

Abstract

Various integrated circuit devices, especially transistors, are formed within an isolation structure comprising a bottom isolation region and a trench extending from the surface of the substrate to the bottom isolation region. The trench may be filled with a dielectric material or may have a conductive material in the center portion and a dielectric material lining the walls of the trench. Various techniques for terminating the isolation structure by extending the bottom isolation region beyond the trench, employing a guard ring, and forming a drift region are described.

Description

Isolated transistors and diodes, isolation and termination structures for semiconductor die

This application is a divisional application of Chinese patent application 200980115026.8 with a filing date of February 25, 2009 and an invention title of "isolated transistor and diode, isolation and termination structure for semiconductor die".

Cross References to Related Applications

This application is a continuation-in-part of Application No. 12/069,941 filed February 14,2008.

This application is a continuation-in-part of Application No. 11/890,993, filed August 8,2007. Application No. 11/890,993 is a continuation of Application No. 11/444,102 filed May 31, 2006 and is a continuation-in-part of: (a) Application No. .10/918,316, which is a divisional application of Application No. 10/218,668, filed August 14, 2002, now U.S. Patent No. 6,900,091; (b) Application No. .11/204,215, which is a divisional application of Application No. 10/218,678, filed Aug. 14, 2002, now US Patent No. 6,943,426. Each of the aforementioned applications and patents is hereby incorporated by reference in its entirety.

Background technique

During the manufacture of semiconductor integrated circuit (IC) chips, it is often necessary to electrically isolate different devices from a semiconductor substrate and from each other. One method of providing lateral isolation between devices is the well-known local oxidation of silicon (LOCOS, Local Oxidation Of Silicon) process, in which the surface of the chip is masked with a relatively hard material, such as silicon nitride, and a thicker oxide layer thermally grown in the openings of the mask. Another approach is to etch a trench in the silicon and then fill the trench with a dielectric material such as silicon oxide, also known as trench isolation. Although both LOCOS and trench isolation can prevent unwanted surface conduction between them, they do not facilitate complete electrical isolation.

Complete galvanic isolation is required to integrate certain types of transistors, including bipolar junction transistors and various metal-oxide-semiconductor (MOS) transistors, including power DMOS transistors. Complete isolation is also required to allow the CMOS control circuitry to float to potentials well above the substrate potential during operation. Complete isolation is also especially important in the manufacture of analog, power and mixed-signal integrated circuits.

Although conventional CMOS wafer fabrication provides high density transistor integration, it does not facilitate complete electrical isolation of the fabricated devices. In particular, NMOS transistors contained in a conventional CMOS transistor pair fabricated in a P-type substrate have a P-well "body" or "back gate" shorted to the substrate and therefore cannot float above ground potential. This limitation substantially prevents NMOS from being used as a high-side switch, as a pass transistor, or as a bidirectional switch. It also makes current sensing more difficult and often prevents the use of integrated source-body shorts, which are needed to make the NMOS more avalanche rugged. Furthermore, since the P-type substrate in conventional CMOS is typically biased to the most negative on-chip potential (defined as "ground potential"), each NMOS necessarily suffers from undesirable substrate noise.

Complete electrical isolation of integrated devices is typically achieved using triple diffusion, epitaxial junction isolation, or dielectric isolation. The most common form of complete galvanic isolation is junction isolation. Although not as ideal as dielectric isolation (where an oxide surrounds each device or circuit), junction isolation has historically provided the best compromise between manufacturing cost and isolation performance.

For conventional junction isolation, electrically isolating CMOS requires a complex structure that includes growing an N-type epitaxial layer on a P-type substrate, which is electrically connected to the P-type substrate by a deep P-type isolation. An annular ring surrounds to form a fully isolated N-type epitaxial island with P-type material underneath and on all sides. The growth of epitaxial layers is slow and time-consuming, representing the most expensive single step in the semiconductor wafer fabrication process. Isolated diffusion is also more expensive, is performed using high temperature diffusion and lasts longer (up to 18 hours). To be able to suppress parasitic devices, the heavily doped N-type buried layer (NBL) must also be masked and selectively introduced prior to epitaxial growth.

To minimize updiffusion during epitaxial growth and isolation diffusion, a slow diffusion agent such as arsenic (As) or antimony (Sb) is chosen to form the N-type buried layer (NBL). However, the NBL layer must be diffused deep enough to reduce its surface concentration prior to epitaxial growth, otherwise the concentration control of the epitaxial growth will be adversely affected. Since the NBL includes a slow diffusing agent, the diffusion process before the epitaxy will take more than ten hours. Only after isolation is complete, conventional CMOS fabrication can begin, adding considerable time and complexity to the fabrication of the junction isolation process compared to conventional CMOS processes.

Junction isolation fabrication methods rely on high temperature processes to form deeply diffused junctions and grow epitaxial layers. These high-temperature processes are expensive and difficult to perform, and they are not compatible with large-diameter wafer fabrication, exhibit considerable variability in device electrical performance and prevent high transistor integration densities. Another disadvantage of junction isolation is that there is area wasted by the isolation structure that cannot be used to fabricate active transistors or circuits. As a further complication, with junction isolation, the design rules (and the amount of wasted area) depend on the maximum voltage of the device being isolated. Clearly, conventional epitaxial junction isolation, despite its electrical advantages, is too wasteful in area to remain a viable technology option for mixed-signal and power integrated circuits.

An alternative method for isolating integrated circuit devices is disclosed in US Patent No. 6,855,985, which is incorporated herein by reference. The module process disclosed therein for the integration of fully isolated CMOS, bipolar and DMOS (BCD) transistors can be achieved without the need for high temperature diffusion or epitaxy. The modular BCD process uses high-energy (MeV) ion implantation through oxides with specific profile shapes to fabricate self-forming isolation structures, virtually eliminating the need for high-temperature processing. This low thermal budget process will benefit from an "as-implanted" dopant profile that undergoes little or no dopant re-diffusion since no high-temperature process is used. diffusion.

Dopants implanted through the LOCOS field oxide form conformal isolation structures, which in turn are used to surround and isolate multi-voltage CMOS, bipolar transistors, and other devices from a common P-type substrate. This same process can be used for integrated bipolar transistors as well as various dual-junction DMOS power devices, all tuned by conformal chainedion implantation of different doses and energies.

Although this "epi-less" low thermal budget technology has many advantages over non-isolated and epitaxial junction-isolated processes, in some cases its reliance on LOCOS limits its scaling to Smaller dimensions and the ability to achieve higher transistor densities. The principle of conformal ion implantation in the LOCOS-based module BCD process is: by implanting through a thicker oxide layer, the dopant atoms will be located close to the silicon surface; by implanting through a thinner oxide layer, the implanted atoms will be Located deep in the silicon away from the surface.

As described, a fully isolated BCD process with implants profiled by LOCOS and readily achievable using 0.35 micron based technology may have problems scaling to smaller dimensions and achieving tighter linewidths. In order to improve the integration density of CMOS transistors, preferably, the bird's beak cone of the field oxide layer can be reduced to a more vertical structure, so that devices can be placed more densely to achieve higher packaging density. However, the narrow LOCOS beak narrows the width of the isolation sidewall and sacrifices isolation quality.

In situations where these issues are significant, it would be desirable to have new strategies for fully isolating integrated circuit devices, especially high voltage devices, using epitaxial-free integrated circuit processes with low thermal budgets, but eliminating the aforementioned narrow sidewall issues to allow denser isolation structure.

Contents of the invention

Embodiments according to the invention are generally formed in a semiconductor substrate of a first conductivity type that does not include an epitaxial layer. An embodiment of an isolated lateral DMOS transistor (LDMOS) includes a bottom isolation region of a second conductivity type and a dielectric-filled trench extending from a surface of a substrate to the bottom isolation region, the trench forming a substrate with the bottom isolation region isolation bag. The LDMOS includes a well of the first conductivity type in an isolated pocket, the well serving as the body of the LDMOS, the well comprising a shallow portion located near the surface of the substrate, the deep portion located below the shallow portion, and the shallow portion The deep portion has a first doping concentration, and the deep portion has a second doping concentration higher than the first doping concentration.

In a second embodiment of isolated LDMOS, the trench comprises a conductive material in a central portion and the walls of the trench are lined with a dielectric material. The isolation bag includes a drift region of the second conductivity type adjacent to the drain region and a shallow trench isolation (STI) structure in the isolation bag adjacent to the substrate surface, and the STI structure is surrounded by the drift region from sides and bottom. The isolation pocket may include a buried snapback control region of the first conductivity type under the source region and/or the drain region.

In an isolated quasi-vertical DMOS (QVDMOS) according to the invention, the trench comprises a conductive material in the central part and the walls of the trench are lined with a dielectric material. The isolation pocket includes a source region of the second conductivity type at the surface of the substrate. Current flows horizontally from the source region through the channel region under the gate, and then vertically flows to the bottom isolation region included in the drain of the QVDMOS.

In an isolated junction field effect transistor (JFET) according to the invention, the trench comprises a conductive material in a central portion and the walls of the trench are lined with a dielectric material. The isolation pocket includes source and drain regions of the first conductivity type and a top gate region of the second conductivity type on the surface of the substrate. A channel region of the first conductivity type is located between the bottom of the top gate region and the bottom isolation region.

In a second embodiment of an isolated junction field effect transistor (JFET), the isolated pocket includes source and drain regions of the second conductivity type, a top gate region of the first conductivity type at the substrate surface, and a buried A bottom gate region of the first conductivity type in the substrate. A channel region of the second conductivity type is located between the bottom of the top gate region and the upper boundary of the bottom gate region.

In a depletion mode MOSFET according to the invention, the trench comprises a conductive material in the central part and the walls of the trench are lined with a dielectric material. The isolation bag includes a source region and a drain region of the second conductivity type, and the doping concentration of the channel region under the gate is substantially equal to the background doping concentration of the substrate. In order to reduce impact ionization and suppress snapback, a buried region of the first conductivity type may be at least partially formed under the gate.

In the isolated diode according to the invention, the isolated pocket comprises an anode region of the first conductivity type. The bottom isolation region serves as the cathode of the diode and is contacted by the conductive material in the trench.

The invention also includes termination structures for areas outside the isolation pockets that border the trenches. A guard ring of the first conductivity type may be formed at the surface of the substrate outside the isolation pocket, and the bottom isolation region may extend laterally beyond an outer edge of the trench. A buried region of the first conductivity type may be formed under the guard ring. A drift region of the second conductivity type may be formed adjacent to the surface of the substrate and the trench outside the isolated pocket. One or more additional trenches comprising a dielectric material may be formed within the drift region or in the substrate between the trench and the guard ring.

Description of drawings

Figure 1 shows a cross-sectional view of a fully isolated N-channel lateral DMOS (LDMOS);

Figure 2 shows a cross-sectional view of an alternative embodiment of an isolated N-channel LDMOS;

Figure 3 shows a cross-sectional view of an isolated N-channel quasi-vertical DMOS;

Figure 4 shows a cross-sectional view of an isolated P-channel JFET;

Figure 5 shows a cross-sectional view of an isolated N-channel JFET;

Fig. 6 shows a cross-sectional view of an N-channel depletion MOSFET.

Figure 7 shows a cross-sectional view of an isolated diode;

Figure 8 shows a cross-sectional view of an isolated Zener diode;

9A-9D show cross-sectional views of termination structures for controlling surface electric fields and for reducing charging and time-dependent surface-related phenomena.

Detailed ways

Figure 1 schematically shows a cross-sectional view of a fully isolated N-channel lateral DMOS (LDMOS) 400 fabricated in accordance with the present invention that does not require epitaxial deposition or high temperature diffusion to be fabricated. LDMOS 400 is fabricated in isolated P-type region 464. The P-type region 464 and the lateral DMOS 400 fabricated in the P-type region 464 are isolated from the P-type substrate 461 by a high-energy implanted N-type bottom isolation region (floorisolation region) 462 and trenches 463A and 463B filled with dielectric.

N-channel LDMOS 400 includes: N+ drain region 468B, separated from gate 474 by implanted N-type lightly doped drain region (LDD) 469, and separated from trench 463B by LDD 476 region; gate 474 , preferably comprising polysilicon and/or silicide; gate oxide layer 472; N+ source region 468A; and P+ body contact region 467, contacting P-type well 465 comprising the body region of LDMOS 400. The P-type well 465 may include at least an upper portion 465A and a lower portion 465B or any number of regions including implants of different energies and doses. The deeper portion 465B of the P-type well 465 may preferably include a higher doping concentration than the upper portion 465A of the P-type well 465 .

Sidewall spacers 473 and lightly doped source extensions 471 are artifacts of CMOS fabrication that are not beneficially required for proper operation of LDMOS 400 . Due to its relatively high doping concentration, the effect of source extension 471 on LDMOS 400 is negligible.

The bottom isolation region 462 electrically contacts the surface of the substrate 461 through the N-type well 466 and the N+ contact region 468D. The region where well 466 is located is bounded by trenches 463A and 463C. Obviously, the trenches 463B and 463C may be part of a single trench in the shape of a closed figure, and the trench 463A may divide the portion of the substrate 461 surrounded by the trenches 463B and 463C into regions including the source region 468A, the drain region 468B and a first portion of P-type well 465 and a second portion including well 466 .

DN bottom isolation region 462 may be electrically biased to the potential of DMOS drain region 468B, P-type well 464, substrate 461, or other fixed or variable potential. The maximum voltage difference between the bottom isolation region 462 and the drain region 468B is limited to the NIN punch-through breakdown voltage between the bottom isolation region 462 and the drain region 468B, while the bottom isolation region 462 and the P-type The maximum voltage difference between wells 465 is set by the PIN reach-through breakdown voltage between bottom isolation region 462 and P-type well 465 . In one embodiment, bottom isolation region 462 and drain region 468B are electrically shorted, eliminating the possibility of NIN punch-through and limiting the BV _DSS of LDMOS 400 to between P-type well 465 and DN bottom isolation region 462 The pin avalanche breakdown voltage. In another embodiment, the bottom isolation region 462 and the substrate 461 are electrically shorted such that the P-type well 465 can be biased below ground potential, ie a more negative potential than the substrate 461 . Another alternative is to "float" bottom isolation region 462, where the potential of bottom isolation region 462 can change until NIN punch-through to N+ drain region 468B occurs, such that the potential of bottom isolation region 462 will follow that of drain region 468B. electric potential.

Although isolated N-channel LDMOS 400 is asymmetrical, it can also be constructed symmetrically, with N+ drain region 468B in the center. Alternatively, LDMOS 400 can be built centered on P-type well 465.

While the outer edges of LDMOS 400 may coincide with trenches 463B and 463C, in an alternative embodiment N-type termination region 478 biased to the potential of drain region 468B may surround trench 463C and add LDMOS 400 With respect to the breakdown voltage of the substrate 461 . If the trenches 463B and 463C are both in the shape of a closed figure, the termination region 478 may be disposed adjacent to the entire outer periphery of the trenches 463B and 463C. LDMOS 400 may also be surrounded by P+ substrate contact region 474 and/or deeply implanted P-type region 475.

2 shows a schematic diagram of an isolated N-channel lateral DMOS 300, which is manufactured in a P-type region 341B, which is connected to a P-type substrate by deep implanting an N-type bottom isolation region 360 and filling trenches 361. 341A isolation. In a preferred embodiment, filled trenches 361 surround LDMOS 300 to provide lateral isolation, while bottom isolation regions 360 provide vertical isolation. Trench 361 includes a conductive central portion 363 laterally surrounded and isolated by insulating sidewalls 364 . Conductive central portion 363 provides electrical contact between bottom isolation region 360 and the surface of substrate 341A to facilitate interconnection.

LDMOS 300 includes a central N+ drain region 348B and an N-type drift region 342 bounded by a gate 355 disposed on top of a gate dielectric layer 362 . In a preferred embodiment, a dedicated implant is used to form drift region 342 to tune its doping profile for optimized LDMOS 300 performance. In another embodiment, the dedicated drift region 342 can be replaced by an N-type well shared with other CMOS devices, which reduces the production cost while taking into account the performance of the LDMOS 300 .

Gate 355 overlaps a portion of drift region 342 and is surrounded by N+ source region 348A and P+ body contact region 347 . P-type well 343 , preferably comprising a boron chain implant region with a non-Gaussian or non-monotonic doping concentration profile, is located locally under gate 355 and forms the body region of LDMOS 300 . P-type well 343 may include a non-monotonic doping profile including at least upper portion 343A and lower portion 343B or any number of regions including implants of different energies and doses. The lower portion 343B of the P-type well 343 preferably includes a higher doping concentration than the upper portion 343A of the P-type well 343 . In the embodiment shown in FIG. 2 , the ends of the P-type well 343 are spaced laterally from the drift region 342 . As a result, the channel of LDMOS 300 has two doping concentrations, the heavier concentration of P-type well 343 sets the threshold voltage of LDMOS 300 and prevents punch-through breakdown, and the lower concentration of region 341B determines the avalanche breakdown of LDMOS 300 Breakthrough voltage and impact ionization. In another embodiment, the P-type well 343 is adjacent to the drift region 342 , wherein the channel of the LDMOS 300 has a single doping concentration which is equal to the doping concentration of the P-type well 343 .

The drift region 342 is partially under a shallow trench isolation (STI) structure 346 , ie, a shallow trench filled with silicon oxide. One benefit of including STI 346 above drift region 342 is that the net integrated charge of drift region 342 located below STI 346 is reduced due to the removal of dopants during trench formation. The net integrated charge of drift region 342, in atoms/cm ² , is the integral of the dopant concentration in drift region 342 from the silicon oxide interface at the bottom of STI 346 to the bottom of drift region 342, i.e.

${\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; Trench</span>}}<span\; class="notranslate">\; =</span>\underset{{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; trench</span>}}}{\overset{{\mathrm{<span\; class="notranslate">\; x</span>}}_{\mathrm{<span\; class="notranslate">\; j</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; drift</span>}<span\; class="notranslate">\; )</span>}{<span\; class="notranslate">\; \&Integral;</span>}}{\mathrm{<span\; class="notranslate">\; N</span>}}_{\mathrm{<span\; class="notranslate">\; Drift</span>}}<span\; class="notranslate">\; (</span>\mathrm{<span\; class="notranslate">\; x</span>}<span\; class="notranslate">\; )</span>\mathrm{<span\; class="notranslate">\; dx</span>}<span\; class="notranslate">\; \&equiv;</span>\mathrm{<span\; class="notranslate">\; \&alpha;</span>}<span\; class="notranslate">\; \&Center\; Dot;</span>{\mathrm{<span\; class="notranslate">\; Q</span>}}_{\mathrm{<span\; class="notranslate">\; D.</span>}}$

The variable α represents the percentage of the injected standard charge that remains in the drift region 342 after the formation of the STI 346, ie, the dopant that was not removed when the trench holding the STI 346 was etched. The reduction in charge results in a weakening of the surface electric field beneath the gate 355, and combined with the field plate effect of the gate 355, reduces impact ionization and reduces the risk of hot carrier damage.

Controlling the location of breakdown and the amount of impact ionization are important considerations in fabricating reliable and robust high voltage and power LDMOS devices. Including body region 343 in LDMOS 300 helps prevent punch-through breakdown and reduces the sensitivity of LDMOS 300 to bipolar injection and snapback by limiting the gain of parasitic lateral NPN bipolar transistors present in LDMOS 300, The parasitic lateral NPN bipolar transistor includes an emitter represented by source region 348A, a base represented by body region 343 and region 341B, and a collector represented by drain region 348B and drift region 342 . However, the bulk of LDMOS 300 is not immune to snapback induced by modulation of the background doping concentration caused by localized impact ionization in drift region 342 .

According to the invention, two methods are used to control snapback. In the first approach, referring again to FIG. 2 , implanted deep P-type region 365 is placed under source region 348A and is used to suppress the electric field under the gate and move the location of high electric field away from the high current density region. This approach is referred to herein as "subsurface shielding," and the deep P-type region 365 may be referred to as a subsurface shielding region. The second method is to clamp the maximum drain voltage of the LDMOS 300 to a voltage below which the snapback occurs so that the snapback phenomenon does not occur. This approach is referred to herein as "drain clamping" and may be implemented by introducing DP region 366 below drain region 348B. DP region 366 concentrates the vertical electric field under drain region 348B to force bulk, ie, non-surface, avalanche breakdown away from hot carrier sensitive gate dielectric layer 362 . DP region 366 may also be referred to as a drain clamp region.

An alternative to the lateral DMOS transistor is the quasi-vertical DMOS transistor. In a lateral DMOS, the lightly doped drift region through which current flows laterally, ie, parallel to the wafer surface. In quasi-vertical DMOS, current flows both laterally and vertically (ie, substantially perpendicular to the wafer surface). Current flows from the device's DMOS surface channel region down into the heavily doped subsurface where it flows laterally, and then flows vertically back to the drain contact, hence the name "quasi-vertical".

FIG. 3 shows a schematic cross-sectional view of an N-channel quasi-vertical DMOS (QVDMOS) transistor 500 . The device comprises: a gate 510 , preferably formed as a series of stripes or a closed geometry; an N+ source region 506 ; a P-type body region 504 ; and a P+ body contact region 505 . The P body region is formed inside the N-type well 502, the N-type well 502 includes the drift region of the QVDMOS 500 and overlaps on the N-type bottom isolation region 501, and the bottom isolation region 501 is buried in the P-type substrate 511 and is included In the drain of the QVDMOS 500.

Filled trench 507 laterally surrounds QVMDOS 500, providing isolation from other devices fabricated in substrate 500. Filling the central portion of the trench 507 is a conductive material 508 extending down from the surface of the substrate 500 to the bottom isolation region 501 . Conductive material 508 is laterally surrounded by insulating material 509 that lines the sidewalls of trench 507 such that conductive material 508 is electrically isolated from N-well 502 and substrate 511 . When the QVDMOS 500 is in the conduction state, the electron flow passes from the N+ source region 506, laterally through the channel formed at the surface of the P body region 504, vertically downward through the N- well 502, laterally through the bottom isolation region 501 and Vertically up through the conductive material 508 filling the trench 507 . Thus, contacts from the surface of the substrate 511 to the source region 506 and the drain (bottom isolation region 501 ) can be easily achieved.

In cases where the P-body region 504 will not be self-aligned with the gate 510, the P-body region 504 may be implanted before the gate 510 is formed. Alternatively, the P-body region 504 may be implanted after the gate 510 is formed by a high tilt angle implant, so that the P-body region 504 is self-aligned to the edge of the gate 510 . The high tilt angle implantation allows the formation of a substantial overlap of the P-body region 504 with the gate 510 without requiring high temperature diffusion.

In another embodiment of QVMDOS (not shown), sidewall spacers and N-type lightly doped source region edges are formed on each gate 505 as artifacts of CMOS fabrication using the same gate layer. edge. As shown in FIG. 3, if a dedicated gate layer is used to form the gate 505, no sidewall spacers will be present within the device. Otherwise, where the N+ source region is self-aligned with the gate 510, the N+ source region is self-aligned with the sidewall spacers and the N- source extension will be self-aligned with the gate.

The subsurface shielding and drain clamping techniques described above may be combined with any variation of the drain and drain extension structures made in accordance with the present invention.

JFETs and Depletion Mode MOSFETs

Unlike conventional enhancement-mode MOSFETs which are "normally-off" _devices , JFETs and depletion-mode MOSFETs still conduct leakage current even when their gates are biased to their source potential, i.e., they still conduct current. Such devices are convenient in forming a current source for starting a circuit because the transistor is normally "on" while the other transistors are not yet in operation.

In a depletion-mode N-channel FET, the threshold voltage must be less than 0 volts so that the device remains in a conducting state even at a gate bias condition of 0 volts or greater, V _GS ≥ 0. While a JFET's threshold voltage is referred to as its "pinch-off" voltage, or _Vpn , an N-channel JFET is also "on" with a 0 volt gate drive. N-channel depletion-mode devices and JFETs can only be turned off by biasing their gates to a negative potential. Conversely, a positive gate bias increases the drain bias of an N-channel device. However, the maximum gate drive of an N-channel JFET is limited to the forward bias voltage of the gate-to-source PN diode. P-channel JFETs also operate with a 0 volt gate drive, but need to be turned off with a positive gate drive, ie, the gate is biased to a higher potential than the source.

FIG. 4 schematically shows a cross-section of an isolated P-channel JFET 100 . P-channel JFET 100 includes P+ drain region 107, P-type channel region 111, N-type top gate including N+ region 106 and optional N-type region 108, bottom gate including N-type bottom isolation region 102, and P+ source polar region 105 . The length L _G of the N-type gate is preferably 1 μm to 20 μm, and is defined by the longer length of the top gate-N+ region 106 or the N-type region 108 .

The JFET 100 is vertically isolated from the P-type substrate 101 by the bottom isolation region 102, and is laterally isolated from the P-type substrate 101 by the filled trench 104. Bottom isolation region 102 serves as the bottom gate of JFET 100. Electrical contact to the surface of the substrate 101 is provided by a conductive material 112 filling the center of the trench 104 . Insulating material 113 laterally surrounds conductive material 112 to insulate conductive material 112 from substrate 101 and P-channel region 111 . The bottom gate (bottom isolation region 102) is electrically biased to potential "BG", and this bottom gate bias BG can be changed in proportion to the top gate (N+ region and N-type region 108) potential "TG", or BG can be is set to a fixed potential.

The pinch-off voltage of the JFET 100 is determined by the doping concentration of the channel region 111 and the vertical dimension of the channel region 111 between the NB region 108 and the bottom isolation region 102 . In one embodiment, the doping concentration of the region 111 is substantially the same as the doping concentration of the substrate 101 . In another embodiment, the doping concentration of the region 111 is increased by implanting additional dopants to adjust the pinch-off voltage of the JFET 100.

The shallow trench 110 can be disposed around the N-type region 108 to isolate the N-type region 108 from the source 105 and the drain 107 . In a preferred embodiment, trench 110 is shallower and narrower than trench 104 because trench 110 should not contact bottom isolation region 102 . Preferably, the trench 107 is completely filled with a dielectric material.

FIG. 5 schematically shows a cross-section of an isolated N-channel JFET 200. JFET 200 includes N+ drain region 203, N-type channel region 204, P-type top gate, bottom gate and P+ source region 209, wherein P-type top gate includes P+ region 205 and optional P-type region 206, bottom gate An isolated P-type pocket 207 and an optional deep implanted P-type region 208 are included. The bottom gate is electrically biased to the potential "BG" through the P-type well 210 and the P+ bottom gate contact region 211 . The bottom gate bias BG may be changed in proportion to the potential "TG" of the top gate, or BG may be set to a fixed potential. The pinch-off voltage of JFET 200 is determined by the doping concentration and thickness of N-channel region 204.

The JFET 200 is vertically isolated from the P-type substrate 201 by the N-type bottom isolation region 202, and is laterally isolated from the P-type substrate 201 by filling the trench 214. Electrical contact to the substrate surface is provided by conductive material 212 filling a central portion of trench 214 . Insulating material 213 laterally surrounds conductive material 212 to insulate it from substrate 201 and P-type regions 210 , 208 , and 207 .

A shallow trench 210 may be disposed around the P-type region 206 to isolate the top gate 206 from the source region 209 and the drain region 203 . In addition, shallow trenches 215 may be used to laterally isolate the P+ bottom gate contact region 211 from the channel region 204 , source region 209 and drain region 203 . In a preferred embodiment, trenches 210 and 215 are shallower and narrower than trench 214 because trenches 210 and 215 should not contact bottom isolation region 202 . Preferably, trenches 210 and 215 are completely filled with a dielectric material.

In another embodiment, bottom isolation region 202 may be removed such that the bottom gate of N-channel JFET 200 includes P-type substrate 201 and/or optional deep P-type region 208.

FIG. 6 schematically shows a cross-section of an N-channel depletion MOSFET 600 . MOSFET 600 is constructed similar to isolated N-channel lateral DMOS transistor 400 shown in FIG. 1 , except that there is no well equivalent to P-type well 465 in isolation pocket region 664 . There is no P-type well in the isolation pocket region 664, and the threshold voltage of the MOSFET 600 is set by the thickness of the gate oxide layer 672 and the doping concentration of the isolation P-type pocket 664, which is substantially equal to the background doping concentration of the substrate 661. This threshold voltage can vary from approximately -0.3V to +0.3V. Even when the threshold voltage is slightly positive, MOSFET 600 can still conduct enough current at V _GS =0 to be used in the start-up circuit.

The snapback effect of a depletion-mode N-channel MOSFET is similar to that of an enhancement-mode MOSFET. The structures that prevent snapback in LDMOS 300 shown in FIG. 2 can be applied to depletion mode devices in any combination.

The depletion mode MOSFET 600 of FIG. 6 includes an N+ drain region 668B with an N-type LDD drift region 669 between the gate 674 and the drain region 668B. Gate 674 is located over gate dielectric layer 672 . LDD region 678 extends from drain region 668B to fill trench 663 . Lightly doped source (LDS) regions 671, as an artifact of the CMOS process, exist under sidewall spacers 673A. N+ source regions 668A are self-aligned with sidewall spacers 673A.

The deep P-type region 675 is disposed under at least part of the gate 674 and may extend laterally beyond the gate 674 to partially overlap the LDD drift region 669 to reduce impact ionization and suppress snapback. Deep P-type region 675 is electrically connected to the surface of substrate 661 through P+ body contact region 667 .

The concentration of the P-type pocket 664 in the channel region 676 under the gate 674 is substantially the same as that of the P-type substrate 661 . In a preferred embodiment, the upper portion of DP region 675 is deep enough to avoid doping of channel region 676, thereby minimizing the threshold voltage of MOSFET 600. In other embodiments, the doping and depth of the deep P-type region 675 can be adjusted to allow its doping profile to complement the doping in the channel region 676 to increase the threshold voltage to a desired value.

The depletion MOSFET in FIG. 6 and the P-type substrate 661 are vertically isolated by the N-type bottom isolation region 602 and laterally separated by the filled trench 663 surrounding the isolation pocket 664 . Electrical contact from the surface of the substrate 661 to the bottom isolation region 662 is provided by the conductive material 680 filling the central portion of the trench 663 . Insulating material 681 laterally surrounds conductive material 680 to insulate the conductive material from substrate 661 and isolation pocket 664 .

Other embodiments of depletion-mode MOSFETs can be implemented similarly to LDMOS 300 of FIG. 2 , but without the P-body region 343, so that the threshold voltage is lower and set by the doping of the isolated pocket 341B, and possibly by the deep P-type region The doping of the upper part of 365 is determined.

isolated diode

In many power applications, for example, an isolated high voltage rectifier diode is desired to recirculate the inductor current during the break-before-make interval when switching the converter.

Figure 7 shows an embodiment of an isolated diode 700 comprising: an N-type buried region 702 serving as the cathode of the diode 700; and one or more P+ contact regions 707 surrounding the isolated P-type Inside region 706 , serves as the anode of diode 700 . Filled trench 705 laterally surrounds diode 700 , which provides lateral isolation, while N-type buried region 702 provides vertical isolation of diode 700 from P-type substrate 701 . Electrical contact from the surface of the substrate 701 to the N-type buried region 702 is provided by a conductive material 712 filling the central portion of the trench 705 . The insulating material 713 laterally surrounds the conductive material 712 to insulate the conductive material from the substrate 701 and the P-type region 706 . A dielectric layer 715 is formed on the surface of substrate 701 and patterned to form openings for anode contacts 716 and cathode contacts 717 .

An additional filled trench 708 may be included to divide the diode into smaller P-type regions and provide a lower resistance contact to buried region 702 . In a preferred embodiment, the isolated P-type region 706 may have substantially the same doping concentration as the P-type substrate 701 . This provides the lowest possible doping at the cathode-anode junction, while allowing the highest breakdown voltage BV. Alternatively, an additional P-type well implant can be introduced to increase the doping concentration in region 706, which provides reduced impedance in the anode region and provides the ability to tune BV to lower values.

In one embodiment, the additional P-type well 706 has a non-monotonic doping profile comprising at least an upper portion 706A and a lower portion 706B, and is preferably formed using boron chain implants of different energies and doses. In one embodiment, the lower portion 706B has a higher doping concentration than the upper portion 706A.

In power integrated circuits, it is often necessary to form a Zener clamp, ie, a P-N diode intended to operate normally in reverse bias, and often in an avalanche breakdown mode, to clamp the circuit voltage to a maximum value. To provide proper protection, the breakdown voltage of the Zener diode must be well controlled between 6V and 20V, which requires a P-N junction with a relatively high doping concentration to produce such a low BV. Surface junctions, such as those formed by overlapping shallow N+ and P+ regions, cannot be made reliable Zener diode clamps because their cross-sectional area is too small and avalanche breakdown occurs near the silicon-oxide interface. Therefore, it is preferred to utilize a buried P-N junction to form a Zener diode clamp to achieve subsurface avalanche breakdown.

FIG. 8 shows an isolated Zener diode 800 comprising a heavily doped buried N-type cathode region 802 and a heavily doped P-type anode region 803 . The P-type anode region 803 is preferably formed by high-dose, high-energy implantation. Contact from the surface of the substrate 801 to the anode region 803 is provided by a P+ contact region 805 and an optional P-well 804 . If no P-well 804 had been introduced, the doping in this region would be substantially the same as that of the substrate 801 . Electrical contact from the surface of the substrate to cathode region 802 is provided by conductive material 812 filling the central portion of trench 806 . The insulating material 813 laterally surrounds the conductive material 812 to insulate the conductive material from the substrate 801 and the P-type regions 803 and 804 . A dielectric layer 815 is formed on the surface of substrate 801 and patterned to form openings for anode contacts 816 and cathode contacts 817 .

Additional filled trenches 807 may be included to divide diode 800 into smaller anode regions 803 and provide lower resistance contacts to cathode regions 802 .

In typical operation, cathode region 802 is biased to a potential equal to or higher than that of grounded substrate 801 . The anode region 803 can be reverse biased with respect to the cathode to achieve a breakdown voltage set by doping on each side of the anode-cathode junction. This BV can be tuned by the depth and dose of the high energy implants preferably used to form the buried anode and cathode regions. For example, the buried anode region can be formed by phosphorus implantation with a dose ranging from 1E13cm ^-2 to 1E14cm ^-2 at an energy from 2000 to 3000keV, while the cathode region can be formed by a dose ranging from 1E13cm ^-2 to 1E14cm ^- 2 ^2. Formed by boron implantation with an energy range from 400 to 2000keV.

High voltage terminals of type I isolation devices

Another desirable feature in power integrated circuits is the ability to allow isolation devices to "float" to high voltages above the substrate potential. The highest voltage for a floating device or isolated pocket does not depend on what is inside the isolated pocket, but on how the pocket is terminated, ie, what features border the outside of the trench isolation sidewalls.

One approach described throughout this publication is to terminate the isolation region with a filled trench and limit the lateral extension of the bottom isolation region to the outer edge of the trench. As previously mentioned, the trenches may be completely filled with dielectric material, or the trenches may include conductive material in the center and dielectric material surrounding the conductive material laterally. Although this method is capable of supporting high voltages, it does not control the surface electric field and can undergo charging and other time-dependent surface-related phenomena.

Another approach is to surround the outside of the sidewall isolation trench or act as a sidewall isolation trench with one or more implant junctions, field relief regions, and channel stops, all including high voltage "terminations" The outer boundaries of , are shown in the series of cross-sectional views shown in Figures 9A-9D. In each figure, the P-type pocket is isolated laterally from the surrounding substrate by the filled trench and vertically by the implanted bottom isolation region. Although the filled trenches are shown as including conductive material in their centers, fully dielectric filled trenches may be used in other embodiments.

The isolated P-pockets shown in cross-section in Figures 9A-9D can contain CMOS, DMOS transistors, JFETs and depletion-mode MOSFETs, NPN and PNP bi-level transistors, Zener and rectifier diodes, or even passive components such as resistors and capacitors. Any combination of components, all of which are constructed and made in accordance with the invention. Each figure includes a "CL" centerline marking, denoting the axis of rotation, whereby the P-pocket is surrounded on all four sides by isolation grooves having an annular or closed geometry.

In each example, the DN bottom isolation region is shown extending beyond the trench by a distance L _DN , the magnitude of which can vary parametrically in length between 0 and tens of microns. When L _DN is 0, the lateral edge of the DN bottom isolation region coincides with the outer edge of the trench. The DN floor isolation regions are assumed to be electrically biased by contacting overlapping N-type wells (eg, as shown in Figure 1) or by filling the trench with conductive material. The outer edge of the termination is identified by a P+ guard ring to prevent surface inversion and serve as a channel stop. Dimensions refer to the outer edge of the trench and the inner edge of the P+ guard ring. The P+ guard ring may include an optional deep P-type DP layer beneath it to accommodate minority carriers laterally, and may also include intervening P-type wells as part of the guard ring structure.

FIG. 9A shows an edge termination structure including an N-type bottom isolation region 902 and a filled trench 904 which together isolate a P-type pocket 903 and any devices it contains from a P-type substrate 901 . Bottom isolation region 902 extends beyond trench 904 by a distance L _DN . When the bottom isolation region 902 is biased to a more positive potential than the substrate 901, a depletion region is distributed into the portion of the substrate 901 above the extension of the bottom isolation region 902, which depletion region lowers the electric field at the silicon surface. The lateral distance between the edge of the bottom isolation region 902 and the edge of the P+ guard ring 905 and the underlying buried P-type region 906 is indicated by the dimension L _SUB and ranges from 1 micron to tens of microns.

FIG. 9B shows an edge termination structure including bottom isolation region 912 and filled trench 914 , which together isolate P-type pocket 913 and any devices it contains from P-type substrate 911 . The bottom isolation region 912 extends beyond the trench 914 by a length L _DN . A deep implanted N-type drift region 917 of length L _D3 contacts the N+ region 918 . The drift region 917 may be biased to the same potential as the bottom isolation region 912, or may be biased to a fixed potential. The outer edge of the drift region 917 is separated from the P+ guard ring 915 and the underlying deep P-type region 916 by a distance L _SUB .

The role of the drift region 917 is to suppress the surface electric field by exhibiting a two-dimensional depletion diffusion effect. Assuming that the drift region 917 has a sufficiently low integrated charge Q _D , typically in the range from 1×10 ¹² cm ⁻² to 5×10 ¹² cm ⁻² , increasing the charge applied to the formed by the drift region 917 and the P-type substrate 911 The voltage of the PN junction causes depletion to diffuse into the drift region 917 and eventually deplete the drift region 917 completely. In this case, the drift region 917 and the intrinsic material behave similarly in a PIN diode, while the surface electric field drops substantially according to the well-known REFURF principle of a two-dimensional inductively induced PIN junction. Furthermore, the vertical overlap of drift region 917 over bottom isolation region 912 enhances the depletion of p-type substrate 911 in the intervening region between regions 917 and 912, further weakening the surface electric field within the termination.

FIG. 9C shows an edge termination structure including bottom isolation region 922 and filled trench 924 , which together isolate P-type pocket 923 and any devices it contains from P-type substrate 921 . Bottom isolation region 922 extends beyond trench 924 by a distance L _DN and is spaced apart from trench 927 by a distance L _SUB . In this embodiment, the gap between bottom isolation region 922 and trench 927, i.e., a gap of dimension L _SUB , is controlled within the surface area between trenches 924 and 927, i.e., the region identified as 928 The potential of the P-type substrate 921 . When the gap between the bottom isolation region 922 and the trench 927 becomes fully depleted, the potential of the P-type region 928 becomes floating. A P+ guard ring 925 surrounds the device and may include an underlying deep P-type region 926 .

FIG. 9D shows an edge termination structure including bottom isolation region 932 and filled trench 934 which together isolate P-type pocket 933 and any devices it contains from P-type substrate 931 . Bottom isolation region 932 extends beyond trench 934 . Deeply implanted N-type drift region 937 contacts N+ region 938 . The drift region 937 may be biased to the same potential as the bottom isolation region 932, or may be biased to a fixed potential. Within the drift region 937, one or more filled trenches 939 are formed. Each trench 939 reduces the local doping concentration in the drift region 937, which allows adjacent portions of the drift region 937 to be more easily depleted, thereby further weakening the local electric field. In a preferred embodiment, trench 939 is narrower and shallower than trench 934 and is completely filled with a dielectric material. In one embodiment, the device is designed such that the ratio of the surface area of trench 939 to the surface area of drift region 937 increases with increasing lateral distance from trench 934 . This allows the part of the drift region 937 farthest from the isolation pocket 933 to be more easily depleted than the part closer to the isolation pocket 933, providing a similar effect to a graded junction termination, which is essential for minimizing support given The lateral distance required for the BV to be effective. The outer edge of the drift region 937 is separated from the P+ guard ring 935 and the underlying deep P-type region 936 by a distance L _SUB .

The embodiments described here are intended to be illustrative and not limiting. Many alternative embodiments within the broad scope of the invention will be apparent to those skilled in the art from the description herein.

Claims (8)

1. An isolated diode formed in a semiconductor substrate of a first conductivity type, said substrate not comprising an epitaxial layer, said isolated diode comprising: a bottom isolation region of a second conductivity type opposite to the first conductivity type, buried in the substrate; a trench extending from the surface of the substrate at least to the bottom isolation region, the trench having a central portion filled with a conductive material and a dielectric material lining the walls of the trench, the conductive material providing a electrical contact of the bottom isolation region to the surface of the substrate, and the trench and the bottom isolation region together form an isolation pocket for the substrate; and An anode region is of the first conductivity type, and in the isolation pocket, the anode region extends from the surface of the substrate to the bottom isolation region. 2. The isolated diode of claim 1, further comprising: a dielectric layer over the surface of the substrate, the dielectric layer having a first opening over the anode region and a second opening over the conductive material; an anodic contact is in the first opening and contacts the anodic region; and A cathode contact is in the second opening and contacts the conductive material. 3. The isolated diode of claim 1, wherein said anode region includes a shallow portion adjacent to the surface of said substrate and a deep portion, said deep portion being located below said shallow portion, said shallow portion The deep portion has a first doping concentration, and the deep portion has a second doping concentration, the second doping concentration being higher than the first doping concentration. 4. An isolation structure formed in a semiconductor substrate of the first conductivity type, the substrate does not include an epitaxial layer, the isolation structure comprising: a bottom isolation region of a second conductivity type opposite to the first conductivity type, buried in the substrate; A first trench extending from the surface of the substrate at least to the bottom isolation region, the first trench comprising a dielectric material, the first trench and the bottom isolation region together forming a bottom isolation region of the substrate isolation bag; a guard ring of the first conductivity type, outside the isolation pocket and at the surface of the substrate, the guard ring has a doping concentration higher than that of the substrate, Wherein the bottom isolation region extends beyond the outer edge of the first trench by a predetermined distance in a direction toward the guard ring. 5. The isolation structure of claim 4, comprising a buried region of the first conductivity type under the guard ring, the buried region having a doping concentration higher than that of the substrate. 6. The isolation structure of claim 4 , comprising a drift region of the second conductivity type adjacent to the surface of the substrate and the first trench outside the isolation pocket, the drift region being connected to the The guard rings are spaced apart. 7. The isolation structure of claim 6, further comprising a second trench comprising a dielectric material and extending from the surface of the substrate into the drift region, the second trench The bottom is located in the drift region. 8. The isolation structure of claim 4, further comprising a second trench extending from the surface of the substrate, the second trench being located between the first trench and the guard ring, and The lateral edges of the bottom isolation regions are spaced apart.