CN102868663B - Sampling clock synchronization method and system in multi-carrier digital information transmission system - Google Patents

Abstract

The embodiment of the invention provides a sampling clock synchronization method and a system in a multi-carrier digital information transmission system. The method comprises: receiving multi-carrier digital signals through channels; performing relevance on signal frames in the multi-carrier digital signals by using local frames to obtain primary peak value positions and each peak value position; calculating displacement of each peak value position of a current frame relative to the primary peak value position of a first frame or a second frame before the current frame; calculating the sum of the peak value displacement, performing alternative and summation on displacement of each peak value position of each frame to determine the minimum sum of absolute values; and obtaining sampling clock deviation according to the minimum sum, and achieving sampling clock synchronization according to the sampling clock deviation. The scheme of the embodiment of the sampling clock synchronization method and the system in the multi-carrier digital information transmission system obtains the sampling clock deviation through calculation of the minimum sum of peak value displacement of a plurality of continuous frames, thereby achieving sampling clock synchronization, facilitating improvement of phase rotation of receiving frame data, and reducing interference among component channels.

Description

Sampling clock synchronous method and system in the multi-carrier digital information transmission system

Technical field

The present invention relates to digital information transmission field, particularly sampling clock synchronous method and system in a kind of multi-carrier digital information transmission system.

Background technology

Fig. 1 is multi-carrier digital information transmission system schematic diagram.As can be seen from Figure 1, X _{i, k}for input, Y _{i, k}for exporting.At transmitter side, X _{i, k}through inverse FFT IFFT, add protection interval after enter channel and transmit, at receiver side, protection interval is removed to the data received, carry out fast Fourier transform FFT after obtain Y _{i, k}.Channel in Fig. 1 can introduce sampling clock deviation.The odjective cause producing sampling clock deviation is because the crystal oscillator as sampling clock benchmark that transmitter side and receiver side adopt is not often same crystal oscillator, there is fabrication tolerance.X _{i, k}with Y _{i, k}between pass be:

$Y_{i,k}=X_{i,k}{H}_{i,k}{e}^{j\frac{2\mathrm{\π}}{N}k[n_{\mathrm{out}}(1+\mathrm{\ζ})+\mathrm{\ζ}({\mathrm{iN}}_{\mathrm{OFDM}}+N_g)]}.$

$e^{j\frac{2\mathrm{\π}}{N}\mathrm{\ϵ}({\mathrm{iN}}_{\mathrm{OFDM}}+N_g)}\·e^{j\frac{2\mathrm{\π}}{N}\mathrm{\ϵ}(1+\mathrm{\ζ})n_{\mathrm{out}}}\·e^{j\frac{2\mathrm{\π}}{N}(N-1-n_{\mathrm{out}})[\mathrm{k\ζ}+(1+\mathrm{\ζ})\mathrm{\ϵ}]}\·e^{j{\stackrel{\‾}{\mathrm{\Φ}}}_i}---\left(1\right)$

$\·\frac{\sin \left[\frac{\mathrm{\π}}{N}(N-n_{\mathrm{out}})(\mathrm{k\ζ}+\mathrm{\ϵ}(1+\mathrm{\ζ}))\right]}{N\sin \frac{\mathrm{\π}(\mathrm{k\ζ}+\mathrm{\ϵ}(1+\mathrm{\ζ}))}{N}}+N_{i,k;\mathrm{ICI}}+N_{i,k;\mathrm{noise}}$

Design parameter implication is as follows:

Y _{i, k}: i-th OFDM symbol kth sample value after FFT conversion;

X _{i, k}: a kth sample value in i-th OFDM symbol before transmitting terminal IFFT;

H _{i, k}: i-th OFDM symbol kth transmission coefficient between data sending terminal and receiving terminal;

N _out: deviation of windowing;

ζ: normalization sampling error, can be expressed as: ζ=(T _rX-T _tX)/T _tX, wherein T _rXfor the receiver sampling period, T _tXfor the transmitter sampling period;

ε: normalization carrier wave frequency deviation, the deviation between actual carrier is f _Δε, wherein f _Δit is subcarrier spacing;

the mean value of the phase noise of i-th OFDM symbol;

, wherein it is the phase noise of the i-th subcarrier;

N:IFFT length;

N _g: each OFDM symbol protection gap length;

N _oFDM: each OFDM symbol length;

N _{i, k; ICI}: interchannel interference;

N _{i, k; Noise}: noise jamming.

According to aforementioned formula (1), knownly work as n _out, when ε is 0, Y _{i, k}be expressed as follows:

$Y_{i,k}=X_{i,k}{H}_{i,k}{e}^{j\frac{2\mathrm{\π}}{N}\mathrm{k\ζ}({\mathrm{iN}}_{\mathrm{OFDM}}+N_g)}+N_{i,k;\mathrm{ICI}}+N_{i,k;\mathrm{noise}}---\left(2\right).$

As can be seen from above-mentioned formula (2): the output impact of described sampling clock deviation on system is as follows:

1) cause receiving data phase to rotate;

2) introduce between subchannel and disturb.

When noul, when one or more in ε are not 0, known according to aforementioned formula (1) equally, described Y _{i, k}in comprise the full content of formula (2) right-hand member equally, thus described reception data phase rotates and between subchannel, interference is same exists.

Summary of the invention

For the problems referred to above, the object of the present invention is to provide sampling clock synchronous method and system in a kind of multi-carrier digital information transmission system.

In first aspect, the embodiment of the present invention provides sampling clock synchronous method in a kind of multi-carrier digital information transmission system, and described method comprises: receive multiple carrier digital signal by channel; Utilize local frame to be correlated with to the signal frame in this multiple carrier digital signal, obtain pre-selected peak position and each peak; The displacement of the first frame before the relatively described present frame of each peak of calculating present frame or the pre-selected peak position of the second frame; Calculate described peak displacement sum, each peak of each frame be displaced through and select one and sue for peace, determine absolute value minimum and value; Minimum obtain sampling clock deviation with value according to described, and it is synchronous to realize sampling clock according to this sampling clock deviation.

In second aspect, the embodiment of the present invention provides sampling clock synchro system in a kind of multi-carrier digital information transmission system, and described system comprises: multiple carrier digital signal receiver module, for receiving multiple carrier digital signal by channel; Peak computing module, for utilizing local frame to be correlated with to the signal frame in this multiple carrier digital signal, obtains pre-selected peak position and each peak; Peak displacement computing module, the displacement of the first frame before the relatively described present frame of each peak for calculating present frame or the pre-selected peak position of the second frame; Displacement sum absolute value minimum value computing module, for calculating described peak displacement sum, being displaced through each peak of each frame and selecting one and sue for peace, determine absolute value minimum and value; Sampling clock synchronization module, for minimum obtaining sampling clock deviation with value according to described, and it is synchronous to realize sampling clock according to this sampling clock deviation.

The scheme of the embodiment of the present invention, the minimum value by peak displacement sum absolute value obtains sampling clock deviation, thus it is synchronous to realize sampling clock, is conducive to improving the phase rotating of frames received certificate, reduces to disturb between subchannel.

Accompanying drawing explanation

Below in conjunction with accompanying drawing, specific embodiment of the invention scheme is described in further detail, in accompanying drawing:

Fig. 1 is multi-carrier digital information transmission system schematic diagram;

Fig. 2 is the multi-frame structure of China Digital TV ground standard;

Fig. 3 is 8 rank m sequence generating structure schematic diagrames of the embodiment of the present invention;

Fig. 4 is a kind of sampling clock synchronous method flow chart in the multi-carrier digital information transmission system of the embodiment of the present invention;

Fig. 5 is a kind of sampling clock synchro system schematic diagram in the multi-carrier digital information transmission system of the embodiment of the present invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making other embodiments all obtained under creative work prerequisite, belong to the scope of protection of the invention.

The embodiment of the present invention can be applied to field of digital television transmission, also can be applied to moving communicating field or other field, be described below for field of digital television transmission, is necessary the frame structure first introducing field of digital television transmission for this reason.

Fig. 2 is the multi-frame structure of China Digital TV ground standard.As shown in Figure 2, China Digital TV ground standard (GB 20600-2006) data frame structure is a kind of four-layer structure.Signal frame is the elementary cell of system data frame structure, and a signal frame is made up of frame head and frame two parts time-domain signal.Frame head is identical with the baseband signalling rate (7.56Msps) of frame signal.

Frame head part is by PN Sequence composition, and its length has three kinds of options.The 4QAM modulation that header signal adopts I road identical with Q road.

Body section comprises the system information of 36 symbols and the data of 3744 symbols, totally 3780 symbols.Frame length is 500 μ s (3780 × 1/7.56 μ s), remains unchanged.

As shown in table 1, for adapting to different application, define three kinds of optional frame head modes and corresponding signal frame structure.For signal frame structure a), every 225 signal frames form a superframe (225 × 4200 × 1/7.56 μ s=125ms), because header signal length is 420 symbols, therefore the type frame can be called PN420 frame; For signal frame structure b), every 216 signal frames form a superframe (216 × 4375 × 1/7.56 μ s=125ms), because header signal length is 595 symbols, therefore the type frame can be called PN595 frame; For signal frame structure c), every 200 signal frames form a superframe (200 × 4725 × 1/7.56 μ s=125ms), because header signal length is 945 symbols, therefore the type frame can be called PN945 frame.Visible, the superframe length corresponding to three kinds of frame head modes all remains unchanged.

Table 1

Be described in detail as follows for frame head mode 1:

The PN sequence definition that frame head mode 1 adopts is 8 rank m sequences of cyclic extensions, can by a LFSR (Linear Feedback Shifting Register, linear feedback shift register) realize, be the binary character of non-return-to-zero through " 0 " to+1 value and " 1 " to the mapping transformation of-1 value.

Length is the header signal (PN420) of 420 symbols, synchronously form by after a preamble, a PN255 sequence and one, preamble and the rear cyclic extensions being synchronously defined as PN255 sequence, wherein preamble length is 82 symbols, rear synchronization length is 83 symbols, as shown in table 2.

Table 2

Preamble 82 symbols

PN255

Synchronous 83 symbols afterwards

The initial condition of LFSR determines the phase place of produced PN sequence.225 signal frames are had in a superframe.In each superframe, the frame head of each signal frame adopts the PN signal of out of phase as signal frame identifier.

The generator polynomial producing the LFSR of sequence PN255 is defined as:

G ₂₅₅(x)＝1+x+x ⁵+x ⁶+x ⁸

Fig. 3 is 8 rank m sequence generating structure schematic diagrames.PN420 sequence just can produce with the LFSR shown in Fig. 3.

The average power of header signal is 2 times of the average power of frame signal.

Specify in agreement: when not requiring instruction frame number, above-mentioned PN sequence, without the need to realizing phase place change, uses the PN initial phase of sequence number 0.

Detailed description about frame head mode 2, frame head mode 3 is similar to the above-mentioned detailed description for frame head mode 1, does not repeat them here.

Fig. 4 is a kind of sampling clock synchronous method flow chart in the multi-carrier digital information transmission system of the embodiment of the present invention, and it comprises following steps:

Step 400, receives multiple carrier digital signal by channel;

Step 402, calculates pre-selected peak position and each peak;

Particularly, by relevant to local sequence for the sequence received, namely utilize local frame to be correlated with to the signal frame in this multiple carrier digital signal, obtain pre-selected peak position I _{i, peak}with each peak I _{i, max1}, I _{i, max2}, I _{i, max3}...; The sequence that described local frame sequence can adopt Fig. 2 to generate, does not repeat them here.

If every frame frame length is N, i-th corresponding signal frame correlation is p _{i, 0}, p _{i, 1}, p _{i, 2}... p _{i, N-1}.

Above-mentioned pre-selected peak p _{i, peak}and pre-selected peak position I _{i, peak}be defined as follows:

p _i，peak＝p _i，0；

I _i，peak＝0；

for(j＝1；j＜N；j++)

{

if(p _i，j＞＝A·p _i，j-1)

{

p _i，peak＝p _i，j；

I _i，peak＝j；

}

}

Wherein A is the threshold coefficient of setting, and its preferred scope is (1,3), also can select the value of other scopes as required, not limit at this.

I _{i, max1}, I _{i, max2}, I _{i, max3}... be respectively the peak-peak position of i-th signal frame, second largest peak, the third-largest peak ....

Step 404, calculates each peak displacement;

Particularly, the displacement of the relative pre-selected peak position of frame before of each peak of present frame is calculated.

Calculate each peak of present frame and the displacement S of previous frame pre-selected peak position _{i, max1}, S _{i, max2}, S _{i, max3}....Wherein:

S _i，max1＝I _i，max1-I _i-1，peak

For second largest peak value and the process of previous frame pre-selected peak position displacement as follows:

if(|I _i，max1-I _i，max2｜)＝＝1

I′ _i，max2＝I _i，max1

else

I′ _i，max2＝I _i，max215

S _i，max2＝I′ _i，max2-I _i-1，peak

In like manner process as follows for the third-largest peak value and previous frame pre-selected peak position:

if(|I _i，max3-I _i，max1|)＝＝1

I′ _i，max3＝I _i，max1

elseif(|I _i，max3-I _i，max2｜)＝＝1

I′ _i，max3＝I _i，max2

else

I′ _i，max3＝I _i，max3

S _i，max3＝I′ _i，max3-I _i-1，peak

In like manner can do similar process to other peaks such as such as the fourth-largest peak values.

Step 406 calculate peak displacement sum and determine absolute value minimum and value;

Particularly, for two continuous frames, calculate S _{i, max1}+ S _{i-1, max1}; S _{i, max1}+ S _{i-1, max2}; S _{i, max1}+ S _{i-1, max3}; S _{i, max2}+ S _{i-1, max1}; S _{i, max2}+ S _{i-1, max2}; S _{i, max2}+ S _{i-1, max3}; S _{i, max3}+ S _{i-1, max1}; S _{i, max3}+ S _{i-1, max2}; S _{i, max3}+ S _{i-1, max3}; Wherein i=0,1,2 ..., N-1.Then the shift value p that described displacement sum absolute value minimum value is corresponding is obtained.

Alternatively, the also difference sum of the peak of desirable continuous print odd number (or even number) frame, simplified illustration, gets the pre-selected peak position of continuous three frames, I _{i-1, peak}, I _{i, peak}, I _{i+1, peak}:

Two continuous frames displacement sum: (I _{i, peak}-I _{i-1, peak})+(I _{i+1, peak}-I _{i, peak})=I _{i+1, peak}-I _{i-1, peak}do not limit at this.

Step 408, according to described absolute value minimum obtain sampling clock deviation with value, and it is synchronous to realize sampling clock according to this sampling clock deviation.

Particularly, sampling clock deviation ζ is exported according to minimum value p _i, and it is synchronous to realize sampling clock according to this sampling clock deviation.ζ _i=ζ _i-1+ qsign (p), wherein q is attenuation coefficient, and sign () is sign function.ζ _ithe current sampling clock deviation that will calculate, ζ _i-1ζ _ilast sampling clock deviation, the initial value of described sampling clock deviation can be set as 0, or is set as a suitable empirical value as required, does not limit at this.

Preferably, at the described sampling clock deviation ζ of calculating _itime, some preconditions can also be set: as:

if((|p|＞＝1)&(|p|＜＝r))

ζ _i＝ζ _i-1+q·sign(p)5

Wherein r is adjustable parameter, and its value depends on the sampling frequency offset scope of tolerance.Such as, if the error of the deviation of PN945 tolerable 350ppm or PN595 tolerable 400ppm, then r=4.

Describedly realize sampling clock according to this sampling clock deviation and be synchronously specially: allow sampling clock=(1+ ζ _i) the current sampling clock of *.

For step 406, describe in more detail as follows:

For PN420 frame data and two continuous frames, the distribution map of its desirable correlation peak displacement can be analyzed, as shown in table 3:

Table 3

Under ideal conditions, continuous two correlation peak displacement sums are 1 ,-1,0,

When sample clock frequency is excessive, continuous two correlation peak displacement sums can be less than-1;

With should sample clock frequency too small time, continuous two peak displacement sums can be greater than 1;

Above-mentioned algorithm is equally applicable to the data of PN595 frame and PN945 frame.

In actual channel, due to multipath and Doppler, footpath corresponding to front and back maximum correlation peaks may not be same footpath, be now-1,1 based on continuous two correlation peak displacement sums, or the conclusion of 0 is just false.

For this reason, the footpath corresponding for maximum correlation peaks before and after guarantee is same footpath, and for each frame, we calculate pre-selected peak position and each peak I _{i, peak}, I _{i, max1}, I _{i, max2}, I _{i, max3}..., because change quiet in actual channel can not be very fast, the S therefore obtained _{i, max1}, S _{i, max2}, S _{i, max3}... in a value must be had to correspond to the correlation peak location in same footpath.

For I _{i, max1}, I _{i, max2}, I _{i, max3}..., if there are two adjacent positions, we should get the position of the correspondence of peak-peak or minimum peak simultaneously, otherwise can introduce interference.The position of described peak-peak or minimum peak changes according to the change of sampling deviation.

Assuming that the correlation peak shift value of present frame is: S _{i, max1}, S _{i, max2}, S _{i, max3}... a value must be had to correspond to the correlation peak location in same footpath, assuming that it is S ' _{i, max}.

The correlation peak shift value of previous frame is: S _{i-1, max1}, S _{i-1, max2}, S _{i-1, max3}... a value must be had to correspond to the correlation peak location in same footpath, assuming that it is S ' _{i-1, max}.

Under ideal conditions, continuous two correlation peak displacement sum S ' _{i, max}+ S ' _{i-1, max}be 1 ,-1,0, when sample clock frequency is excessive, described continuous two correlation peak displacement sums can be less than-1; With should sample clock frequency too small time, described continuous two peak displacement sums can be greater than 1; Assuming that peak number is M, then the calculation process of the peak displacement sum p that absolute value is minimum is as follows:

p＝|S _i，max1+S _i-1，max1｜；

for(m＝1；m＜＝M；m++)

for(n＝1；n＜＝M；n++)

{

if(｜S _i，maxm+S _i-1，maxn｜)＜p

p＝｜S _i，maxm+S _i-1，maxn｜；

}

Obtain sampling clock deviation by the minimum value of peak displacement sum absolute value in the sampling clock synchronous method of the embodiment of the present invention, thus it is synchronous to realize sampling clock, is conducive to improving the phase rotating of frames received certificate, reduces to disturb between subchannel.

Fig. 5 is a kind of sampling clock synchro system schematic diagram in the multi-carrier digital information transmission system of the embodiment of the present invention, and described sampling clock synchro system comprises as lower module:

Multiple carrier digital signal receiver module 500, for receiving multiple carrier digital signal by channel;

Peak computing module 502, for utilizing local frame to be correlated with to the signal frame in this multiple carrier digital signal, obtains pre-selected peak position and each peak;

Particularly, by relevant to local sequence for the sequence received, obtain pre-selected peak position and each peak I _{i, peak}, I _{i, max1}, I _{i, max2}, I _{i, max3}...; The sequence that described local sequence can adopt Fig. 2 to generate, does not repeat them here.

If every frame frame length is N, i-th corresponding signal frame correlation is p _{i, 0}, p _{i, 1}, p _{i, 2}... p _{i, N-1}.

Above-mentioned pre-selected peak p _{i, peak}and pre-selected peak position I _{i, peak}be defined as follows:

p _i，peak＝p _i，0；

I _i，peak＝0；

for(j＝1；j＜N；j++)

{

if(p _i，j＞＝A·p _i，j-1)

{

p _i，peak＝p _i，j；

I _i，peak＝j；

}

}

Wherein A is the threshold coefficient of setting, and its preferred scope is (1,3), also can select the value of other scopes as required, not limit at this.

I _{i, max1}, I _{i, max2}, I _{i, max3}... be respectively the peak-peak position of i-th signal frame, second largest peak, the third-largest peak ....

Peak displacement computing module 504, the displacement of the pre-selected peak position of frame before each peak for calculating present frame is relative;

Particularly, each peak of present frame and the displacement S of previous frame pre-selected peak position is calculated _{i, max1}, S _{i, max2}, S _{i, max3}....Wherein:

S _i，max1＝I _i，max1-I _i-1，peak

For second largest peak value and the process of previous frame pre-selected peak position displacement as follows:

if(|I _i，max1-I _i，max2|)＝＝1

I′ _i，max2＝I _i，max1

else

I′ _i，max2＝I _i，max2

S _i，max2＝I′ _i，max2-I _i-1，peak

In like manner process as follows for the third-largest peak value and previous frame pre-selected peak position:

if(|I _i，max3-I _i，max1|)＝＝1

I′ _i，max3＝I _i，max1

elseif(|I _i，max3-I _i，max2｜)＝＝1

I′ _i，max3＝I _i，max2

else

I′ _i，max3＝I _i，max3

S _i，max3＝I′ _i，max3-I _i-1，peak

In like manner can do similar process to the displacement of other peaks such as such as the fourth-largest peak value.

Displacement sum absolute value minimum value computing module 506, for calculating multiframe peak displacement sum, being displaced through each peak of each frame in described multiframe and selecting one and sue for peace, and determines minimum and value; Particularly, for two continuous frames, calculate S _{i, max1}+ S _{i-1, max1}; S _{i, max1}+ S _{i-1, max2}; S _{i, max1}+ S _{i-1, max3}; S _{i, max2}+ S _{i-1, max1}; S _{i, max2}+ S _{i-1, max2}; S _{i, max2}+ S _{i-1, max3}; S _{i, max3}+ S _{i-1, max1}; S _{i, max3}+ S _{i-1, max2}; S _{i, max3}+ S _{i-1, max3}; Wherein i=0,1,2 ..., N-1.Then the p value of the minimum correspondence of described displacement sum absolute value is obtained.

Alternatively, also can carry out the peak displacement sum of continuous three frames or more frame, not limit at this.

Sampling clock synchronization module 508, for minimum obtaining sampling clock deviation with value according to described, and it is synchronous to realize sampling clock according to this sampling clock deviation.

Particularly, ζ _i=ζ _i-1+ qsign (p), wherein q is attenuation coefficient, and it determines the tracking convergence rate of sampling clock deviation; Sign () is sign function.ζ _ithe current sampling clock deviation that will calculate, ζ _i-1ζ _ilast sampling clock deviation, the initial value of described sampling clock deviation can be set as 0, or according to being set as a suitable empirical value, does not limit at this.

Preferably, at the described sampling clock deviation ζ of calculating _itime, some preconditions can also be set: as:

if((|p|＞＝1)&(|p|＜＝r))

ζ _i＝ζ _i-1+q·sign(p)

Wherein r is adjustable parameter, and its value depends on the sampling frequency offset scope of tolerance.Such as, if the error of the deviation of PN945 tolerable 350ppm or PN595 tolerable 400ppm, then r=4.

Describedly realize sampling clock according to this sampling clock deviation and be synchronously specially: allow sampling clock=(1+ ζ _i) the current sampling clock of *.

For the calculation process of above-mentioned displacement sum absolute value minimum value computing module, more detailed description can refer to the aforementioned detailed description to step 406, does not repeat them here.

Obtain sampling clock deviation by the minimum value of peak displacement sum absolute value in the sampling clock synchro system of the embodiment of the present invention, thus it is synchronous to realize sampling clock, is conducive to improving the phase rotating of frames received certificate, reduces to disturb between subchannel.

In several embodiments that the application provides, should be understood that disclosed device can realize by another way.Such as, device embodiment described above is only schematic, such as, the division of described module, be only a kind of logic function to divide, actual can have other dividing mode when realizing, such as multiple module or assembly can in conjunction with or another system can be integrated into, or some features can be ignored, or do not perform.Another point, shown or discussed coupling each other or direct-coupling or communication connection can be by some interfaces, and the indirect coupling of device or module or communication connection can be electrical, machinery or other form.The described module illustrated as separating component can or may not be physically separates, and the parts as module display can be or may not be physical module, namely can be positioned at a place, or also can be distributed on multiple mixed-media network modules mixed-media.Some or all of module wherein can be selected according to the actual needs to realize the object of the present embodiment scheme.

In addition, each functional module in each embodiment of the present invention, device can be integrated in a processing module, also can be that the independent physics of modules exists, also can two or more module integrations in a module.Above-mentioned integrated module both can adopt the form of hardware to realize, and the form of software function module also can be adopted to realize.

If described integrated module using the form of software function module realize and as independently production marketing or use time, can be stored in a computer read/write memory medium.Based on such understanding, the part that technical scheme of the present invention contributes to prior art in essence in other words or all or part of of this technical scheme can embody with the form of software product, this computer software product is stored in a storage medium, comprising some instructions in order to make a computer equipment (can be personal computer, server, or the network equipment etc.) perform all or part of step of method described in each embodiment of the present invention.And aforesaid storage medium comprises: USB flash disk, portable hard drive, read-only memory (ROM, Read-OnlyMemory), random access memory (RAM, Random Access Memory), magnetic disc or CD etc. various can be program code stored medium.

Above-described embodiment; object of the present invention, technical scheme and beneficial effect are further described; be understood that; the foregoing is only the specific embodiment of the present invention; the protection range be not intended to limit the present invention; within the spirit and principles in the present invention all, any amendment made, equivalent replacement, improvement etc., all should be included within protection scope of the present invention.

Claims (6)

1. a sampling clock synchronous method in the multi-carrier digital information transmission system, is characterized in that, described method comprises:

Multiple carrier digital signal is received by channel;

Utilize local frame to be correlated with to the signal frame in this multiple carrier digital signal, obtain pre-selected peak position and each peak;

Calculate the displacement of the pre-selected peak position of the first frame before the relatively described present frame of each peak of present frame or the second frame respectively;

Calculate described peak displacement sum, each peak of each frame be displaced through and select one and sue for peace, determine absolute value minimum and value;

According to described absolute value minimum obtain sampling clock deviation with value, and it is synchronous to realize sampling clock according to this sampling clock deviation;

Wherein, according to the computing formula obtaining sampling clock deviation with value that described absolute value is minimum be:

ζ _i=ζ _i-1+ qsign (p), wherein q is attenuation coefficient, and sign () is sign function, ζ _idescribed sampling clock deviation, ζ _i-1last sampling clock deviation, P be peak sum absolute value minimum and value;

Describedly realize sampling clock according to this sampling clock deviation and be synchronously specially: allow the sampling clock that sampling clock=(1+ sampling clock deviation) * is current.

2. method as claimed in claim 1, is characterized in that, if described each peak exists two adjacent peaks, then each peak value all gets the peak that peak amplitude is comparatively large or amplitude is less.

3. method as claimed in claim 2, it is characterized in that, described each peak is peak-peak position, second largest peak, the third-largest peak or pre-selected peak position.

4. the sampling clock synchro system in the multi-carrier digital information transmission system, is characterized in that, described sampling clock synchro system comprises:

Multiple carrier digital signal receiver module, for receiving multiple carrier digital signal by channel;

Peak computing module, for utilizing local frame to be correlated with to the signal frame in this multiple carrier digital signal, obtains pre-selected peak position and each peak;

Peak displacement computing module, the displacement of the first frame before the relatively described present frame of each peak for calculating present frame or the pre-selected peak position of the second frame;

Displacement sum absolute value minimum value computing module, for calculating described peak displacement sum, being displaced through each peak of each frame and selecting one and sue for peace, determine absolute value minimum and value;

Sampling clock synchronization module, for according to described absolute value minimum obtain sampling clock deviation with value, and it is synchronous to realize sampling clock according to this sampling clock deviation; Wherein, according to the computing formula obtaining sampling clock deviation with value that described absolute value is minimum be: ζ _i=ζ _i-1+ qsign (p), wherein q is attenuation coefficient, and sign () is sign function, ζ _idescribed sampling clock deviation, ζ _i-1last sampling clock deviation, P be peak sum absolute value minimum and value; Describedly realize sampling clock according to this sampling clock deviation and be synchronously specially: allow the sampling clock that sampling clock=(1+ sampling clock deviation) * is current.

5. sampling clock synchro system as claimed in claim 4, is characterized in that, if described each peak exists two adjacent peaks, then each peak value all gets the peak that peak amplitude is comparatively large or amplitude is less.

6. sampling clock synchro system as claimed in claim 5, it is characterized in that, described each peak is peak-peak position, second largest peak, the third-largest peak or pre-selected peak position.