CN102881333B - Shift-register circuit and chip - Google Patents

Abstract

The embodiment of the invention discloses a shift register circuit and a chip. The circuit includes: a matrix of resistive memristors and a current sensitive module; connected so that the non-inverting input terminals of the same row of resistive memristors are used as signal input ports; Connect so that the output terminal of the current sensitive module is used as a signal output port; the input terminal of the current sensitive module is connected to a low level when it is working, and when the current received by the input terminal of the current sensitive module is greater than the threshold current, the output terminal of the current sensitive module Output high level, when the current received by the input terminal of the current sensitive module is less than the threshold current, the output terminal of the current sensitive module outputs low level. In the embodiment of the present invention, while saving the area occupied by the shift register circuit, the programmable performance of the shift register circuit is realized.

Description

Shift register circuits and chips

technical field

The invention relates to the field of electronic technology, in particular to a shift register circuit and a chip.

Background technique

Shift register circuits are usually based on metal-oxide-semiconductor (MOS, Metal-Oxide-Semiconductor) tube storage devices. As the requirements for chip integration become higher and higher, the size of shift register circuits is also decreasing, but Due to the limitation of the size of the MOS transistor storage device itself, the shift register circuit in the prior art has a technology node with the smallest size.

Contents of the invention

Embodiments of the present invention provide a shift register circuit and a chip, which are used to solve the problem that the shift register circuit in the prior art has a minimum size technical node.

In order to solve the above problems, the embodiment of the present invention discloses the following technical solutions:

On the one hand, a shift register circuit is provided, including: a matrix of resistive memristors and a current sensitive module; the positive phase input terminals of the same column of resistive memristors in the square array of resistive memristors are connected , so that the positive-phase input terminal of the same row of resistance-variable memristors is used as a signal input port; The input terminal of the module is connected so that the output terminal of the current sensitive module is used as a signal output port; the input terminal of the current sensitive module is connected to a low level during operation, and the current received by the input terminal of the current sensitive module When the current is greater than the threshold current, the output end of the current sensing module outputs a high level, and when the current received by the input end of the current sensing module is less than the threshold current, the output end of the current sensing module outputs a low level.

Preferably, the resistance state of the resistive memristor includes: a high resistance resistance state and a low resistance resistance state.

Preferably, there is a resistive memristor in a low-resistance resistance state in the same row of resistive memristors in the matrix of resistive memristors; Among the resistive memristors in the column, there is a resistive memristor in a low-resistance resistance state.

Preferably, the resistive memristor includes: a unipolar resistive memristor or a bipolar resistive memristor.

Preferably, the resistive memristor includes: resistive memory (RRAM, Resistive Random Access Memory) or phase-change memory (PRAM, Phase-Change Random Access Memory) or ferroelectric memory (FRAM, ferroelectric Random Access Memory) or magnetic Memory (MRAM, Magnetic Random Access Memory).

On the one hand, a chip is provided, including: a top electrode metal strip, a bottom electrode metal strip, and a shift register circuit; the shift register circuit includes: a resistance variable memristor matrix and a current sensitive module; the resistance variable In the memristor square array, the positive-phase input ends of the same column of resistance-variable memristors are connected through the top electrode metal strip, so that the normal-phase input terminals of the same column of resistance-variable memristors are used as signal input ports; The inverting input terminal of the resistance variable memristor of the same row in the resistance variable memristor square array is connected to the input terminal of one of the current sensitive modules through the bottom electrode metal strip, so that the output of the current sensitive module The terminal is used as a signal output port; the input terminal of the current sensitive module is connected to a low level when it is working, and when the current received by the input terminal of the current sensitive module is greater than the threshold current, the output terminal of the current sensitive module outputs a high voltage level, when the current received by the input end of the current sensing module is less than the threshold current, the output end of the current sensing module outputs a low level.

Preferably, the resistance state of the resistive memristor includes: a high resistance resistance state and a low resistance resistance state.

Preferably, there is a resistive memristor in a low-resistance resistance state in the same row of resistive memristors in the matrix of resistive memristors; Among the resistive memristors in the column, there is a resistive memristor in a low-resistance resistance state.

Preferably, the resistive memristor includes: a unipolar resistive memristor or a bipolar resistive memristor.

Preferably, the resistive memristor includes: RRAM or PRAM or FRAM or MRAM.

The shift register circuit provided by the embodiment of the present invention does not completely adopt the traditional MOS transistor storage device in its circuit composition, but partially adopts a new type of storage device with a two-terminal structure, such as a resistive memristor. The variable memristor has the characteristics of good scalability, high storage density, low power consumption, fast read and write speed, strong resistance to repeated operations, and long data retention time. Therefore, while effectively saving the area occupied by the shift register circuit , realizing the programmable performance of the shift register circuit.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the accompanying drawings required in the embodiments. Obviously, the accompanying drawings in the following description are only some of the present invention. Embodiments, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without any creative effort.

Fig. 1 is the schematic diagram of the shift register circuit in one embodiment of the present invention;

Fig. 2 is the circuit principle diagram of the current sensitive module in one embodiment of the present invention;

Figure 3a is a graph showing the conductivity of a unipolar resistive memristor increasing with voltage;

Fig. 3b is a graph showing that the conductivity of a unipolar resistive memristor decreases with voltage;

Fig. 4 is a graph showing the conductivity of a bipolar resistive memristor as a function of voltage;

Fig. 5 is a schematic diagram of the corresponding resistance state setting when the shift register circuit realizes the output function of one bit left shift;

FIG. 6 is a schematic diagram of the corresponding resistance state setting when the shift register circuit implements a one-bit right-shift output function.

detailed description

The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without creative efforts fall within the protection scope of the present invention.

As shown in FIG. 1 , it is a schematic diagram of a shift register circuit in an embodiment of the present invention.

The shift register circuit may include a resistive memristor matrix 10 and a current sensing module 11 . In the resistive memristor square matrix 10, the positive phase input terminals of the same column resistance variable memristor 101 are connected, so that the positive phase input terminal of the same column resistance variable memristor 101 is used as a signal input port, and the signal input port is used For receiving low-level or high-level signals, specifically, it can be used to receive one of N-bit digital input signals (Din), N is a positive integer, and its value is at least 2, and the same The inverting input terminal of the row resistance variable memristor 101 is connected with the input terminal of a current sensitive module 11, so that the output terminal of the current sensitive module 11 is used as a signal output port, and the signal output port is used to output low level or high The level signal can be specifically used to output one of the N-bit digital output signals (Dout).

Wherein, the resistive memristor 101 is a two-terminal device. Referring to FIG. 1 , the upper end of the resistive memristor 101 is a non-inverting input end, and the lower end of the resistive memristor 101 is an inverting input end.

In the embodiment of the present invention, the input terminal of the current sensitive module 11 is connected to a low level during operation, and when the current received by the input terminal of the current sensitive module 11 is greater than the threshold current, the output terminal of the current sensitive module 11 outputs a high level, corresponding Ground, the signal output port outputs a high level, that is, a digital signal "1"; when the current received by the input terminal of the current sensitive module 11 is less than the threshold current, the output terminal of the current sensitive module 11 outputs a low level, correspondingly, the signal output The port outputs a low level, that is, a digital signal "0".

Wherein, the current sensitive module 11 can be realized in various ways, and the present invention does not specifically limit it. For example, the current signal can be amplified by an amplifier and converted into a voltage signal for output, or a mirror current source circuit can be used to mirror the current and then externally connect a load resistor. Then, the voltage signal on the load resistor is processed and output, and the method of implementing the current sensitive module 11 through the mirror current source circuit will be described in detail below.

Referring to Fig. 2, it is the circuit schematic diagram of current sensitive module 11 in one embodiment of the present invention, and this current sensitive module 11 is made up of mirror current source circuit 111, load resistance 112 and comparator 113, wherein, the input of mirror current source circuit 111 The terminal Iin is used as the input terminal of the current sensitive module 11, the output terminal of the mirror current source circuit 111 is connected to the non-inverting input terminal of the comparator 113 through the load resistor 112, the inverting input terminal of the comparator 113 is connected to the reference level Vref, and the comparator The output terminal Vout of 113 is used as the output terminal of the current sensing module 11 . The mirror current source circuit 111 is grounded, so that the input terminal of the mirror current source circuit 111 is connected to a low level during operation, that is, the input terminal of the current sensitive module 11 is connected to a low level during operation, so it is connected to the input terminal of the current sensitive module 11. The inverting input terminals of the connected resistive memristors 101 are at low level. When the shift register circuit is working, if the current received by the input terminal of the current sensing module 11 is greater than the threshold current, the current passes through the mirror current source circuit 111 and is mirrored to the output branch, which is connected to the load resistor 112, because The resistance value of the load resistor 112 is equivalent to the resistance value when the resistance variable memristor 101 is in a low-resistance resistance state, so the voltage generated on the load resistor 112 is equivalent to the high level received by the signal input port of the shift register circuit , for the convenience of description, the high level received by the signal input port when the shift register circuit is working can be called the working voltage, and the reference level Vref can be set to half of the working voltage, which can be realized by resistive voltage division. The voltage on the load resistor 112 is higher than the reference level Vref, and the comparator 113 outputs a high level, thereby realizing the function of the current sensing module 11 .

The resistive memristor 101 used in the embodiment of the present invention may have two resistance states: a high resistance state and a low resistance state. In the resistive memristor 101 of the same row in the resistive memristor matrix 10, there is a resistive memristor in a low-resistance resistance state, and the resistive memristor in the same row in the resistive memristor square matrix 10 The memristor 101 has a resistive switching memristor in a low-resistance resistance state. Before the shift register circuit works, each resistance change memristor 101 in the resistance change memristor matrix 10 can be programmed according to the function to be realized by the shift register circuit, and the above programming is about to make each resistance change memristor 101 If it is set to a low-resistance resistance state or a high-resistance resistance state, since the shift register circuit of the present invention can realize its corresponding function through programming, the shift register circuit of the present invention can be called a programmable shift register circuit.

The resistive memristor 101 has a resistive state memory function. When the voltage applied across the resistive memristor 101 is lower than the threshold voltage, the resistive state of the resistive memristor 101 remains unchanged. When the resistive memristor 101 When the voltage applied to both ends is higher than the threshold voltage, the resistance state of the resistive memristor 101 may change. It can be seen from the above that the working voltage of the resistive memristor 101 should be less than the threshold voltage; The voltage applied across the resistive memristor 101 during programming.

The usage modes of the shift register circuit of the present invention may include: programming mode and working mode. When the shift register circuit is in the programming mode, the magnitude of the programming voltage applied to the two ends of the resistive memristor 101 should exceed the threshold voltage of the resistive memristor 101. The number of resistive memristors 101 may be many, for example, when the shift register circuit has 8 signal input terminals and 8 signal output terminals, the resistive memristor matrix 10 may contain 64 resistive memristors Resistor 101, when programming each resistive memristor 101 in the resistive memristor square array 10 respectively, the efficiency is low, and most of the resistive memristors 101 in the resistive memristor square array 10 are It should be set to a high-resistance resistance state, so all the resistive memristors 101 in the resistive memristor matrix 10 can be programmed uniformly, that is, all the resistive memristors 101 are in high resistance through unified programming value resistance state, and then separately program a small number of resistive memristors 101 that should be set to low resistance resistance states, that is, through separate programming, part of the resistive memristors 101 that have been uniformly programmed are in low resistance resistance states. state.

When the above-mentioned resistance variable memristor 101 is uniformly programmed, the signal input port of the shift register circuit can be used as the non-inverting input terminal of the programming voltage, and the inverting input terminal of each resistance variable memristor 101 can be used as the inverse input terminal of the programming voltage. phase input.

When the above-mentioned resistance variable memristor 101 is individually programmed, the signal input terminal of the column where the resistance variable memristor 101 is located can be used as the non-inverting input terminal of the programming voltage, and the inverting input terminal of the resistance variable memristor 101 As the inverting input terminal of the programming voltage, the inverting input terminal of each resistive memristor 101 in the same row as the resistive memristor 101 in the resistive memristor matrix 10 can also be used as the inverting input terminal of the programming voltage. phase input.

In the embodiment of the present invention, the resistive memristor 101 may be a unipolar resistive memristor, or a bipolar resistive memristor. When programming the resistive memristor 101, the programming voltage The size can be selected according to the unipolar or bipolar characteristics of the resistive memristor 101 .

Referring to the graphs of the conductivity of the unipolar resistive memristor as a function of voltage in FIG. 3a and FIG. and high-resistance resistance-state threshold voltage Vreset are both positive voltages. When performing unified programming on the resistance-variable memristors 101, since all resistance-variable memristors 101 are to be set to high resistance-value resistance states, the first programming The voltage V1 should satisfy: Vset>V1>Vreset, so that all the resistive memristors 101 in the resistive memristor square array 10 are set to a high-resistance resistance state; When each resistive memristor 101 that should be set to a low-resistance resistance state is individually programmed, the second programming voltage V2 should satisfy: V2>Vset.

Referring to the graph of the conductivity of the bipolar memristor as a function of voltage in FIG. , the threshold voltage Vreset of the high-resistance resistance state is a negative voltage. When performing unified programming on the resistance-variable memristors 101, since all the resistance-variable memristors 101 must be set to high-resistance resistance states, the programming voltage can be set to The non-inverting input terminal of the programming voltage is grounded, and the inverting input terminal of the programming voltage is connected to the third programming voltage V3, and V3 should satisfy: V3>|Vreset|, so that all the resistive memristors 101 in the resistive memristor matrix 10 are all set to a high-resistance resistance state; then, when individually programming each resistance-variable memristor 101 that should be set to a low-resistance resistance state in the resistance-variable memristor square matrix 10, the reverse phase of the programming voltage can be The input end is grounded, and the non-inverting input end of the programming voltage is connected to the fourth programming voltage V4, and V4>Vset.

The shift register circuit can select the corresponding function according to the needs, for example, the digital input signal is shifted to the left by one bit, or the digital input signal is shifted to the right by one bit, and the digital input signal and digital output signal corresponding to the above two functions can be As shown in Table 1, in Table 1, the digital input signal is represented by Din, the digital output signal when the digital input signal is shifted left by one bit is represented by Dout1, and the digital output signal when the digital input signal is shifted right by one bit is output by Dout2 said.

Table I:

Dining A1 A2 A3 ... AN-1 AN Dout1 A2 A3 A4 ... AN A1 Dout2 AN A1 A2 ... AN-2 AN-1

In the embodiment of the present invention, the resistive memristor 101 has two resistance states of high resistance and low resistance. , and OFF, when the same voltage is applied to both ends of the two resistive memristors 101 in different resistance states, there will be a large current in the resistive memristor in the low resistance state, and the resistance variable memristor in the high resistance state will There is almost no current in the resistive memristor in the resistance state, so the resistive memristor 101 has the characteristic of selective conduction.

In order to realize the function of the shift register circuit, among the resistive memristors 101 in each row of the resistive memristor matrix 10, there is only one resistive memristor 101 in a low-resistance resistance state, and the other resistive memristors 101 are in a low-resistance resistance state. The memristors 101 are all in a high-resistance resistance state, and similarly, this resistance state is also set in each column. Because of the selective conductivity of the resistive memristor 101 , the setting of this resistance state determines the position of each bit of the digital input signal in the digital output signal after passing through the shift register circuit.

As shown in Figure 5, when the function of the shift register circuit is a left-shift output, a schematic diagram of the resistance state setting of the resistance variable memristor in the shift register circuit, wherein the resistance state is in the low resistance value resistance state The memristor is represented by connecting lines to distinguish it from the resistive memristor whose resistance state is in a high resistance state.

Performing a one-bit left-shift output on the N-bit digital input signal is essentially shifting the lowest bit of the digital input signal to the highest bit, and shifting each of the remaining bits to the lower bit to generate a digital output signal. The resistance setting of the resistive memristor in Figure 5 determines the corresponding bit of the digital output signal corresponding to each bit of the digital input signal. For example, A1 in Figure 5 is the lowest bit of the digital input signal, and its corresponding resistance Among the resistive memristors in the same column in the variable memristor square array, only the bottom one is in a low-resistance resistance state, and this resistive memristor corresponds to the highest bit of the digital output signal , so the lowest bit A1 of the digital input signal is shifted to the highest bit of the digital output signal. Similarly, the remaining bits of the digital input signal are also shifted to the corresponding bits of the corresponding digital output signal through such a selective conduction method. .

As shown in Figure 6, it is a schematic diagram of the resistance setting of the resistance change memristor in the shift register circuit when the function of the shift register circuit is a bit right shift output, wherein the resistance change state is in the low resistance resistance state The memristor is represented by connecting lines to distinguish it from the resistive memristor whose resistance state is in a high resistance state.

Performing a one-bit right-shift output on the N-bit digital input signal is essentially shifting the highest bit of the digital input signal to the lowest bit, and shifting each other bit to the upper bit, thereby generating a digital output signal. The resistance setting of the resistive memristor in Figure 6 determines the corresponding bit of the digital output signal corresponding to each bit of the digital input signal. For example, AN in Figure 6 is the highest bit of the digital input signal, and its corresponding resistance Among the resistive memristors in the same column in the variable memristor square array, only the uppermost resistive memristor is in a low-resistance resistance state, and this resistive memristor corresponds to the lowest bit of the digital output signal , so the highest bit AN of the digital input signal is shifted to the lowest bit of the digital output signal. Similarly, the remaining bits of the digital input signal are also shifted to the corresponding bits of the corresponding digital output signal through such a selective conduction method. .

In addition, the above-mentioned resistive memristor may be any one of RRAM, PRAM, FRAM and MRAM.

The shift register circuit provided by the embodiment of the present invention does not completely use the traditional MOS tube storage device in its circuit composition, but uses a new type of storage device with a two-terminal structure, such as a resistive memristor. Memristors have the characteristics of good scalability, high storage density, low power consumption, fast read and write speed, strong resistance to repeated operations, and long data retention time. Therefore, while effectively saving the area occupied by the shift register circuit, The programmable performance of the shift register circuit is realized.

The embodiment of the present invention also provides a chip, including: a top electrode metal strip, a bottom electrode metal strip and a shift register circuit. The shift register circuit includes: a square matrix of resistive memristors and a current sensitive module, wherein the positive phase input terminals of the same column of resistive memristors in the square matrix of resistive memristors are connected through top electrode metal strips, so that The non-inverting input terminal of the same row of resistive memristors is used as the signal input port, and the inverting input terminal of the same row of resistive memristors in the same row of resistive memristors is connected to the input terminal of a current sensitive module through the metal strip of the bottom electrode. Connected so that the output terminal of the current sensing module is used as a signal output port.

Wherein, the input terminal of the current sensitive module is connected to a low level when working, and when the current received by the input terminal of the current sensitive module is greater than the threshold current, the output terminal of the current sensitive module outputs a high level, and the When the current received by the input end of the current sensing module is less than the threshold current, the output end of the current sensing module outputs a low level.

Preferably, the resistance state of the resistance variable memristor includes: a high resistance value resistance state and a low resistance value resistance state; A resistance variable memristor in a resistance state; and, there is a resistance variable memristor in a low resistance state among the resistance variable memristors in the same column in the resistance variable memristor square array.

Preferably, the resistive memristor includes: a unipolar resistive memristor or a bipolar resistive memristor; and, the resistive memristor includes: RRAM or PRAM or FRAM or MRAM.

In the embodiment of the present invention, in order to reduce the size of the chip as much as possible, the metal strips of the top electrode and the metal strips of the bottom electrode can be vertically intersected to form a resistive memristor at each intersection point, for example, the resistive memristor is It is formed by filling the intersection of the top electrode metal strip and the bottom electrode metal strip with a resistive variable medium.

In addition, the top electrode metal strips and the bottom electrode metal strips may be respectively disposed on different metal layers in the chip, for example, two adjacent metal layers.

In the embodiment of the present invention, since the resistive memristor is compatible with the Complementary Metal Oxide Semiconductor (CMOS, Complementary Metal Oxide Semiconductor) process, the manufacturing process of the chip is simple.

The chip provided by the embodiment of the present invention includes the top electrode metal strip, the bottom electrode metal strip and the shift register circuit. In its circuit configuration, the traditional MOS tube storage device is not completely used, but the resistive memristor is partially used. Resistive memristor, a new type of storage device with two-terminal structure, has the characteristics of good scalability, high storage density, low power consumption, fast read and write speed, strong tolerance to repeated operations, and long data retention time. Therefore, while effectively saving the area occupied by the shift register circuit, the programmable performance of the shift register circuit is realized, the size of the chip is correspondingly reduced, and the performance of the chip is improved.

The above description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the embodiments of the invention. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the embodiments of the present invention . Therefore, the embodiments of the present invention will not be limited to these embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

The above descriptions are only preferred embodiments of the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. Any modifications, equivalent replacements, improvements, etc. within the spirit and principles of the embodiments of the present invention are It should be included in the protection scope of the embodiments of the present invention.

Claims (6)

1. A kind of shift register circuit, it is characterized in that, comprising: Resistive memristor matrix and current sensitive module; The positive-phase input terminals of the same column of resistance-variable memristors in the square array of resistance-variable memristors are connected, so that the normal-phase input terminals of the same column of resistance-variable memristors are used as signal input ports; The inverting input terminals of the same row of resistive memristors in the matrix of resistive memristors are connected to the input terminal of one of the current sensitive modules, so that the output terminal of the current sensitive module serves as a signal output port; The input terminal of the current sensitive module is connected to a low level when working, and when the current received by the input terminal of the current sensitive module is greater than the threshold current, the output terminal of the current sensitive module outputs a high level, and the current sensitive module outputs a high level. When the current received by the input terminal of the module is less than the threshold current, the output terminal of the current sensitive module outputs a low level; Wherein, the current sensitive module is composed of a mirror current source circuit, a load resistor and a comparator, the input terminal of the mirror current source circuit is used as the input terminal of the current sensitive module, and the output terminal of the mirror current source circuit passes through the The load resistance is connected to the non-inverting input terminal of the comparator, the inverting input terminal of the comparator is connected to the reference level, and the output terminal of the comparator is used as the output terminal of the current sensitive module; Wherein, the resistance state of the resistive memristor includes: a high resistance resistance state and a low resistance resistance state; Wherein, the resistive memristors in the same row in the resistive memristor array have a resistive memristor in a low-resistance resistance state; and, the same column in the resistive memristor array The resistive memristor has a resistive memristor in a low-resistance resistance state. 2. The shift register circuit according to claim 1, wherein the resistive memristor comprises: a unipolar resistive memristor or a bipolar resistive memristor. 3. The shift register circuit according to claim 1, wherein the resistive memristor comprises: a resistive memory (RRAM), a phase change memory (PRAM), a ferroelectric memory (FRAM), or a magnetic memory (MRAM). 4. A chip, characterized in that it comprises: a top electrode metal strip, a bottom electrode metal strip and a shift register circuit; The shift register circuit includes: a resistive memristor matrix and a current sensitive module; The positive-phase input terminals of the same column of resistance-variable memristors in the square array of resistance-variable memristors are connected through the top electrode metal strip, so that the normal-phase input terminals of the same column of resistance-variable memristors serve as signal input port; The inverting input terminal of the resistance variable memristor of the same row in the resistance variable memristor square array is connected with the input terminal of one of the current sensitive modules through the bottom electrode metal strip, so that the current sensitive module’s The output terminal is used as a signal output port; The input terminal of the current sensitive module is connected to a low level when working, and when the current received by the input terminal of the current sensitive module is greater than the threshold current, the output terminal of the current sensitive module outputs a high level, and the current sensitive module outputs a high level. When the current received by the input terminal of the module is less than the threshold current, the output terminal of the current sensitive module outputs a low level; Wherein, the current sensitive module is composed of a mirror current source circuit, a load resistor and a comparator, the input terminal of the mirror current source circuit is used as the input terminal of the current sensitive module, and the output terminal of the mirror current source circuit passes through the The load resistance is connected to the non-inverting input terminal of the comparator, the inverting input terminal of the comparator is connected to the reference level, and the output terminal of the comparator is used as the output terminal of the current sensitive module; Wherein, the resistance state of the resistive memristor includes: a high resistance resistance state and a low resistance resistance state; Wherein, the resistive memristors in the same row in the resistive memristor array have a resistive memristor in a low-resistance resistance state; and, the same column in the resistive memristor array The resistive memristor has a resistive memristor in a low-resistance resistance state. 5. The chip according to claim 4, wherein the resistive memristor comprises: a unipolar resistive memristor or a bipolar resistive memristor. 6 . The chip according to claim 4 , wherein the resistive memristor comprises: a resistive memory (RRAM), a phase change memory (PRAM), a ferroelectric memory (FRAM), or a magnetic memory (MRAM).