CN102882585A

CN102882585A - Data recording and playback device, system and method

Info

Publication number: CN102882585A
Application number: CN2012103266101A
Authority: CN
Inventors: 张洪群; 吴业炜; 韩家玮; 李安; 张彧; 张国敬
Original assignee: CENTER FOR EARTH OBSERVATION AND DIGITAL EARTH CHINESE ACADEMY OF SCIENCES; Tsinghua University
Current assignee: CENTER FOR EARTH OBSERVATION AND DIGITAL EARTH CHINESE ACADEMY OF SCIENCES; Tsinghua University
Priority date: 2012-09-05
Filing date: 2012-09-05
Publication date: 2013-01-16
Anticipated expiration: 2032-09-05
Also published as: CN102882585B

Abstract

The invention provides a data recording and playback system. The system includes a signal input circuit, a signal output circuit, two storage units, first and second FPGAs cooperating with each other, and an external recording device. The two storage units and the second FPGA form a cache structure to perform ping-pong cache processing on data. The storage capacity of the two storage units is determined by the first FPGA according to the data rate of the input data. With this data recording and playback system, it is possible to adaptively adapt to changes in data rates in high-speed data transmission without manual system changes. In addition, problems such as system overflow caused by instantaneous high-speed signal input and output can be eliminated.

Description

The device, the system and method that are used for data record and playback

Technical field

The present invention relates to digital communication technology field, more specifically, relate to and a kind of high-speed digital signal is recorded data record and playback system and method with playback.

Background technology

In the high-speed digital communication system design process, for the ease of debugging and testing communication system, need to produce specific data and use this particular data that systematic function is debugged and tested.Simultaneously, in order to improve actual test and the system-level uniting and adjustment efficient in when examination, the signal of receiving in the test process need to be recorded first as requested, and in the process of debugging, the recorded data file is carried out playback with the form code speed as required of the signal of telecommunication, so that in debug process, find the problem that exists in the correction system also.

In remote sensing and satellite communication system, message transmission rate can change in the scope of 1000Mbps at 1 MBPS (Mbps).In some main flow remote sensing and satellite communication system, message transmission rate has reached 100Mbps, or even the magnitude of Gigabits per second (Gbps), for example NASA and JAXA have had a plurality of satellite projects to realize the downlink transfer link of Gbps magnitude, and the transmission rate of China's Aerospace Satellite communication of future generation also will reach the Gbps magnitude.

For the changes in data rate of the 1Mbps in adaptive remote sensing and the satellite communication system to 1000Mbps, at present remote sensing and the employed high-speed data recording of satellite communication system and playback system, manual change system need to be set usually.These manual change systems cause the complicated operation of high-speed data recording and playback system and mistake occurs easily.In addition, in present high-speed record and playback system since moment high speed signal input and output, the unstable situation such as cause system to produce overflowing.

Summary of the invention

In view of the above problems, an object of the present invention is to provide a kind of data record and playback system and method, it is the variation in the adaptation data transmission rate adaptively.

Another object of the present invention provides a kind of device and method for realizing high-speed data recording.

Another object of the present invention provides a kind of device and method for realizing the high-speed data playback.

According to an aspect of the present invention, provide a kind of device for realizing high-speed data recording, comprising: signal input circuit is configured to receive the baseband signal from the outside input, and the baseband signal that receives is converted to data; The one FPGA, link to each other with described signal input circuit and link to each other with the external record device by bus, be configured to from the signal input circuit receive data, and the data that receive are continued to output to the 2nd FPGA, and after receiving data from the 2nd FPGA, the data communication device that receives is crossed bus transfer in the external record device, carry out record; The 2nd FPGA, link to each other with a described FPGA, be configured to be written to from the data that a FPGA receives in the memory cell the first and second memory cell, simultaneously from another memory cell reading out data and be buffered in the inner buffer of the 2nd FPGA, and when the size of the data of inner buffer institute buffer memory reaches the first predetermined value, the data of inner buffer are sent to a FPGA; The first and second memory cell, link to each other with described the 2nd FPGA, the ping-pong buffer operation is carried out in wherein said two memory cell and described the 2nd FPGA cooperation, wherein, the memory capacity equal and opposite in direction of described the first and second memory cell, and control the 2nd FPGA by a FPGA according to the speed of input signal and set.

In one or more examples aspect above-mentioned, described device can also comprise: level and serial to parallel conversion unit are used for the signal from the outside input is carried out level and serial to parallel conversion.

In one or more examples aspect above-mentioned, described device can also comprise: bridge, be used for the bridge joint between realization the first bus and the second bus, wherein, a described FPGA links to each other by the first bus with bridge, and described bridge links to each other by the second bus with the external record device.

In one or more examples aspect above-mentioned, described bridge can be PEX 8311.

According to a further aspect in the invention, provide a kind of device for realizing the high-speed data playback, comprising: signal output apparatus is used for the data that receive are converted to baseband signal; The 3rd FPGA, link to each other with described signal output apparatus and link to each other with the external record device by bus, be configured to read recorded data from the external record device, and the data that read are transferred to the 4th FPGA constantly, and after receiving data from the 4th FPGA, carry out playback after the data that receive are transferred to signal output apparatus and are converted to baseband signal according to assigned rate; The 4th FPGA, link to each other with described the 3rd FPGA, be configured to be written to from the data that the 3rd FPGA receives in the internal storage location the third and fourth memory cell, simultaneously from another internal storage location reading out data and be buffered in the inner buffer of the 4th FPGA, and when the size of the data of inner buffer institute buffer memory reaches the second predetermined value, the data of inner buffer are sent to the 3rd FPGA; And third and fourth memory cell, linking to each other with described the 4th FPGA, the ping-pong buffer operation is carried out in wherein said the third and fourth memory cell and described the 4th FPGA cooperation.

In one or more examples aspect above-mentioned, described signal output apparatus can also comprise: level and parallel serial conversion unit are used for carrying out and string and level translation from the data of the 3rd FPGA output.

In one or more examples aspect above-mentioned, described device can also comprise: bridge, be used for the bridge joint between realization the first bus and the second bus, wherein, described the 3rd FPGA links to each other by the first bus with bridge, and described bridge links to each other by the second bus with the external record device.

In one or more examples aspect above-mentioned, described assigned rate is according to the playback rate information setting in the data readback instruction that receives by the 3rd FPGA.

In one or more examples aspect above-mentioned, described assigned rate be by the 3rd FPGA according to the playback rate information in the data readback instruction that receives, set by frequency synthesizer.

According to a further aspect in the invention, provide a kind of data record and playback system, comprising: aforesaid device for realizing high-speed record; Aforesaid for realizing the high-speed playback device; And tape deck.

In one or more examples aspect above-mentioned, a described FPGA is identical with the 4th FPGA with described the 3rd FPGA respectively with the 2nd FPGA, and described the first and second memory cell are identical with described the third and fourth memory cell respectively.

According to a further aspect in the invention, a kind of data record method of being carried out by the device that is used for the realization high-speed data recording is provided, comprise: receive the baseband signal of inputting from the outside and be converted to data by signal input circuit, and the FPGA of the transfer of data to the after will changing; The one FPGA continues to output to the 2nd FPGA with the data that receive; The 2nd FPGA will be written to from the data that a FPGA receives in the memory cell the first and second memory cell, simultaneously from another memory cell reading out data and be buffered in the inner buffer of the 2nd FPGA, and when the size of the data of inner buffer institute buffer memory reaches the first predetermined value, the data of inner buffer are sent to a FPGA; And after receiving data from the 2nd FPGA, the one FPGA carries out record with the transfer of data that receives by bus in the external record device, wherein, the memory capacity equal and opposite in direction of described the first and second memory cell, and control the 2nd FPGA by a FPGA according to the speed of input signal and set.

According to a further aspect in the invention, a kind of data readback method of being carried out by the device that is used for the playback of realization high-speed data is provided, comprise: the 3rd FPGA reads recorded data by bus from the external record device, and the data that read are transferred to the 4th FPGA constantly; The 4th FPGA will be written to from the data that the 3rd FPGA receives in the internal storage location the third and fourth memory cell, simultaneously from another internal storage location reading out data and be buffered in the inner buffer of the 4th FPGA, and when the size of the data of inner buffer institute buffer memory reaches the second predetermined value, the data of inner buffer are sent to the 3rd FPGA; And after receiving data from the 4th FPGA, the 3rd FPGA is transferred to the data that receive signal output apparatus according to assigned rate and is converted to baseband signal and carries out playback.

Utilize above-mentioned data record and playback system, the changes in data rate in the adaptive high speed data transfer adaptively, and need not manually to change system.In addition, can also eliminate owing to moment high speed signal input and output the problem such as cause system to produce overflowing.

In order to realize above-mentioned and relevant purpose, one or more aspects of the present invention comprise the feature that the back will describe in detail and particularly point out in the claims.Following explanation and accompanying drawing describe some illustrative aspects of the present invention in detail.Yet, the indication of these aspects only be some modes that can use in the variety of way of principle of the present invention.In addition, the present invention is intended to comprise all these aspects and their equivalent.

Description of drawings

According to following detailed description of carrying out with reference to accompanying drawing, above and other purpose of the present invention, feature and advantage will become more apparent.In the accompanying drawings:

Fig. 1 shows the structured flowchart according to the device that is used for high-speed data recording of the embodiment of the invention;

Fig. 2 shows the schematic diagram of a realization example of the signal input circuit of the device among Fig. 1;

Fig. 3 shows the bus control structure according to the embodiment of the invention;

Fig. 4 shows the data buffer storage structure according to the many speed of adaptation of the embodiment of the invention;

Fig. 5 shows the structured flowchart according to the device that is used for the high-speed data playback of the embodiment of the invention;

Fig. 6 shows the schematic diagram of a realization example of the signal output apparatus of the device among Fig. 5;

Fig. 7 shows the structured flowchart according to data record of the present invention and playback system;

Fig. 8 shows the schematic diagram according to an example of data record of the present invention and playback system;

Fig. 9 shows according to the Bit Error Code Statistics structure in data record of the present invention and the playback system;

Figure 10 shows the flow chart for the method for carrying out high-speed data recording according to the embodiment of the invention; With

Figure 11 shows the flow chart for the method for carrying out the high-speed data playback according to the embodiment of the invention.

Identical label is indicated similar or corresponding feature or function in institute's drawings attached.

Embodiment

Various aspects of the present disclosure are described below.Should be understood that the instruction of this paper can be with varied form imbody, and disclosed any concrete structure, function or both only are representational in this article.Based on the instruction of this paper, those skilled in the art should be understood that an aspect disclosed herein can be independent of any other side and realize, and the two or more aspects in these aspects can make up according to variety of way.For example, can use the aspect of any number described in this paper, implement device or hands-on approach.In addition, can use other structure, function or except one or more aspects described in this paper or be not the 26S Proteasome Structure and Function of one or more aspects described in this paper, realize this device or put into practice this method.In addition, any aspect described herein can comprise at least one element of claim.

Below in conjunction with description of drawings according to embodiments of the invention.

Fig. 1 shows the structured flowchart according to the device 100 that is used for high-speed data recording of the embodiment of the invention.

As shown in Figure 1, device 100 comprises signal input circuit 110, a FPGA 120, the 2nd FPGA130, the first internal storage location 140 and the second internal storage location 150.

Signal input circuit 110 links to each other with a FPGA.When carrying out high-speed data recording, signal input circuit 110 is configured to receive from the baseband signal of outside input, such as the ECL level signal from the outside input, and the baseband signal that receives is converted to data.Subsequently, will be through transfer of data to the FPGA 120 who obtains after the conversion.

In an embodiment according to the present invention, the level of the baseband signal that receives of signal input circuit 110 can require different from the level of the input signal of a FPGA 120.In addition, the baseband signal that signal input circuit 110 receives can be serial signal, rather than the desired parallel signal of the input signal of FPGA.In this case, signal input circuit 110 can also comprise level and serial to parallel conversion unit, is used for the baseband signal that receives from the outside is carried out level and serial to parallel conversion.Fig. 2 shows the configuration diagram of a realization example of signal input circuit in the time need to carrying out level and serial to parallel conversion to the baseband signal of outside input.

As shown in Figure 2, the level of the baseband signal of outside input is the ECL level.Shown in figure 2 in the circuit structure, at first, by EP 90 chips the baseband signal of this outside input being carried out level translation, is LVPECL with the level translation of this baseband signal.Then, utilize FPGA (Field Programmable Gate Array) delay chip MC10EP195 that the clock signal of EP 90 chips output is postponed, thereby realize strictly aliging of data and clock signal.The theoretical transmission rate of this chip is 1.2GHz, and delay precision is 10ps.Then, utilize the MC10EP445 chip data are gone here and there and to change, the data flow of maximum 1Gbps is become the parallel data stream of 8 road maximum 125MHz.Then, the parallel LVPECL signal that the MC10EP445 conversion is obtained by the MC100LVELT23 chip is converted into the LVTTL level signal and gives FPGA, and the MC100LVELT23 chip is that binary channels LVTTL drives chip, and the single channel transmission rate can reach more than the 180MHz.FPGA receives by the LVTTL interface.FPGA module (that is, a FPGA and the 2nd FPGA) adopts StratixII EP2S180F1020C3 chip, and maximum operating frequency reaches 550MHz, and wherein LVTTL interface transmission rate can reach 250Mbps.In addition, also comprise the MC100EPT22 chip in this signal input circuit, in order to realizing the LVTTL level to the conversion of LVPECL level, and realize control to above chip.

The one FPGA 120 is configured to receive the data from signal input circuit output.In addition, a FPGA 120 links to each other with the 2nd FPGA 130, is used for the data that receive are continued to output to the 2nd FPGA130.And, the one FPGA 120 also is configured to link to each other with the external record device by bus, be used for when carrying out data record, after the data that receive the 2nd FPGA 130 transmission, by bus the transfer of data that receives carried out record in the external record device.

The 2nd FPGA 130 links to each other with the second memory cell 150 with the first memory cell 140, and be configured to be written to from the data that a FPGA 120 receives in the memory cell the first memory cell 140 and the second memory cell 150, simultaneously from another memory cell reading out data and be buffered in the inner buffer of the 2nd FPGA130.In addition, when the size of the data of inner buffer institute buffer memory reached the first predetermined value, the 2nd FPGA 130 was configured to the data of inner buffer are sent to a FPGA 120.

Described the first memory cell 140 and the second memory cell 150 are configured to data cached.In the present invention, the mode of utilizing two memory cell (being in this example the DDR2 internal memory) to cooperate with the inside FIFO of the 2nd FPGA 130 is carried out the ping-pong buffer operation, realizes the buffer memory of highspeed serial data stream.When carrying out the ping-pong buffer operation, control the hardware time order of the first memory cell 140 and the second memory cell 150 by the 2nd FPGA 130.

For example, in the embodiment shown in fig. 1, the inner buffer of the first memory cell 140, the second memory cell 150 and the 2nd FPGA 130 (that is, FIFO) forms buffer structure, and cooperates to come together to the operation of data-signal execution ping-pong buffer.Described ping-pong buffer operation refers to when a memory cell is carried out write operation, and another memory cell is carried out read operation.To the first memory cell 140 and the second memory cell 150 carry out write and/or the switching sequence of read operation by the 2nd FPGA 130 controls.When 130 pairs of memory cell of the 2nd FPGA were carried out write operation and write full this memory cell, the 2nd FPGA 130 became this memory cell execution read operation.When 130 pairs of memory cell of the 2nd FPGA were carried out read operation and read empty this memory cell, the 2nd FPGA 130 became this memory cell execution write operation.In addition, the memory capacity of the first memory cell 140 and the second memory cell 150 is set to equal and opposite in direction usually, and should size controls the 2nd FPGA 130 by a FPGA 120 according to the speed of input signal and set.

In addition, in data recording process, data need to the device 100 and the external record device (for example, computer) transmits between, in order to reach the upper limit requirement of speed, device 100 can also comprise bridge 160, is used for the bridge joint between realization the first bus and the second bus.In this case, usually need to link to each other by the first bus (that is, local bus) between a FPGA 120 and the bridge 160, and bridge 160 and external record device are (for example, computer) links to each other by the second bus (for example, PCI-E bus).In an example of the present invention, described bridge 160 can adopt the PEX8311 of PLX company.

Fig. 3 shows the diagram according to an example of the bus control structure of the embodiment of the invention.Figure 3 illustrates the relation of fpga chip, PEX8311 chip and PCI-E interface bus.PEX8311 is the bridging chip that a PCI-E bus of PLX company arrives local bus, supports the one-way transmission speed of 2.5Gbps, and data can be transmitted mutually by PCI-E bus and computer, satisfies rate requirement.The clock that local bus adopts the 66M crystal oscillator to produce, data are with 32bit bit wide parallel transmission.

Fig. 4 shows the schematic diagram according to an example of the data buffer storage structure of the many speed of adaptation of the embodiment of the invention, adopt in the figure bridge PEX8311, when carrying out data record, the api function that at first utilizes PLX company to provide is opened the DMA transmission of PEX8311.

As shown in Figure 4, the work clock of DDR2 internal memory is 100MHz, is provided by FPGA.Owing to save as the 64bit highway width in the DDR2, so the interface rate of DDR2 internal memory can reach more than the 12Gbps, can tackle the serial data stream of 1Gbps fully.When carrying out data record, a FPGA 120 will input data and constantly be written to the 2nd FPGA 130, the two FPGA 130 and write data into and carry out buffer memory in the DDR2 internal memory.When a slice DDR2 internal memory is written into, the 2nd FPGA 130 sense data and being cached among the FIFO of the 2nd FPGA 130 from another sheet DDR2 internal memory.When data in the FIFO during greater than the first predetermined value, the 2nd FPGA 130 passes to a FPGA 120 with the data of buffer memory among the FIFO.Subsequently, a FPGA 120 passes to bridge PEX8311 with data.Then, by the DMA transmission, data-signal is transferred in the assigned address (for example, specified file) of external record device (for example, computer) from bridge PEX8311.In addition, when of short duration obstruction appears in the DMA of PEX8311 transmission, the 2nd FPGA 140 reading out data from the DDR2 internal memory also will suspend, but the data that do not affect another piece internal memory write.

In addition, can mate adaptively 1Mbps to the changes in data rate of 1000Mbps in order to make system, and can be because of the input and output of moment high speed signal, causing system to produce overflows, in the present invention, the memory capacity size (being buffer size) of the first memory cell 140 and the second memory cell 150 is set to set according to the data rate of input data, is namely set according to data rate control the 2nd FPGA of input signal by a FPGA.For example, externally the tape deck end (for example, the buffer size of the computer software end), according to input data rate needs being opened up reaches a FPGA 120, the one FPGA 120 by order and then can control the 2nd FPGA 130 and set buffer size.

In the present invention, buffer size is relevant with input data rate.When input data rate was fast, buffer area was set to larger, thereby it is low and cause cache overflow to prevent that factor data from writing the momentary rate of PEX8311.In addition, buffer size also cannot be set to excessive, otherwise in the starting stage, and data are write full a slice DDR2 internal memory to be needed for a long time, will cause the FPGA for a long time can't reading out data, affects record efficiency.

Fig. 5 shows the structured flowchart according to the device 500 that is used for the high-speed data playback of the embodiment of the invention.As shown in Figure 5, device 500 comprises signal output apparatus 510, the 3rd FPGA 520, the 4th FPGA530, the 3rd memory cell 540 and the 5th memory cell 550.

Signal output apparatus 510 is used for the data that receive are converted to baseband signal.The 3rd FPGA 520 links to each other with the external record device by bus.In addition, the 3rd FPGA 520 also links to each other with the 4th FPGA 530 with described signal output apparatus 510.When carrying out data readback, the 3rd FPGA 520 is configured to read recorded data by bus from external record device (for example, computer), and the data that read are transferred to the 4th FPGA constantly.In addition, after receiving data from the 4th FPGA 530, the 3rd FPGA 520 also is configured to the data that will receive, is transferred to signal output apparatus 510 according to assigned rate, and carries out playback after being converted to signal by signal output apparatus 510.Described assigned rate is according to the playback rate information setting in the data readback instruction that receives by the 3rd FPGA.In an example of the present invention, described assigned rate be by the 3rd FPGA according to the playback rate information in the data readback instruction that receives, set by the adjustable frequency synthesizer.

The 4th FPGA 530 links to each other with described the 3rd FPGA 520, the 3rd memory cell 540 and the 4th memory cell 550.The inner buffer of the 4th FPGA 530 and the third and fourth memory cell form buffer structure, and data-signal is carried out the ping-pong buffer operation.

The 4th FPGA 530 is configured to be written to from the data that the 3rd FPGA 520 receives in the internal storage location the third and fourth memory cell, simultaneously from another internal storage location reading out data and be buffered in the inner buffer of the 4th FPGA 530.In addition, when the size of the data of inner buffer institute buffer memory reaches the second predetermined value, the data of inner buffer are sent to the 3rd FPGA 520.

In another example of the present invention, device 500 can also comprise bridge 560, is used for the bridge joint between realization the first bus and the second bus.In this case, connect by the first bus (for example, local bus) between the 3rd FPGA 520 and the bridge 560, and bridge 560 and external record device are (for example, computer) connects by the second bus (for example, PCI-E bus) between.

In addition, in another example of the present invention, device 500 can also comprise frequency synthesizer 570, is used for the rate information according to the data readback instruction that receives from the 3rd FPGA, playback rate when data readback is set, namely the 3rd FPGA is transferred to the assigned rate of signal output apparatus.

In addition, in another example of the present invention, similar with the signal input circuit 110 among Fig. 1, data-signal output circuit 510 also can comprise and string and level translation unit, be used for to carrying out and string and level translation from the data of the 3rd FPGA output, to be converted to baseband signal.

Fig. 6 shows the schematic diagram according to operation principle and the process of data readback of the present invention.In this process, the user arranges playback rate by external record device end (for example, computer software end).When the 3rd FPGA 520 receives the data readback instruction, the playback rate size information is passed to frequency synthesizer 570 by command word.The sinusoidal signal of frequency synthesizer 570 output corresponding frequencies, sinusoidal signal is become the clock signal of PECL level by the MAX9600 chip, to give I/Q parallel-serial conversion chip be MC10EP446 to the PECL of MAX9600 chip output through driving all the time chip MC100EP14 again, it can carry out 1/8 frequency division according to input clock signal simultaneously, 1/8 fractional frequency signal that obtains given pass to FPGA after the MC100LVELT23 chip becomes the LVTTL level signal, realize the output of 8 parallel-by-bit data.In addition, in the circuit shown in Fig. 6, also adopt delay chip MC10EP195 that the serial i/Q signal of output is alignd with clock signal, be converted into the NECL level signal by the LVPECL clock signal of clock delay chip output and I, the Q two paths of signals of chip MC10EP446 output through the MC100EP91 chip.The end of playback section is the MC10EP16 chip, in order to driving N ECL level signal.

Here be noted that above-mentioned the first predetermined value and the second predetermined value are set to fixed value usually, can be identical, also can be different.

Fig. 7 shows the structured flowchart according to data record of the present invention and playback system 10.As shown in Figure 7, data record and playback system 10 comprise aforesaid device 100, aforesaid device 500, tape deck 200.

Fig. 8 shows the schematic diagram according to an example of data record of the present invention and playback system 10.In this example, a described FPGA is identical with the 4th FPGA with described the 3rd FPGA respectively with the 2nd FPGA, and described the first and second memory cell are identical with described the third and fourth memory cell respectively.In other words, a FPGA and the 3rd FPGA are same chips, and the 2nd FPGA and the 4th FPGA are same chips, and the first memory cell and the 3rd memory cell are same memory cell, and the second memory cell and the 4th memory cell are same memory cell.

In an example of the present invention, data record and playback system 10 can also have the Bit Error Code Statistics function.Fig. 9 shows the diagram according to the structure that is used for the realization Bit Error Code Statistics in the data record of the embodiment of the invention and the playback system.

As shown in Figure 9, in a FPGA of data record and playback system 10, can also comprise: local M sequence generation module, synchronization module/XOR module and counting/Bit Error Code Statistics module.

M sequence generation module in local M sequence generation module and the external circuit all uses shift register and XOR gate to consist of.

When the M sequence that the outside M sequence generation module of inputting is generated is carried out Bit Error Code Statistics, received front several (number depends on the pattern of M sequence) data are input in the shift register of local M sequence generation module, make register self circulation obtain correct M sequence with channel synchronization.The M sequence that self-channel transmission is come makes data synchronously with the local M sequence that produces by synchronization module and carries out the XOR bit that locates errors.Then, error rate of system is added up and calculated to counting/Bit Error Code Statistics module to the errored bit number.At last, by the Mailbox register error rate numerical value that comparison obtains is transferred to server, thus the statistics of the settling signal error rate.32 mailbox registers that the Mailbox register can adopt PEX8311 to provide, the value of these registers can be read and write arbitrarily at the software section Using API Function, also can be read and write according to certain sequential by local bus by FPGA in hardware.

In the present invention, when carrying out high-speed data playback or record, the DMA data-transmission mode that utilizes PEX8311 to provide.Under the DMA transmission mode, the api function that provides by PLX company starts and the DMA transmission is set, and utilizes the data that api function obtains recording or the data that spread out of playback.

As above referring to figs. 1 through Fig. 9 data record according to the present invention and playback system are illustrated.The below is described data record according to the present invention and back method to Figure 11 with reference to Figure 10.

Figure 10 shows the flow chart for the method for carrying out high-speed data recording according to the embodiment of the invention.

As shown in figure 10, when carrying out high-speed data recording, at first, at step S1010, receive from the signal of outside input by signal input circuit, the signal that receives is converted to data, then will be through transfer of data to the FPGA who obtains after the conversion.Receiving after the data of signal input circuit transmission, at step S1020, a FPGA continues to output to the 2nd FPGA with the data that receive.

Then, at step S1030, the 2nd FPGA will be written to from the data that a FPGA receives in the memory cell the first and second memory cell, simultaneously from another memory cell reading out data and be buffered in the inner buffer of the 2nd FPGA.Here, the memory capacity equal and opposite in direction of described the first and second memory cell, and control the 2nd FPGA by a FPGA according to the speed of input data and set.

Then, at step S1040, judge whether the size of the data of inner buffer reaches the first predetermined value.When the size of the data of inner buffer institute buffer memory reaches the first predetermined value, that is, the judged result of step S1040 at step S1050, is sent to a FPGA with the data of inner buffer when being.After receiving data from the 2nd FPGA, at step S1060, a FPGA carries out record with the transfer of data that receives by bus in the external record device, finish thus the high-speed data recording process.Exist bridge (for example, PEX8311) in the situation, also need to utilize api function to open the DMA transfer function of PEX8311, and pass through local bus, import data into PEX8311 from a FPGA, then PEX8311 crosses the PCI-E bus with data communication device and passes to the external record device.

When carrying out data readback, at first, at step S1110, the 3rd FPGA reads recorded data by bus from the external record device, and the data-signal that reads is transferred to the 4th FPGA constantly.Exist bridge (for example, PEX8311) in the situation, also need to utilize api function to open the DMA transfer function of PEX8311, and by the PCI-E bus, import data into PEX8311 from the external record device, then PEX8311 crosses local bus with data communication device and passes to the 3rd FPGA.

After receiving data from the 3rd FPGA, at step S1120, the 4th FPGA will be written to from the data that the 3rd FPGA receives in the internal storage location the third and fourth memory cell, simultaneously from another internal storage location reading out data and be buffered in the inner buffer of the 4th FPGA.

Then, at step S1130, judge whether the size of the data of inner buffer institute buffer memory reaches the second predetermined value.When the size of the data of inner buffer institute buffer memory reached the second predetermined value, namely the judged result of step S1130 was when being, at step S1140, the 4th FPGA is sent to the 3rd FPGA with the data of inner buffer.

After receiving data from the 4th FPGA, at step S1150, the 3rd FPGA is transferred to signal output apparatus with the data that receive according to assigned rate, and is converted to baseband signal and carries out playback.

Utilize data record of the present invention and playback system, be provided for the memory capacity size (buffer size) of data cached memory cell by the data rate according to the input data, the changes in data rate in the matched data transmission adaptively, and need not to arrange manual change system.

In addition, the cache size by buffer structure of the present invention is set to enough large, even the input and output of moment high speed signal occur, and can be because not overflowing obliterated data yet.

In addition, the method according to this invention can also be implemented as the computer program of being carried out by CPU.When this computer program is carried out by CPU, carry out the above-mentioned functions that limits in the method for the present invention.

In addition, said method step and system unit also can utilize controller (for example, processor) and be used for storage so that controller is realized the computer readable storage devices realization of the computer program of above-mentioned steps or Elementary Function.

Although the disclosed content in front shows exemplary embodiment of the present invention, should be noted that under the prerequisite of the scope of the present invention that does not deviate from the claim restriction, can carry out multiple change and modification.Function, step and/or action according to the claim to a method of inventive embodiments described herein do not need to carry out with any particular order.In addition, although element of the present invention can be with individual formal description or requirement, also it is contemplated that a plurality of, unless clearly be restricted to odd number.

Be described although as above described each embodiment according to the present invention with reference to figure, it will be appreciated by those skilled in the art that each embodiment that the invention described above is proposed, can also make various improvement on the basis that does not break away from content of the present invention.Therefore, protection scope of the present invention should be determined by the content of appending claims.

Claims

1. A device for realizing high-speed data recording, comprising:

a signal input circuit configured to receive a baseband signal input from the outside, and convert the received baseband signal into data;

The first FPGA, which is connected to the signal input circuit and connected to the external recording device through a bus, is configured to receive data from the signal input circuit, and continuously output the received data to the second FPGA, and receive the data from the second FPGA After receiving the data, transmit the received data to an external recording device through the bus for recording;

The second FPGA, connected to the first FPGA, is configured to write data received from the first FPGA into one of the first and second storage units, while reading data from the other storage unit and cached in the internal cache of the second FPGA, and when the size of the cached data in the internal cache reaches a first predetermined value, the data in the internal cache is transmitted to the first FPGA;

The first and second storage units are connected to the second FPGA, wherein the two storage units cooperate with the second FPGA to perform a ping-pong buffer operation,

Wherein, the storage capacities of the first and second storage units are equal, and are set by the first FPGA controlling the second FPGA according to the rate of the input signal.

2. The device according to claim 1, wherein the signal input circuit further comprises:

The level and serial-to-parallel conversion unit is used to perform level and serial-to-parallel conversion on the baseband signal input from the outside.

3. The apparatus of claim 1, further comprising:

a bus bridge, used to realize the bridging between the first bus and the second bus,

Wherein, the first FPGA is connected to the bus bridge through a first bus, and the bus bridge is connected to an external recording device through a second bus.

4. The apparatus of claim 1, wherein the bus bridge is a PEX 8311.

5. A device for realizing high-speed data playback, comprising:

a signal output circuit for converting the received data into a baseband signal;

The third FPGA, connected to the signal output circuit and connected to the external recording device through the bus, is configured to read the recorded data from the external recording device, and continuously transmit the read data to the fourth FPGA, and After receiving the data from the fourth FPGA, the received data is transmitted to the signal output circuit at a specified rate and converted into a baseband signal for playback;

A fourth FPGA, connected to the third FPGA, is configured to write data received from the third FPGA into one memory unit of the third and fourth storage units, while reading data from another memory unit and cached in the internal cache of the fourth FPGA, and when the size of the cached data in the internal cache reaches a second predetermined value, the data in the internal cache is transferred to the third FPGA; and

The third and fourth storage units are connected to the fourth FPGA, wherein the third and fourth storage units cooperate with the fourth FPGA to perform a ping-pong buffer operation.

6. The device according to claim 5, wherein the signal output circuit further comprises:

The level and parallel-to-serial conversion unit is used to perform parallel-to-serial and level conversion on the data output from the third FPGA.

7. The apparatus of claim 5, further comprising:

Wherein, the third FPGA is connected to the bus bridge through the first bus, and the bus bridge is connected to the external recording device through the second bus.

8. The apparatus according to claim 5, wherein the predetermined rate is set by the third FPGA according to playback rate information in the received data playback command.

9. The device according to claim 8, wherein the predetermined rate is set by the third FPGA through a frequency synthesizer according to playback rate information in the received data playback command.

10. A data recording and playback system, comprising:

A device as claimed in any one of claims 1 to 4;

An apparatus as claimed in any one of claims 5 to 9;

recording device.

11. The data recording and playback system as claimed in claim 10, wherein, the first FPGA and the second FPGA are respectively the same as the third FPGA and the fourth FPGA, and the first and second storage units are respectively Same as the third and fourth storage units.

12. A data recording method performed by the apparatus of claim 1, comprising:

receiving an externally input baseband signal through a signal input circuit and converting it into data, and transmitting the converted data to the first FPGA;

The first FPGA continuously outputs the received data to the second FPGA;

The second FPGA writes the data received from the first FPGA into one of the first and second storage units, and simultaneously reads the data from the other storage unit and caches it in the internal cache of the second FPGA, and at the same time When the size of the data cached in the internal cache reaches a first predetermined value, the data in the internal cache is transmitted to the first FPGA; and

After receiving the data from the second FPGA, the first FPGA transmits the received data to an external recording device via the bus for recording,

13. A data playback method performed by the device according to claim 5, comprising:

The third FPGA reads the recorded data from the external recording device through the bus, and continuously transmits the read data to the fourth FPGA;

The 4th FPGA writes the data received from the 3rd FPGA into one memory unit in the 3rd and the 4th storage unit, reads data from another memory unit simultaneously and caches in the internal cache of the 4th FPGA, and in When the size of the data cached in the internal cache reaches a second predetermined value, the data in the internal cache is transmitted to the third FPGA; and

After receiving the data from the fourth FPGA, the third FPGA transmits the received data to the signal output circuit at a specified rate and converts it into a baseband signal for playback.