CN102915952B - Manufacturing method for semiconductor device - Google Patents
Manufacturing method for semiconductor device Download PDFInfo
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- CN102915952B CN102915952B CN201110222354.7A CN201110222354A CN102915952B CN 102915952 B CN102915952 B CN 102915952B CN 201110222354 A CN201110222354 A CN 201110222354A CN 102915952 B CN102915952 B CN 102915952B
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- Prior art keywords
- layer
- silicon
- thermal oxide
- oxide layer
- silicon nitride
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 8
- 230000004888 barrier function Effects 0.000 claims abstract description 31
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910052802 copper Inorganic materials 0.000 claims abstract description 27
- 239000010949 copper Substances 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 26
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 25
- 239000010703 silicon Substances 0.000 claims abstract description 25
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims abstract description 17
- 229910010271 silicon carbide Inorganic materials 0.000 claims abstract description 17
- 238000009792 diffusion process Methods 0.000 claims abstract description 14
- 239000000758 substrate Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 45
- 239000002184 metal Substances 0.000 claims description 26
- 229910052751 metal Inorganic materials 0.000 claims description 26
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 24
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 22
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 22
- 238000005229 chemical vapour deposition Methods 0.000 claims description 17
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 12
- 239000000463 material Substances 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 12
- 239000000428 dust Substances 0.000 claims description 9
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 claims description 7
- 239000002243 precursor Substances 0.000 claims description 7
- 229910021529 ammonia Inorganic materials 0.000 claims description 6
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 claims description 5
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims description 5
- 229910000077 silane Inorganic materials 0.000 claims description 5
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 claims description 2
- 239000010410 layer Substances 0.000 abstract 11
- 238000009413 insulation Methods 0.000 abstract 3
- 150000004767 nitrides Chemical class 0.000 abstract 3
- 239000002355 dual-layer Substances 0.000 abstract 1
- 238000010276 construction Methods 0.000 description 8
- 238000005516 engineering process Methods 0.000 description 5
- 238000000151 deposition Methods 0.000 description 4
- 230000008021 deposition Effects 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- PQDJYEQOELDLCP-UHFFFAOYSA-N trimethylsilane Chemical compound C[SiH](C)C PQDJYEQOELDLCP-UHFFFAOYSA-N 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000000280 densification Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000003701 mechanical milling Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- NHDHVHZZCFYRSB-UHFFFAOYSA-N pyriproxyfen Chemical compound C=1C=CC=NC=1OC(C)COC(C=C1)=CC=C1OC1=CC=CC=C1 NHDHVHZZCFYRSB-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000002210 silicon-based material Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229940094989 trimethylsilane Drugs 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention provides a manufacturing method for a semiconductor device, comprising the following steps: a semiconductor substrate is provided, an insulation layer is formed on the semiconductor substrate, and a copper interconnecting wire is formed in the insulation layer; a silicon-rich nitride layer is formed on the insulation layer and the copper interconnecting wire; and a thermal oxide layer is formed on the silicon-rich nitride layer; and nitrogen-doped silicon carbide is formed on the thermal oxide layer. According to the manufacturing method for a semiconductor device, the silicon-rich nitride layer and the thermal oxide layer constitute a dual-layer copper diffusion barrier layer, and thermal oxide layer can effectively improve the damage of current, induced by plasma induced damage (PID), to the semiconductor device.
Description
Technical field
The present invention relates to semiconductor fabrication process, there is the copper metal diffusion barrier layer of new construction in particular to a kind of employing to improve the method for plasma-induced damage (PID).
Background technology
In existing advanced copper metal interconnect technology, conventionally use the silicon oxide carbide (SiCO) of porous as the material of dielectric layer, form carbonitride of silicium (SiCN) layer of a densification simultaneously thereon as copper metal diffusion barrier layer and etch stop layer.
Described SiCN layer stop copper metal to be diffused into the SiCO layer of porous and prevent through time play vital effect aspect dielectric breakdown, simultaneously as etch stop layer, the etching selectivity of itself and porous SiC O is greater than 8:1, can control well the etched shape of through hole.
But described SiCN layer can run into the problem of plasma-induced damage (PID), power while adopting plasma reinforced chemical vapour deposition (PECVD) technique to form described SiCN layer is greater than 200W, there will be obvious PID phenomenon, affect the electrology characteristic of described SiCN layer and porous SiC O layer.
Therefore, need to propose a kind of method of improving plasma-induced damage (PID) and induce the damage of the electric current generating to device to reduce PID.
Summary of the invention
For the deficiencies in the prior art, the invention provides a kind of manufacture method of semiconductor device, comprising: Semiconductor substrate is provided, in described Semiconductor substrate, forms an insulating barrier, and in described insulating barrier, form copper metal interconnecting wires; On described insulating barrier and copper metal interconnecting wires, form silicon-rich silicon nitride layer; On described silicon-rich silicon nitride layer, form thermal oxide layer; On described thermal oxide layer, form the silicon carbide layer of doping nitrogen.
Preferably, adopt chemical vapor deposition method to form described silicon-rich silicon nitride layer.
Preferably, the precursor material that forms described silicon-rich silicon nitride layer comprises silane and ammonia.
Preferably, the flow of described silane is 100-1000sccm; The flow of described ammonia is 100-500sccm.
Preferably, described chemical vapor deposition processes is at pressure 1-7Torr, under the condition of power 50-100W, carries out.
Preferably, the thickness of described silicon-rich silicon nitride layer is 30-150 dust.
Preferably, adopt chemical vapor deposition method to form described thermal oxide layer.
Preferably, the precursor material that forms described thermal oxide layer comprises tetraethoxysilane and ozone.
Preferably, the flow of described tetraethoxysilane is 50-500sccm; The flow of described ozone is 50-1000sccm.
Preferably, described chemical vapor deposition processes is to carry out under the condition of pressure 1-7Torr.
Preferably, the thickness of described thermal oxide layer is 100-500 dust.
Preferably, adopt chemical vapor deposition method to form the silicon carbide layer of described doping nitrogen.
Preferably, the thickness of the silicon carbide layer of described doping nitrogen is 50-300 dust.
Preferably, described silicon-rich silicon nitride layer and described thermal oxide layer form double-deck copper metal diffusion barrier layer.
Preferably, the silicon carbide layer of described doping nitrogen forms through hole etch stop layer.
Preferably, described insulating barrier is the material layer with low-k.
According to the present invention, can effectively improve plasma-induced damage (PID) and induce the infringement of the electric current generating to device.
Brief description of the drawings
Following accompanying drawing of the present invention is used for understanding the present invention in this as a part of the present invention.Shown in the drawings of embodiments of the invention and description thereof, be used for explaining principle of the present invention.
In accompanying drawing:
Figure 1A-Fig. 1 D is employing that the present invention the proposes copper metal diffusion barrier layer with new construction to improve the schematic cross sectional view of each step of method of plasma-induced damage (PID);
Fig. 2 is employing that the present invention the proposes copper metal diffusion barrier layer with new construction to improve the flow chart of method of plasma-induced damage (PID).
Embodiment
In the following description, a large amount of concrete details have been provided to more thorough understanding of the invention is provided.But, it is obvious to the skilled person that the present invention can be implemented without one or more these details.In other example, for fear of obscuring with the present invention, be not described for technical characterictics more well known in the art.
In order thoroughly to understand the present invention, will detailed step be proposed in following description, so that how explaination the present invention adopts the copper metal diffusion barrier layer with new construction to improve plasma-induced damage (PID).Obviously, execution of the present invention is not limited to the specific details that the technical staff of semiconductor applications has the knack of.Preferred embodiment of the present invention is described in detail as follows, but except these are described in detail, the present invention can also have other execution modes.
Should be understood that, when using in this manual term " to comprise " and/or when " comprising ", it indicates and has described feature, entirety, step, operation, element and/or assembly, exists or additional one or more other features, entirety, step, operation, element, assembly and/or their combination but do not get rid of.
Copper metal diffusion barrier layer that employing that the present invention proposes has a new construction is described to improve the detailed step of method of plasma-induced damage (PID) with reference to Figure 1A-Fig. 1 D and Fig. 2 below.
With reference to Figure 1A-Fig. 1 D, wherein show copper metal diffusion barrier layer that employing that the present invention proposes has a new construction to improve the schematic cross sectional view of each step of method of plasma-induced damage (PID).
First, as shown in Figure 1A, provide Semiconductor substrate 100, the constituent material of described Semiconductor substrate 100 can adopt unadulterated monocrystalline silicon, monocrystalline silicon, silicon-on-insulator (SOI) etc. doped with impurity.As example, in the present embodiment, Semiconductor substrate 100 selects single crystal silicon material to form.In Semiconductor substrate 100, be formed with isolation channel, buried regions, and various trap (well) structure, in order to simplify, omitted in diagram.
In described Semiconductor substrate 100, be formed with various elements, in order to simplify, in diagram, omitted, an insulating barrier 101 is only shown here, it typically is the material layer with low-k.In described insulating barrier 101, be formed with the groove for filling metal interconnecting wires.Deposit a metal level, for example copper metal layer, on described insulating barrier 101, and fills up the groove in described insulating barrier 101.Adopt chemical mechanical milling tech to remove unnecessary copper metal layer, the surface that is ground to described insulating barrier 101 stops, and in described insulating barrier 101, forms copper metal interconnecting wires 102.
Then, as shown in Figure 1B, on described insulating barrier 101 and copper metal interconnecting wires 102, form a silicon-rich silicon nitride layer 103.Adopt chemical vapor deposition method to form described silicon-rich silicon nitride layer 103, wherein, with silane (SiH
4) and ammonia (NH
3) as the precursor material that forms described silicon-rich silicon nitride layer 103.
The concrete technology parameter of described chemical vapor deposition method is as follows: pressure 1-7Torr, power 50-100W, SiH
4flow be 100-1000sccm, NH
3flow be 100-500sccm.The thickness of the described silicon-rich silicon nitride layer 103 that deposition forms is 30-150 dust.
Then, as shown in Figure 1 C, on described silicon-rich silicon nitride layer 103, form a thermal oxide layer 104.Adopt chemical vapor deposition method to form described thermal oxide layer 104, wherein, with tetraethoxysilane (TEOS) and ozone (O
3) as the precursor material that forms described thermal oxide layer 104.
The concrete technology parameter of described chemical vapor deposition method is as follows: pressure 1-7Torr, the flow of TEOS is 50-500sccm, O
3flow be 50-1000sccm.The thickness of the described thermal oxide layer 104 that deposition forms is 100-500 dust.
Then,, as shown in Fig. 1 D, on described thermal oxide layer 104, form the silicon carbide layer 105 of a doping nitrogen.Adopt chemical vapor deposition method to form the silicon carbide layer 105 of described doping nitrogen, wherein, use trimethyl silane (3MS) and ammonia (NH
3) as the precursor material of silicon carbide layer 105 that forms described doping nitrogen.
The concrete technology parameter of described chemical vapor deposition method is as follows: pressure 0.2-0.9Torr, the flow of 3MS is 100-1000sccm, NH
3flow be 100-1000sccm.The thickness of the silicon carbide layer 105 of the described doping nitrogen that deposition forms is 50-300 dust.
So far, whole processing steps that method is implemented are according to an exemplary embodiment of the present invention completed, formation has the copper metal diffusion barrier layer of new construction: described silicon-rich silicon nitride layer 103 and thermal oxide layer 104 form double-deck copper metal diffusion barrier layer, wherein, described silicon-rich silicon nitride layer also plays the effect of the oxygen diffusion stoping in described thermal oxide layer, and described thermal oxide layer can improve plasma-induced damage; The silicon carbide layer 105 of described doping nitrogen is as through hole etch stop layer, and described thermal oxide layer 104 also can play the effect of through hole etch-stop.Do not need the mode of using plasma deposition when forming power lower (50-100W) required when described silicon-rich silicon nitride layer and form described thermal oxide layer, thereby can reduce the damage to device of electric current that PID induction generates.
With reference to Fig. 2, wherein show copper metal diffusion barrier layer that employing that the present invention proposes has a new construction to improve the flow chart of method of plasma-induced damage (PID), for schematically illustrating the flow process of whole manufacturing process.
In step 201, Semiconductor substrate is provided, in described Semiconductor substrate, form insulating barrier, and form copper metal interconnecting wires in described insulating barrier;
In step 202, on described insulating barrier and copper metal interconnecting wires, form silicon-rich silicon nitride layer;
In step 203, on described silicon-rich silicon nitride layer, form thermal oxide layer;
In step 204, on described thermal oxide layer, form the silicon carbide layer of doping nitrogen.
The present invention is illustrated by above-described embodiment, but should be understood that, above-described embodiment is the object for giving an example and illustrating just, but not is intended to the present invention to be limited in described scope of embodiments.In addition it will be appreciated by persons skilled in the art that the present invention is not limited to above-described embodiment, can also make more kinds of variants and modifications according to instruction of the present invention, these variants and modifications all drop in the present invention's scope required for protection.Protection scope of the present invention is defined by the appended claims and equivalent scope thereof.
Claims (16)
1. a manufacture method for semiconductor device, comprising:
Semiconductor substrate is provided, in described Semiconductor substrate, forms an insulating barrier, and in described insulating barrier, form copper metal interconnecting wires;
On described insulating barrier and copper metal interconnecting wires, form silicon-rich silicon nitride layer;
On described silicon-rich silicon nitride layer, form thermal oxide layer, described thermal oxide layer and described silicon-rich silicon nitride layer form double-deck copper metal diffusion barrier layer, and the precursor material that forms described thermal oxide layer comprises tetraethoxysilane and ozone, to improve plasma-induced damage;
On described thermal oxide layer, form the silicon carbide layer of doping nitrogen.
2. method according to claim 1, is characterized in that, adopts chemical vapor deposition method to form described silicon-rich silicon nitride layer.
3. method according to claim 1 and 2, is characterized in that, the precursor material that forms described silicon-rich silicon nitride layer comprises silane and ammonia.
4. method according to claim 3, is characterized in that, the flow of described silane is 100-1000sccm.
5. method according to claim 3, is characterized in that, the flow of described ammonia is 100-500sccm.
6. method according to claim 2, is characterized in that, described chemical vapor deposition processes is at pressure 1-7Torr, under the condition of power 50-100W, carries out.
7. method according to claim 1 and 2, is characterized in that, the thickness of described silicon-rich silicon nitride layer is 30-150 dust.
8. method according to claim 1, is characterized in that, adopts chemical vapor deposition method to form described thermal oxide layer.
9. method according to claim 1, is characterized in that, the flow of described tetraethoxysilane is 50-500sccm.
10. method according to claim 1, is characterized in that, the flow of described ozone is 50-1000sccm.
11. methods according to claim 8, is characterized in that, described chemical vapor deposition processes is to carry out under the condition of pressure 1-7Torr.
12. according to the method described in claim 1 or 8, it is characterized in that, the thickness of described thermal oxide layer is 100-500 dust.
13. methods according to claim 1, is characterized in that, adopt chemical vapor deposition method to form the silicon carbide layer of described doping nitrogen.
14. according to the method described in claim 1 or 13, it is characterized in that, the thickness of the silicon carbide layer of described doping nitrogen is 50-300 dust.
15. methods according to claim 1, is characterized in that, the silicon carbide layer of described doping nitrogen forms through hole etch stop layer.
16. methods according to claim 1, is characterized in that, described insulating barrier is the material layer with low-k.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201110222354.7A CN102915952B (en) | 2011-08-04 | 2011-08-04 | Manufacturing method for semiconductor device |
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|---|---|---|---|
| CN201110222354.7A CN102915952B (en) | 2011-08-04 | 2011-08-04 | Manufacturing method for semiconductor device |
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|---|---|
| CN102915952A CN102915952A (en) | 2013-02-06 |
| CN102915952B true CN102915952B (en) | 2014-11-05 |
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Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9741557B1 (en) * | 2016-06-23 | 2017-08-22 | Texas Instruments Incorporated | Silicon nitride process for reduction of threshold shift |
| CN119822372A (en) * | 2024-09-09 | 2025-04-15 | 浙江大学 | Copper-doped silicon carbide composite material and preparation method and application thereof |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1672250A (en) * | 2002-01-15 | 2005-09-21 | 国际商业机器公司 | Double-layer HDPCVD/PE CVD cap layer in improved BEOL interconnection structure and its method |
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| KR100390951B1 (en) * | 1999-12-29 | 2003-07-10 | 주식회사 하이닉스반도체 | Method of forming copper wiring in a semiconductor device |
| US7122900B2 (en) * | 2000-06-26 | 2006-10-17 | Renesas Technology Corp. | Semiconductor device and method manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1672250A (en) * | 2002-01-15 | 2005-09-21 | 国际商业机器公司 | Double-layer HDPCVD/PE CVD cap layer in improved BEOL interconnection structure and its method |
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