CN102938417B - A kind of division grid-type power MOS (Metal Oxide Semiconductor) device with groove - Google Patents

Abstract

The present invention relates to MOS device domain edge designs field, be specifically related to a kind ofly be applied in the division grid-type power MOS (Metal Oxide Semiconductor) device with groove that in low, middle voltage device, groove structure is communicated with terminal structure.Division grid-type power MOS (Metal Oxide Semiconductor) device with groove of the present invention, in active area, groove structure is communicated with terminal structure, and the table top in active area is two ends is semicircular elongate configuration, and semicircular diameter is identical with mesa width.In the present invention, splitting bar power MOS (Metal Oxide Semiconductor) device with groove is groove circumscribe mesa structure, can ensure that the active region mesa of device is consistent like this, Electric Field Distribution in optimised devices in mesa structure, thus the puncture voltage improving division grid-type power MOS (Metal Oxide Semiconductor) device with groove on the whole.

Description

A Split Gate Trench Power MOS Device

technical field

The invention relates to the field of layout edge design of MOS devices, in particular to a split gate type trench power MOS device used in low and medium voltage devices in which the trench structure communicates with the terminal structure.

Background technique

In the 1990s, the main research direction of the development and industrialization technology of power trench MOS field effect transistor (PowerTrenchMOSFET) was mainly to minimize the forward conduction resistance (Ron) of low-voltage power devices. Today, the structure of power trench MOS devices is suitable for most power MOSFET applications, and the characteristics of the devices are constantly approaching the one-dimensional limit of silicon materials (expressing the characteristic on-resistance in the drift region of the device and the breakdown in the off-state Theoretical relationship of voltage). The proposal of the reduced surface electric field REducedSURfaceField (RESURF) technology can make power trench MOS devices with a breakdown voltage of 600V exceed the one-dimensional limit of silicon materials. Then, based on the working principle of RESURF, a split-gate trench (Split-GateTrench) MOSFET device structure appeared, which can exceed the one-dimensional limit of silicon materials at a low voltage of about 30V that is scaled down. Therefore, the split gate trench MOS device has a lower forward conduction resistance in the range of low and medium voltage (20~200V), which has obvious advantages.

However, there are still problems in the design of the edge of the current split-gate trench MOSFET device layout. It requires multiple processes and multiple photolithography plates to complete the structure, but it is still difficult to ensure the withstand voltage of the device terminal, which not only increases The manufacturing cost of the device is reduced, and the working reliability of the device is also reduced.

The US patent "PowerSemiconductorDevicesWithTrenchedShieldedSplitGateTransistorAndMethodsOfManufacture" with the publication number US8013391B2 discloses the cell structure design and device layout design of split gate trench power MOS devices (Figure 27 of the accompanying drawing of the US patent application specification). The design principle of the device layout edge is: when the trench in the active area is parallel to the terminal guard ring, the distance between them is equal to the width of the mesa in the cell; when the terminal guard ring is an arc, the trench in the active area is the same as the terminal guard ring. The shortest distance between the guard rings is half the width of the mesa in the cell. The problem with this device is that the device is prone to premature breakdown, and the breakdown point occurs at the closest position between the outermost cell and the terminal protection ring.

Contents of the invention

The object of the present invention is to provide a split-gate trench power MOS device which can effectively improve the breakdown voltage.

The purpose of the present invention is achieved like this:

For split gate trench power MOS devices, the trench structure in the active region is connected to the terminal structure, and the mesa in the active region is a long strip structure with semicircular ends, and the diameter of the semicircle is the same as the width of the mesa.

The terminal protection ring of the split-gate trench power MOS device and the cell structure of the split-gate trench power MOS device are on the same layer of photolithography.

The beneficial effects of the present invention are:

In the present invention, the split-gate trench power MOS device has a mesa structure surrounded by trenches, which can ensure that the mesa structure in the active region of the device is consistent, and optimize the electric field distribution in the mesa structure in the device, thereby improving the split-gate trench power MOS as a whole. The breakdown voltage of the device.

Description of drawings

FIG. 1 is a schematic diagram of an edge structure of a layout of a disclosed split-gate trench MOS power device;

Fig. 2 is the three-dimensional model corresponding to the A-A `area in Fig. 1;

Fig. 3 is a schematic diagram of the layout edge structure of the split-gate trench MOS power device disclosed by the present invention;

Figure 4 The three-dimensional model corresponding to the B-B` area in Figure 3;

C-C' cross-sectional schematic diagram in Fig. 5 Fig. 3;

Fig. 6 is a schematic diagram comparing the breakdown voltage simulation curves of the present invention and the structure of the existing invention;

Fig. 7 is a schematic diagram comparing the maximum electric field intensity distribution in the silicon body between the present invention and the prior invention;

Fig. 8 is a schematic diagram comparing the distribution of the maximum impact ionization rate in the silicon body between the present invention and the prior invention.

Detailed ways

The present invention will be further described below in conjunction with accompanying drawing:

The present invention proposes layout edge design of split-gate trench power MOS devices. The trench structure in the device cell is specially designed to communicate with the terminal structure, and the mesa structure in the active region is a long strip structure with equal diameters and semicircles at both ends. While not adding process steps and photolithographic plates, the process steps are saved, the breakdown voltage of the device is ensured, and the working reliability of the device is improved.

In the research of split-gate trench power MOS devices, it is found that when the trench depth is constant, the breakdown voltage of split-gate trench power MOS devices is mainly affected by the spacing of the trenches in the active region of the device. The traditional split-gate MOS device has a trench structure surrounded by mesas. At the corner of the device, the distance between the terminal trench and the trench in the active region varies greatly (as shown in Figure 1), which directly affects the flattening of the electric field distribution in the mesas. , thereby reducing the breakdown voltage of the split-gate trench MOS device. In the present invention, the split gate trench power MOS device has a trench surrounded by a mesa structure, which can ensure that the mesa structure in the active region of the device is consistent, optimize the electric field distribution in the mesa structure in the device, and thereby improve the power of the split gate trench as a whole. Breakdown voltage of MOS devices.

The design feature of the present invention is that the groove structure in the device cell is connected to the terminal structure, and the mesa structure in the active region is a long strip structure with equal diameter and semicircle at both ends, as shown in FIG. 3 .

The structure in FIG. 3 includes 301 terminal trench structure, 302 active region trench structure, 303 mesa structure, and 301 is connected with 302 . Taking C-C` as the section line, its cross-sectional schematic diagram is shown in Figure 5. It includes a gate extraction electrode 501 , a suspended polysilicon electrode 502 under the gate electrode, a thick oxide layer 503 , a gate electrode connection metal 504 , a source electrode 505 , a drift region (N-) 506 , and a drain electrode 507 .

Fig. 6 shows the comparison curves of the device structure breakdown voltage simulation of the present invention (C) and the existing invention (B). It can be seen from the figure that under the same vertical device structure parameters, the breakdown voltage of the structure of the present invention can reach 118V, while the breakdown voltage of the existing structure of the invention is 59V.

Fig. 7 shows the comparison of the maximum electric field distribution in the silicon body of the device structure of the present invention (C) and the prior invention (B). It can be seen from the figure that the electric field distribution in the device structure silicon body of the present invention (C) is uniform, and the electric field intensity gradually increases as it approaches thick oxygen; the existing invention (B) the electric field intensity distribution in the device structure silicon body has two peaks, As a result, the device breaks down prematurely under high voltage conditions.

Fig. 8 shows the comparison of the maximum impact ionization rate distribution in the silicon body of the device structure of the present invention (C) and the prior invention (B). It can be seen from the figure that the distribution of impact ionization rate in the drift region of the device structure silicon body in the present invention (C) is relatively uniform; the impact ionization rate in the existing invention (B) device structure silicon body is mainly concentrated in the PN junction where the device channel and the drift region are connected At , and the ionization rate is strong, the avalanche breakdown of the device occurs in advance.

Split gate trench power MOS device layout edge design terminal. It is characterized in that: the groove structure in the active area is connected with the terminal structure, the mesa structure in the active area is a long strip structure with equal diameter and semicircle at both ends, and the diameter of the semicircle at both ends is the same as the width of the mesa. The schematic diagram of the device structure for comparison and simulation is shown in Figure 4. The specific structural parameters are: the thickness of the sink bottom is 7.1 μm, the concentration of n-type impurities is 1.23×10 ¹⁶ /cm ³ ; the thickness of the channel region is 0.5 μm, and the concentration of p-type impurities is 1.2 ×10 ¹⁷ /cm ³ ; the N+ source region is 0.3μm, the impurity concentration is 1.0×10 ²⁰ /cm ³ ; the trench depth is 7.4μm, the thickness of the thick oxide is 0.8μm, and the thickness of the gate oxide is The distance between the cells is 5.6 μm, and the width of the mesa is 1.3 μm; the diameter of the semicircle at the contact between the cells and the terminal protection ring is 1.3 μm.

The above are specific examples of the present invention and are not intended to limit the present invention. The layout edge design of the split gate type trench power MOS device provided by the invention is also applicable to common super junction structure devices and their variants. Without departing from the essence and scope of the present invention, some adjustments and optimizations can be made, and the protection scope of the present invention shall prevail in the claims.

Claims (1)

1. divide a grid-type power MOS (Metal Oxide Semiconductor) device with groove, it is characterized in that: in active area, groove structure is communicated with terminal structure, the table top in active area is two ends is semicircular elongate configuration, and semicircular diameter is identical with mesa width; The terminal protection ring of described division grid-type power MOS (Metal Oxide Semiconductor) device with groove and the structure cell of division grid-type power MOS (Metal Oxide Semiconductor) device with groove are at same layer photolithography plate; Substrate thickness 7.1 μm, N-shaped impurity concentration is 1.23 × 10 ¹⁶/ cm ³; Channel region thickness is 0.5 μm, and p-type impurity concentration is 1.2 × 10 ¹⁷/ cm ³; N+ source region is 0.3 μm, and impurity concentration is 1.0 × 10 ²⁰/ cm ³; Gash depth is 7.4 μm, and wherein thick oxygen thickness is 0.8 μm, and gate oxide thickness is distance between cells is 5.6 μm, and mesa width is 1.3 μm; Cellular is 1.3 μm with terminal protection articulating synapsis semicircle diameter.