CN102931978B - Phase adjusting apparatus with and relevant gate generator and adjust the method for phase place - Google Patents

Abstract

The invention relates to a phase adjustment device, a related clock pulse generator and a related method for providing a clock signal to a core circuit. The core circuit is powered by a core voltage. The phase adjustment device includes two clock pulse receiving ends, several digital receiving ends, and a synthesis circuit. The two clock pulse receivers receive two original clock pulse signals. The two original clock signals have substantially the same frequency but different phases. These digital receivers receive several phase selection signals. The synthesizing circuit is powered by a first voltage lower than the core voltage, and is used for generating the clock signal according to the phase control signals and the two original clock signals.

Description

Phase adjusting device and its related clock pulse generator and method for adjusting phase

technical field

The invention relates to a phase adjustment device, a clock pulse generator and a method for adjusting the phase of the clock pulse.

Contemporary television or communication products all need to extract the transmitted signal from the carrier. Therefore, the receiving end needs to generate a very accurate local oscillator signal or clock pulse signal to demodulate the carrier. Not only must the frequency of the clock signal be accurate, but the phase of the clock signal must also be accurate.

As known in the industry, a phase-locked loop (PLL) can generate an original clock signal whose frequency is about the same as a reference signal. However, the phase in the original clock signal may be different from the actual required phase. To obtain a clock pulse signal with accurate phase and frequency, it may be necessary to adjust the phase of the original clock pulse signal.

Contents of the invention

The embodiment of the present invention discloses a phase adjustment device for providing a clock signal to a core circuit. The core circuit is powered by a core voltage. The phase adjusting device includes two clock pulse receiving ends, several digital receiving ends and a synthesizing circuit. The two clock pulse receivers receive two original clock pulse signals. The two original clock signals have substantially the same frequency but different phases. These digital receivers receive several phase selection signals. The synthesizing circuit is powered by a first voltage lower than the core voltage, and is used for generating the clock signal according to the phase control signals and the two original clock signals.

The embodiment of the invention discloses a clock pulse generator. The clock pulse generator includes a phase-locked loop and a phase adjustment device. The PLL has a voltage controlled oscillator and a loop filter. The VCO generates two original clock pulse signals with the same frequency but different phases. The loop filter generates a control voltage for controlling the frequency of the two original clock signals. The phase adjusting device is powered by a first voltage, and is used for generating a clock pulse signal according to a ratio and the two original clock pulse signals. The clock signal is provided to a core circuit. The core circuit is powered by a core voltage. The first voltage is lower than the core voltage.

The embodiment of the present invention discloses a method for adjusting phase, which is used to provide a clock signal to a core circuit, and the core circuit is powered by a core voltage. The method includes: synthesizing a clock signal according to two original clock signals and a ratio. The two original clock signals have substantially the same frequency but different phases. The signal swing of the clock signal is smaller than the core voltage.

Description of drawings

Figure 1 shows an operating system.

FIG. 2A illustrates the phase adjustment device in FIG. 1 .

FIG. 2B shows a driving circuit in FIG. 2A.

3A and 3B respectively show the relationship between the clock signal Clk ₀ and the signals S _m and S _m+1 in FIG. 2A under two different clock frequencies.

Figure 4 shows another operating system.

FIG. 5 illustrates the phase adjustment device in FIG. 4 .

FIG. 6A and FIG. 6B respectively show the relationship between the clock signal Clk ₀ and the signals T _m and T _m+1 at two different clock frequencies.

Figure 7 and Figure 8 show another two operating systems.

Explanation of main component symbols

10, 10 _a , 10 _b , 10 _c clock pulse generator

11 PLL

12 core circuits

14 phase detectors

16 charge pump

18 loop filter

20 voltage buffer

22 Voltage Controlled Oscillators

24 frequency divider

28, 28a phase adjustment device

30, 30 _a , 32, 32 _a driving circuit

60, 62 voltage buffer

66 amplifiers

Clk ₀ clock pulse signal

Clk ₁ -Clk _K , Clk _m , Clk _m+1 original clock pulse signal

Clk _adj clock pulse signal

Clock pulse after Clk _DIV frequency division

Clk _REF reference signal

D ₁ -D _N drive unit

P ₁ -P _N phase selection signal

S _m , S _m+1 , T _m , T _m+1 signals

SW ₁ -SW _N switch

V _CORE core voltage

V _CORE1 core voltage

V _CORE2 core voltage

V _CTL control voltage

V _RNG regulation voltage

V _SPLY supply voltage

detailed description

FIG. 1 shows an operating system with a clock generator 10 and a core circuit 12 . The clock generator 10 has a phase adjustment device 28 . The clock generator 10 also includes a phase locked loop (PLL) 11 . The phase locked loop 11 includes a phase detector (phase detector) 14 receiving a reference signal Clk _REF , a charge pump (chargepump) 16, a loop filter (loop filter) 18, a voltage buffer (voltage buffer) 20, a control voltage control An oscillator (voltage-controlled oscillator, VCO) 22 and a frequency divider 24 .

Wherein, a phase detector (phase detector) 14 compares the phase difference between the reference signal Clk _REF and the frequency-divided clock pulse Clk _DIV to drive a charge pump (chargepump) 16 . The current drawn or drawn by the charge pump 16 passes through a loop filter 18 to form a control voltage V _CTL . As shown in FIG. 1 , the control voltage V _CTL passes through a voltage buffer (voltage buffer) 20 to become the regulation voltage V _RNG , or the control voltage V _CTL can also be directly used as a control voltage-controlled oscillator (VCO) 22 The regulating voltage V _RNG is used to control the frequency of multiple original clock pulse signals Clk ₁ -Clk _K generated by the VCO22. The original clock signals Clk ₁ -Clk _K have the same frequency but different phases. One of the original clock signals Clk ₁ -Clk _K can be frequency-divided by the frequency divider 24 to generate a frequency-divided clock pulse Clk _DIV to feed back to the phase detector 14 .

The phase adjustment device 28 receives the above-mentioned original clock pulse signals Clk ₁ -Clk _K . In addition, the phase adjustment device 28 also receives phase selection signals P ₁ -P _N . The digital phase selection signals P ₁ -P _N can control the phase adjusting device 28 to synthesize part of the original clock pulse signals to generate a clock pulse signal Clk ₀ . The clock pulse signal Clk ₀ is sent to the core circuit 12 as its timing control. The core voltage V _CORE1 and the core voltage V _CORE2 supply power to the core circuit 12 and the phase adjustment device 28 respectively. Wherein, the core voltage V _CORE1 may be equal to the core voltage V _CORE2 .

Take the phase adjusting device 28 shown in FIG. 2A as an example. The phase adjusting device 28 also includes two driving circuits 30 , 32 . The phase adjustment device 28 can use an interpolation method to synthesize a clock signal Clk ₀ from two original clock signals Clk _m , Clk _m+1 . The phase adjustment device 28 includes a synthesizing circuit, which adjusts the respective proportions of the original clock signals Clk _m , Clk _m+1 to generate the clock signal Clk ₀ . Specifically, the phase selection signals P ₁ -P _N are used to determine the driving forces of the two driving circuits 30 and 32, and the phase adjustment device 28 further adjusts the original clock pulse signals Clk _m , The respective proportions of Clk _m+1 are used to generate the clock pulse signal Clk ₀ . For example, if the driving force ratio of the driving circuits 30 and 32 is determined to be 5:5 by the current phase selection signals _{P 1} -PN, the respective proportions of the original clock pulse signals Clk _m and Clk _m+1 are 5:5; in this way, the phase of the clock signal Clk ₀ is approximately in the middle of the two phases of the original clock signals Clk _m and Clk _m+1 .

FIG. 2B shows the driving circuit 30 in FIG. 2A. The driving circuit 30 has the same driving cells D ₁ -D _N , and each driving cell has a unit driving force. The switches SW ₁ -SW _N are controlled by the phase selection signals P ₁ -P _N , and each determines whether a corresponding driving unit drives the clock signal Clk ₀ . For example, if the phase selection signals P ₁ -P _N short-circuit the switches SW ₁ -SW ₃ while the other switches in FIG. 2B are open, the current driving force of the driving circuit 30 is 3 units. The driving circuit 31 may have a circuit similar to that of the driving circuit 30 , which will not be repeated here.

The relationship between the clock signal Clk ₀ and the signals S _m and S _m+1 in FIG. 2A will be shown in FIG. 3A and FIG. 3B , respectively, under two different clock frequencies. The signal S _m represents the waveform of the clock pulse signal Clk ₀ when the driving force ratio of the driving circuits 30 and 32 is 10:0, which roughly corresponds to the original clock pulse signal Clk _m ; the signal S _m+1 represents the driving force of the driving circuits 30 and 32 When the driving force ratio is 0:10, the waveform of the clock pulse signal Clk ₀ roughly corresponds to the original clock pulse signal Clk _m+1 . The swings of the signals S _m and S _m+1 are determined by the power supply, and are approximately the core voltage V _CORE2 .

It can be seen from FIG. 3A that the clock signal Clk ₀ is synthesized by approximately 50% of S _m and 50% of S _m+1 . Although the clock pulse signal Clk ₀ is not rail-to-rail, the phase of the clock pulse signal Clk ₀ is indeed approximately in the middle of the two phases of the signals S _m and S _m+1 , that is, approximately between the original clock signal Clk _m and Clk The middle of _m+1 .

FIG. 3B also shows that the clock signal Clk ₀ is synthesized by approximately 50% of S _m and 50% of S _m+1 , but the frequencies of the signals S _m and S _m+1 are relatively low. It can be seen from Figure 3B that because the signals S _m and S _m+1 will have high flat tops and low flat valleys, the potential of the clock pulse signal Clk ₀ is maintained at a constant value in the middle for a period of time, which will make the clock pulse signal Clk A phase of ₀ is difficult to discern or use. Therefore, the phase adjustment device 28 often needs to be adjusted for different clock pulse frequencies, so as to avoid the situation in FIG. 3B from occurring.

FIG. 4 shows another operating system of the embodiment of the present invention, which has a clock pulse generator 10 _a and a core circuit 12 . The main difference between the _{clock pulse generator 10a} in FIG. 4 and the clock pulse _generator 10 in FIG. As low as a ratio, the ratio must be such that the slope of the change of the signals T _m and T _m+1 is low enough to have a specific characteristic, as described in detail below. There is an amplifier 66 in the core circuit 12 to amplify the clock pulse signal Clk ₀ to generate a rail-to-rail clock pulse signal Clk _adj , the signal swing of which is the core voltage V _CORE .

Take the phase adjustment device 28 _a shown in FIG. 5 as an embodiment of the present invention. The operation mode of the phase adjustment device 28a is very similar to the aforementioned phase adjustment device 28, and also uses interpolation to synthesize the two original clock pulse signals Clk _m and Clk m _{+ 1} received from the two clock pulse receiving ends Clock pulse signal Clk ₀ . It also uses the phase selection signals _{P 1} -PN received from the digital receiving end to determine a ratio between the driving forces of the two driving circuits 30 _a and 32 _a . For example, if the driving force ratio of the driving circuits 30 _a and 32 _a is determined to be 5:5 by the current phase selection signals P ₁ -P _N , then the phase of the clock signal Clk ₀ will be approximately at the original clock pulse The middle of the two phases of the signals Clk _m and Clk _m+1 . If the phase selection signals _{P 1} -PN determine that the ratio is 7:3, the phase of the clock signal Clk ₀ will be closer to the original clock signal Clk _m .

FIG. 6A and FIG. 6B respectively show the relationship between the clock signal Clk ₀ and the signals T _m and T _m+1 in FIG. 5 under two different clock frequencies. Similar to the signals S _m and S _m+1 in FIG. 3A and FIG. 3B , the signal T _m represents the waveform of the clock pulse signal Clk ₀ when the driving force ratio of the driving circuits 30 _a and 32 _a is 10:0, which roughly corresponds to The original clock pulse signal Clk _m ; the signal T _m+1 represents the waveform of the clock pulse signal Clk ₀ when the driving force ratio of the driving circuits 30 _a and 32 _a is 0:10, which roughly corresponds to the original clock pulse signal Clk _m+1 . It should be noted that since the phase adjustment device 28 _a is powered by the regulation voltage _VRNG , the swings of the signals T _m and T _m+1 are approximately equal to the regulation voltage _VRNG . Therefore, the swing of the clock pulse signal Clk ₀ will not be greater than the regulation voltage _VRNG .

It can be seen from FIG. 6A that the clock signal Clk ₀ is synthesized by approximately 50% of T _m and 50% of T _m+1 . In other words, the phase of the clock signal Clk ₀ is approximately in the middle of the two phases of the clock signals Clk _m and Clk _m+1 . The waveforms of the clock pulse signal Clk ₀ in FIG. 6A and FIG. 3A are not significantly different except for the swing amplitude. However, comparing the waveforms of the clock signal Clk ₀ in FIG. 6B with that in FIG. 3B , there are obvious differences.

FIG. 6B also shows that the clock signal Clk ₀ is synthesized by approximately 50% of T _m and 50% of T _m+1 , but the frequencies of the signals T _m and T _m+1 are relatively low. Comparing FIG. 6B with FIG. 3B , the difference is that the clock signal Clk ₀ in FIG. 6B does not stay in the middle ground, so its phase is easier to identify or use. One of the reasons is analyzed as follows. As mentioned above, the phase adjustment device _28a is powered by the regulating voltage _VRNG . Compared with the core voltage V _CORE which is independent of the original clock pulse signals Clk _m , Clk _m+1 , the regulating voltage V _RNG has a characteristic of decreasing as the frequency of the original clock pulse signals Clk _m , Clk _m+1 decreases. Accordingly, the reduced regulating voltage V _RNG makes the driving forces of the driving circuits 30 _a and 32 _a smaller, and the slopes of the signals T _m and T _m+1 are relatively smaller (compared to FIG. 6A ), so the signal T _m and T _m+1 are less prone to high peaks and low valleys like the signals S _m and S _m+1 . Therefore, the clock pulse signal Clk ₀ synthesized from the signals T _m and T _m+1 will not stay in the middle ground.

In Fig. 4, the phase adjustment device _28a is directly powered by the regulating voltage V _RNG , and utilizes the characteristic that the regulating voltage _VRNG decreases as the frequencies of the original clock pulse signals Clk _m and Clk _m+1 decrease, thereby avoiding the clock pulse In the waveform of the signal Clk ₀ , the potential stays at a constant value in the middle. However, directly supplying power from the regulating voltage _VRNG is not a necessary feature of the present invention, and is only an embodiment. In order to describe the spirit of the present invention in detail, please refer to FIG. 7 and FIG. 8 . FIG. 7 shows another operating system, wherein a voltage buffer 60 generates a supply voltage V _SPLY according to the regulation voltage _VRNG to supply power to the phase adjustment device 28 _a . FIG. 8 shows another operating system, wherein a voltage buffer 62 generates a supply voltage V _SPLY according to the control voltage V _CTL output by the loop filter 18 to supply power to the phase adjusting device 28 _a . The power supply voltage V _SPLY is preferably not greater than the power supply voltage V _CORE of the core circuit 12 . In summary, there is a positive correlation among the control voltage V _CTL , the regulation voltage V _RNG , and the power supply voltage V _SPLY . The control voltage V _CTL becomes higher, and the regulation voltage V _RNG and the power supply voltage V _SPLY become higher. In other words, the spirit of the present invention is to supply power to the phase adjustment device 28 _a through a voltage linked to the frequency of the original clock pulse signal Clk _m , Clk _m+1 , or a voltage lower than the power supply voltage V _CORE , thereby avoiding the clock In the waveform of the pulse signal Clk ₀ , the potential stays at a constant value in the middle. In one embodiment, the control voltage V _CTL : the regulation voltage V _RNG : the power supply voltage V _SPLY is equal to 1:1:1. In another embodiment, the voltage values of the control voltage V _CTL , the regulation voltage V _RNG , and the power supply voltage V _SPLY are not equal to each other.

The above descriptions are only preferred embodiments of the present invention, and all equivalent changes and modifications made according to the scope of the patent application of the present invention shall fall within the scope of the present invention.

Claims (7)

1. a phase adjusting apparatus, in order to clock pulse signal to core circuit to be provided, this core circuit is with a corePower voltage supply, this phase adjusting apparatus includes:

Two clock pulses receiving terminals, receive two original clock pulse signals, and it is identical that this two original clocks pulse signal has essenceFrequency, not identical phase place;

Multiple digital receiving terminals, receive multiple Selecting phasing signals; And

One combiner circuit, comprises two drive circuits, in order to according to these these two drive circuits of Selecting phasing signal decidingDriving force, and it is shared respectively to adjust these two original clock pulse signals according to a driving force ratio of these two drive circuitsProportion, produces this clock pulse signal;

Wherein, this combiner circuit is by one first power voltage supply, and this first voltage is lower than this core voltage; This two original clocks pulseSignal frequency controlled in a regulation and control voltage, this first voltage is relevant to this regulation and control voltage.

2. phase adjusting apparatus as claimed in claim 1, is characterized in that, this first voltage equals this regulation and control voltage.

3. phase adjusting apparatus as claimed in claim 1, is characterized in that, separately includes:

One voltage buffer, according to this regulation and control voltage, provides this first voltage.

4. phase adjusting apparatus as claimed in claim 1, is characterized in that, is coupled to a phase-locked loop, and this phase-locked loop is usedSo that this first voltage and this two original clocks pulse signal to be provided, include:

One loop filter, in order to a control voltage to be provided, wherein, this first voltage produces according to this control voltage;

One voltage buffer, in order to receive this control voltage and to produce a regulation and control voltage; And

One voltage-controlled oscillator, in order to receive this regulation and control voltage and to produce this two original clocks pulse signal, wherein, these regulation and controlThe frequency of this two original clocks pulse signal of Control of Voltage.

5. a gate generator, includes:

One phase-locked loop, includes:

One loop filter, in order to produce a control voltage; And

One voltage-controlled oscillator, identical in order to produce frequency according to this control voltage, but two different original clock arteries and veins of phase placeRush signal; And

One phase adjusting apparatus, by one first power voltage supply, comprises two drive circuits, in order to the several Selecting phasing signals of foundationDetermine the driving force of these two drive circuits, and adjust these two when original according to a driving force ratio of these two drive circuitsThe proportion that clock signal is shared, produces a clock pulse signal;

Wherein, this clock pulse signal provides to a core circuit, and this core circuit powered by a core voltage, this first electricityForce down in this core voltage; This first voltage is relevant to this control voltage.

6. adjust a method for phase place, in order to clock pulse signal to core circuit to be provided, this core circuit is with a coreHeart power voltage supply, the method includes:

Utilize voltage-controlled oscillating to produce two original clock pulse signals according to a control voltage;

According to this control voltage, produce one first voltage; One combiner circuit is provided, two drive circuits of this combiner circuit, this closesBecome the driving force of circuit according to several these two drive circuits of Selecting phasing signal deciding, and driving according to these two drive circuitsPower ratio is adjusted this two shared proportions of original clock pulse signals difference, synthetic this clock pulse signal, and these two are formerBeginning clock pulse signal has frequency and the phase different phase that essence is identical; Wherein, a signal swing of this clock pulse signal is littleIn this core voltage;

With this first voltage, to this combiner circuit power supply; Wherein, this first voltage is less than this core voltage.

7. the method for adjustment phase place as claimed in claim 6, is characterized in that, separately includes:

Amplify this clock pulse signal, to produce clock pulse signal after an amplification, a letter of clock pulse signal after this amplificationNumber amplitude of oscillation equals this core voltage.