CN102957427A - Bit synchronization correction method for multilevel parallel analog-digital converter - Google Patents

Abstract

The invention discloses a bit synchronization correction method for a multilevel parallel analog-digital converter. The method includes the steps of connecting differential output of a folding circuit to comparators to generate a synchronization correction signal determining correction range; and subjecting output of a coarse conversion module to n-bit synchronization correction according to output of a fine conversion module and the synchronization correction signal. The method is simple in logic, the correction range is definable, error correction and bit synchronization can be achieved in wide range, the number of the comparators is decreased, and power consumption is lowered.

Description

The bit synchronization bearing calibration of multistage parallel analog to digital converter

Technical field

The present invention relates to integrated circuit fields, in particular to a kind of bit synchronization bearing calibration of multistage parallel analog to digital converter.

Background technology

At present, high-speed AD converter is widely used in the fields such as wireless telecommunication system, Digital Television, liquid crystal display drive circuit and hard drive circuit.Wherein, the flash-type analog to digital converter is that speed is the highest, but along with the raising of resolution, the number of comparator is exponential growth, causes power consumption very high.The multistage parallel analog to digital converter is divided into thickness conversion two parts to analog-to-digital conversion, thereby the number that has reduced widely comparator lowers power consumption, and thin modular converter and thick modular converter are in parallel working method, so the speed of multistage parallel analog to digital converter is suitable with the flash-type analog to digital converter.

Because the thin modular converter in the multistage parallel analog to digital converter and thick modular converter are in parallel working method, so that have stationary problem between the thickness modular converter.Any little time tranfer delay or not mating all of offset voltage, may cause the nonlinearity erron that whole analog to digital converter is large between the thickness modular converter, as shown in Figure 1.Finish synchronous correction so in encoder, need to increase extra circuit, therefore need extra synchronous correction module.

Proofread and correct as example take a bit synchronization, under the ideal state switching levels of the MSB position of thick modular converter just in time and the highest order LSB switching levels of thin modular converter coincide, therefore can judge and proofreaies and correct MSB and export by LSB, as shown in Figure 2.Specific implementation is to be made of two comparators, and reference level Ref_L and Ref_H have defined correcting range.Two comparator outputs are respectively sync_H and sync_L, and in this correcting range, MSB is decided by LSB, that is:

$\mathrm{MSB}=\stackrel{\‾}{\mathrm{LSB}}---\left(1\right)$

In other scope, MSB is still decided by oneself.Therefore, only need to carry out certain logical combination to sync_H, sync_L and LSB and just can obtain MSB after synchronous correction.

Usually, more employing one bit synchronization of the multistage parallel analog to digital converter of low resolution (4～6) is proofreaied and correct.And when resolution higher (7～10), then need the synchronous correction of multidigit, need a plurality of correcting ranges of definition, therefore need more comparator, and the index rising with the increase of synchronous correction bit number of required comparator number, cause the power consumption of synchronous correction module larger.

Summary of the invention

The invention provides a kind of bit synchronization bearing calibration of multistage parallel analog to digital converter, in order to reduce the power consumption of synchronous correction module.

For achieving the above object, the invention provides a kind of bit synchronization bearing calibration of multistage parallel analog to digital converter, it may further comprise the steps:

Difference output by folding electric circuit connects comparator, generates the synchronous correction signal of determining correcting range;

According to the output of synchronous correction signal and thin modular converter the n bit synchronization being carried out in the output of thick modular converter proofreaies and correct:

$\mathrm{MSB}\left(m\right)=\mathrm{<figure-callout\; id="1"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}1\&CenterDot;\mathrm{LSB}+\mathrm{<figure-callout\; id="2"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}2\&CenterDot;\mathrm{LSB}+\&CenterDot;\&CenterDot;\&CenterDot;+\mathrm{sync}(m-1)\&CenterDot;\mathrm{LSB}+\mathrm{sync}\left(m\right)\&CenterDot;\stackrel{\&OverBar;}{\mathrm{LSB}}$

$+\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}1}\&CenterDot;\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="2"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}2}\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\stackrel{\&OverBar;}{\mathrm{sync}\left(m\right)}\&CenterDot;\mathrm{MSB}{\left(m\right)}^{\&prime;}$

Wherein, do not exported by the m position binary code before the synchronous correction in the thick modular converter of MSB (m) ' expression, m the synchronous correction signal that sync (m) expression folding electric circuit produces, the high-order output in m position that the thick modular converter of MSB (m) expression is final, m, n are natural number, and 1≤m≤n.

The n bit synchronization correcting logic of above-described embodiment is simple, and correcting range can define, and can realize error correction and the bit synchronization of wide region, and the synchronous correction logic realizes all can with static circuit or dynamic circuit.

For the synchronous correction of n position, the synchronization correction method of traditional usage comparison device definition correcting range, synchronous correction module and thick modular converter need 3 (2 at least ⁿ-1) individual comparator, and adopt in the present embodiment the synchronization correction method of folders definition correcting range only to need 2n comparator.Therefore, the way of the synchronous correction of present embodiment has reduced the number of employed comparator, thereby reduces power consumption.

Description of drawings

In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, the below will do to introduce simply to the accompanying drawing of required use in embodiment or the description of the Prior Art, apparently, accompanying drawing in the following describes only is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain according to these accompanying drawings other accompanying drawing.

Fig. 1 is that thickness is changed nonsynchronous schematic diagram in the correlation technique;

Fig. 2 is traditional synchronous correction schematic diagram;

Fig. 3 is the folding electric circuit connection layout of one embodiment of the invention;

Fig. 4 is the bit synchronization bearing calibration flow chart of the multistage parallel analog to digital converter of one embodiment of the invention;

Fig. 5 is the realization schematic diagram of the two bit synchronization correcting logics of one embodiment of the invention;

Fig. 6 is the realization schematic diagram of the three bit synchronization correcting logics of one embodiment of the invention.

Embodiment

Below in conjunction with the accompanying drawing in the embodiment of the invention, the technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment only is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not paying the every other embodiment that obtains under the creative work prerequisite.

Fig. 3 is the folding electric circuit schematic diagram of one embodiment of the invention.The difference output of as shown in Figure 3 folding electric circuit is connected comparator, just can obtain the numeral output that changes with input signal, like this, the function of folding electric circuit is further expanded, and can utilize folding electric circuit to generate the synchronous correction signal of definite correcting range.

Fig. 4 is the bit synchronization bearing calibration flow chart of the multistage parallel analog to digital converter of one embodiment of the invention; As shown in Figure 4, this bit synchronization bearing calibration may further comprise the steps:

S102, the difference output connection comparator by folding electric circuit generates the synchronous correction signal of determining correcting range;

S104, carry out the n bit synchronization according to the output of described synchronous correction signal and thin modular converter to the output of thick modular converter and proofread and correct:

$\mathrm{MSB}\left(m\right)=\mathrm{<figure-callout\; id="1"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}1\&CenterDot;\mathrm{LSB}+\mathrm{<figure-callout\; id="2"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}2\&CenterDot;\mathrm{LSB}+\&CenterDot;\&CenterDot;\&CenterDot;+\mathrm{sync}(m-1)\&CenterDot;\mathrm{LSB}+\mathrm{sync}\left(m\right)\&CenterDot;\stackrel{\&OverBar;}{\mathrm{LSB}}$ (2)

$+\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}1}\&CenterDot;\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="2"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}2}\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\stackrel{\&OverBar;}{\mathrm{sync}\left(m\right)}\&CenterDot;\mathrm{MSB}{\left(m\right)}^{\&prime;}$

Wherein, do not exported by the m position binary code before the synchronous correction in the thick modular converter of MSB (m) ' expression, m the synchronous correction signal that the described folding electric circuit of sync (m) expression produces, the high-order output in m position that the described thick modular converter of MSB (m) expression is final, m, n are natural number, and 1≤m≤n.

The n bit synchronization correcting logic of present embodiment is simple, and correcting range can define, and can realize error correction and the bit synchronization of wide region, and the synchronous correction logic realizes all can with static circuit or dynamic circuit.

For the synchronous correction of n position, the synchronization correction method of traditional usage comparison device definition correcting range, synchronous correction module and thick modular converter need 3 (2 at least ⁿ-1) individual comparator, and adopt in the present embodiment the synchronization correction method of folders definition correcting range only to need 2n comparator.Therefore, the way of the synchronous correction of present embodiment has reduced the number of employed comparator, thereby reduces power consumption.

The below proofreaies and correct as example take two bit synchronizations, and the synchronous correction logic of utilizing folding electric circuit to finish is described, the multidigit synchronous correction is similar with it.

Fig. 5 is the two bit synchronization correcting logic schematic diagrames of one embodiment of the invention.As shown in Figure 5, sync1 and sync2 are the bit synchronization correction signals that produces with folding electric circuit, are used for defining the regional extent that needs bit synchronization to proofread and correct, and are regional A and B as shown in Figure 5.Wherein, MSB1 ' and MSB2 ' are not exported by the binary code before the synchronous correction in the thick modular converter, and it is directly generated behind comparator by the difference output of folders.LSB comes synchronous correction MSB1 ' and MSB2 ' from thin modular converter with LSB.

At regional A, sync1 is effective, and thick final output MSB1 and the MSB2 of modular converter determined by LSB:

$\mathrm{<figure-callout\; id="1"\; label="MSB"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">MSB</figure-callout>}1=\stackrel{\&OverBar;}{\mathrm{LSB}}---\left(3\right)$

MSB2＝LSB (4)

At regional B, sync2 is effective, and the MSB2 in the thick modular converter is also determined by LSB:

$\mathrm{<figure-callout\; id="2"\; label="MSB"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">MSB</figure-callout>}2=\stackrel{\&OverBar;}{\mathrm{LSB}}---\left(5\right)$

In sum, the thick conversion output after proofreading and correct through bit synchronization can be by following relational implementation:

$\mathrm{<figure-callout\; id="1"\; label="MSB"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">MSB</figure-callout>}1=\mathrm{<figure-callout\; id="1"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}1\&CenterDot;\stackrel{\&OverBar;}{\mathrm{LSB}}+\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}1}\&CenterDot;{\mathrm{MSB}1}^{\&prime;}---\left(6\right)$

$\mathrm{<figure-callout\; id="2"\; label="MSB"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">MSB</figure-callout>}2=\mathrm{<figure-callout\; id="1"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}1\&CenterDot;\mathrm{LSB}+\mathrm{<figure-callout\; id="2"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}2\&CenterDot;\stackrel{\&OverBar;}{\mathrm{LSB}}+\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}1}\&CenterDot;\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="2"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}2}\&CenterDot;{\mathrm{MSB}2}^{\&prime;}---\left(7\right)$

For three synchronous correction, its principle as shown in Figure 6, sync1, sync2 and sync3 are the bit synchronization correction signals that produces with folding electric circuit, are used for defining the regional extent that needs bit synchronization to proofread and correct, and are regional A, B and C as shown in the figure.Wherein, MSB1 ', MSB2 ' and MSB3 ' are not exported by the binary code before the synchronous correction in the thick modular converter, and it is directly generated behind comparator by the difference output of folders.LSB comes synchronous correction MSB1 ', MSB2 ' and MSB3 ' from thin modular converter with LSB.Final high position output can represent with following three formulas:

$\mathrm{<figure-callout\; id="1"\; label="MSB"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">MSB</figure-callout>}1=\mathrm{<figure-callout\; id="1"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}1\&CenterDot;\stackrel{\&OverBar;}{{\mathrm{LSB}}^{\&prime;}}+\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}1}\&CenterDot;{\mathrm{MSB}1}^{\&prime;}---\left(8\right)$

$\mathrm{<figure-callout\; id="2"\; label="MSB"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">MSB</figure-callout>}2=\mathrm{<figure-callout\; id="2"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}2\&CenterDot;\mathrm{LSB}+\mathrm{<figure-callout\; id="2"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}2\&CenterDot;\stackrel{\&OverBar;}{\mathrm{LSB}}+\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}1}\&CenterDot;\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="2"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}2}\&CenterDot;{\mathrm{MSB}2}^{\&prime;}---\left(9\right)$

$\mathrm{MSB}3=\mathrm{<figure-callout\; id="1"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}1\&CenterDot;\mathrm{LSB}+\mathrm{<figure-callout\; id="2"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}2\&CenterDot;\mathrm{LSB}+\mathrm{sync}3\&CenterDot;\stackrel{\&OverBar;}{\mathrm{LSB}}$

$+\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="1"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}1}\&CenterDot;\stackrel{\&OverBar;}{\mathrm{<figure-callout\; id="2"\; label="sync"\; filenames="HDA0000084314720000032.png"\; state="\{\{state\}\}">sync</figure-callout>}2}\&CenterDot;\stackrel{\&OverBar;}{\mathrm{sync}3}\&CenterDot;{\mathrm{mSB}3}^{\&prime;}---\left(10\right)$

Can find out that from the description of above-described embodiment bit synchronization bearing calibration of the present invention can expand to the synchronous correction of any position, logic is simple, and correcting range can define, and can realize error correction and the bit synchronization of relative broad range; Compared with prior art reduce the use number of comparator, thereby can reduce power consumption.

One of ordinary skill in the art will appreciate that: accompanying drawing is the schematic diagram of an embodiment, and the module in the accompanying drawing or flow process might not be that enforcement the present invention is necessary.

One of ordinary skill in the art will appreciate that: the module in the device among the embodiment can be described according to embodiment and be distributed in the device of embodiment, also can carry out respective change and be arranged in the one or more devices that are different from present embodiment.The module of above-described embodiment can be merged into a module, also can further split into a plurality of submodules.

One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be finished by the relevant hardware of program command, aforesaid program can be stored in the computer read/write memory medium, this program is carried out the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: the various media that can be program code stored such as ROM, RAM, magnetic disc or CD.

It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that previous embodiment is put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of embodiment of the invention technical scheme.

Claims (3)

1. the bit synchronization bearing calibration of a multistage parallel analog to digital converter is characterized in that, may further comprise the steps:

Difference output by folding electric circuit connects comparator, generates the synchronous correction signal of determining correcting range;

According to the output of described synchronous correction signal and thin modular converter the n bit synchronization being carried out in the output of thick modular converter proofreaies and correct:

$\mathrm{MSB}\left(m\right)=\mathrm{sync}1\&CenterDot;\mathrm{LSB}+\mathrm{sync}2\&CenterDot;\mathrm{LSB}+\&CenterDot;\&CenterDot;\&CenterDot;+\mathrm{sync}(m-1)\&CenterDot;\mathrm{LSB}+\mathrm{sync}\left(m\right)\&CenterDot;\stackrel{\&OverBar;}{\mathrm{LSB}}$

$+\stackrel{\&OverBar;}{\mathrm{sync}1}\&CenterDot;\stackrel{\&OverBar;}{\mathrm{sync}2}\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\&CenterDot;\stackrel{\&OverBar;}{\mathrm{sync}\left(m\right)}\&CenterDot;\mathrm{MSB}{\left(m\right)}^{\&prime;}$

Wherein, do not exported by the m position binary code before the synchronous correction in the thick modular converter of MSB (m) ' expression, m the synchronous correction signal that the described folding electric circuit of sync (m) expression produces, the high-order output in m position that the described thick modular converter of MSB (m) expression is final, m, n are natural number, and 1≤m≤n.

2. bit synchronization bearing calibration according to claim 1 is characterized in that, described folding electric circuit is static circuit.

3. bit synchronization bearing calibration according to claim 1 is characterized in that, described folding electric circuit is dynamic circuit.

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