CN102970031B - Phase-locked loop frequency synthesizer - Google Patents

Abstract

The invention discloses a phase-locked loop frequency synthesizer which comprises a phase detection discriminator, a charge pump, a low-pass loop filter, a voltage controlled oscillator, a frequency divider, an automatic frequency controller and a decoder. The input end of the decoder is connected with the frequency divider, and the output end of the decoder is connected with the charge pump to produce control signals according to frequency dividing ratio of the frequency divider to control current of the charge pump to enable a current value of the charge pump to be inversely contracted with the square of the frequency dividing ratio of the frequency divider. The invention further discloses a method for keeping bandwidth of the frequency synthesizer loop to be stable. By means of the phase-locked loop frequency synthesizer and the method for keeping the bandwidth of the frequency synthesizer loop to be stable, the phase-locked loop frequency synthesizer can be provided with the stable loop bandwidth.

Description

Phase-locked loop frequency integrator

Technical field

The present invention relates to wireless communication field, be specifically related to a kind of phase-locked loop frequency integrator.

Background technology

The typical circuit diagram based on the frequency synthesizer 100' of charge pump phase lock loop as shown in Figure 1, frequency synthesizer 100' comprises: phase detection discriminator (PFD) 102', charge pump (CP) 103', low-pass loop filter (LPF) 104', LC voltage controlled oscillator (VCO) 105', frequency divider 106' and automatic frequency controller 107'(AFC, Automatic frequency calibration).Start after phase-locked loop operation at frequency synthesizer 100', the precise frequency that phase-locked loop completes LC voltage controlled oscillator 105' is tuning, namely phase detection discriminator 102' comparison reference signal frequencies omega ' _refwith the frequency after frequency divider 106' frequency division to be differed, charge pump 103' produces the discharge and recharge electric charge corresponding with difference and converts control voltage to by low-pass loop filter 104', to control increase or the reduction of voltage controlled oscillator 105' output frequency, progressively to reduce reference signal ω ' _refwith the frequency difference of feedback signal, until locking.

The transfer function LG (S) of this frequency synthesizer 100' is:

$\mathrm{LG}\left(S\right)=\frac{I_{\mathrm{CP}}}{2\mathrm{\π}}\·\mathrm{LF}\left(S\right)\·\frac{K_{\mathrm{VCO}}}{S}\·\frac{1}{N}$ (formula 1)

Wherein, I _cPbe charge pump current, LF (S) is the transfer function of loop filter 104', K _vCObe the sensitivity of LC voltage controlled oscillator 105', N is the divider ratio of frequency divider 106'.

Under normal circumstances, under frequency synthesizer 100' is operated in overdamping state, its closed loop-three dB bandwidth is:

${\mathrm{\ω}}_{-3\mathrm{dB}}\≈\frac{I_{\mathrm{CP}}}{2\mathrm{\π}}\·R_2\·\frac{K_{\mathrm{VCO}}}{N}$ (formula 2)

Wherein, R2 is the resistance value in loop filter 104'.

The performance of loop bandwidth to it of frequency synthesizer 100' has material impact, and loop bandwidth is too little can cause phase lock loop lock on time long, and meanwhile, in-band phase noise is bad, and loop bandwidth is too large and can worsen the outer phase noise of band of phase-locked loop.A loop bandwidth optimized, can compromise and consider the content of these several respects, but the loop bandwidth optimized can change along with the change of technique, temperature.In order to address this problem, obtain constant bandwidth, document [1] (Ting Wu, P.K.Hanumolu, K.Mayaram and Un-Ku Moon, ' Method for a ConstantLoop Bandwidth in LC-VCO PLL Frequency Synthesizers ' IEEE J.Solid-State Circuits, 2009,44, (2), P427 – P435) propose following methods.

Consider $K_{\mathrm{VCO}}=\frac{L}{2}\·{{\mathrm{\ω}}^3}_{\mathrm{OSC}}\·\left|\frac{{\∂C}_{\mathrm{VAR}}}{{\∂V}_{\mathrm{CTRL}}}\right|$ (formula 3)

Convert formula 2 to following form:

$\frac{{\mathrm{\ω}}_{-3\mathrm{dB}}}{{\mathrm{\ω}}_{\mathrm{ref}}}=\frac{I_{\mathrm{CP}}}{2\mathrm{\π}}\·R_2\·\frac{L}{2}\·{{\mathrm{\ω}}^2}_{\mathrm{OSC}}\·\left|\frac{{\∂C}_{\mathrm{VAR}}}{{\∂V}_{\mathrm{CTRL}}}\right|$ . (formula 4)

In formula 3,4, L is the resonant inductance of the resonant cavity of LC voltage controlled oscillator 105', C _vARfor the varactor of resonant cavity, V _cTRLfor the control voltage of voltage controlled oscillator 105', ω _oscfor frequency of oscillation.Inductance L is less along with the change of technique, can not consider.The change of R2, can by with I _cPgeneration resistance offset.Thus, in order to obtain constant bandwidth, need:

and $I_{\mathrm{CP}}\∝\frac{1}{{{\mathrm{\ω}}^2}_{\mathrm{OSC}}}.$

Document [1], by arranging the mode of many biased varactors to voltage controlled oscillator 105', makes the change equalization of varactor, thus obtains in order to make the electric current I of charge pump _cPbe inversely proportional to frequency of oscillation ω _oscsquare, voltage controlled oscillator 105' coarse adjustment and fine tuning loop are set, this voltage controlled oscillator 105' is also referred to as analog regulation VCO (analog tunedVCO), is obtained the height of voltage controlled oscillator 105' frequency, thus make I by the control voltage of coarse tuning loop _cPwith frequency of oscillation ω _oscbe inversely proportional to.

But the shortcoming of said method is, when voltage controlled oscillator 105' frequency needed for coverage wide time, need very large varactor, so just can worsen the phase noise of frequency synthesizer 100'.

Summary of the invention

For the problems referred to above, the object of the present invention is to provide a kind of phase-locked loop frequency integrator and the stable method of holding frequency synthesizer loop bandwidth, stable loop bandwidth can be provided while not worsening frequency synthesizer phase noise.

For achieving the above object, the present invention adopts following technical scheme:

Phase-locked loop frequency integrator, comprise phase detection discriminator, charge pump, low-pass loop filter, voltage controlled oscillator, frequency divider and automatic frequency controller, described phase detection discriminator one input termination reference signal, first output of another input termination frequency divider, the input of charge pump described in the output termination of phase detection discriminator, electric charge delivery side of pump connects the input of described low-pass loop filter, the input of voltage controlled oscillator described in the output termination of low-pass loop filter, the input of the output termination frequency divider of voltage controlled oscillator, second output of an input termination frequency divider of automatic frequency controller, another input termination reference signal, output is for exporting control signal, to control the value of the switched capacitor array control word of voltage controlled oscillator, described phase-locked loop frequency integrator also comprises decoder, the input of described decoder connects the 3rd output of frequency divider, output connects charge pump, control signal is produced for the frequency dividing ratio according to frequency divider, to control the electric current of charge pump, make the current value of charge pump be inversely proportional to frequency divider frequency dividing ratio square, namely be inversely proportional to voltage controlled oscillator frequency of oscillation square.

A kind of method that holding frequency synthesizer loop bandwidth is stable, for in phase-locked loop frequency integrator, described phase-locked loop frequency integrator comprises phase detection discriminator, charge pump, low-pass loop filter, voltage controlled oscillator, frequency divider, automatic frequency controller and decoder, described phase detection discriminator one input termination reference signal, first output of another input termination frequency divider, the input of charge pump described in the output termination of phase detection discriminator, electric charge delivery side of pump connects the input of described low-pass loop filter, the input of voltage controlled oscillator described in the output termination of low-pass loop filter, the input of the output termination frequency divider of voltage controlled oscillator, second output of an input termination frequency divider of automatic frequency controller, another input termination reference signal, output is for exporting control signal, to control the value of the switched capacitor array control word of voltage controlled oscillator, the input of described decoder connects the 3rd output of frequency divider, output connects charge pump, the stable method of described holding frequency synthesizer loop bandwidth comprises step:

Produce control signal by described decoder according to the frequency dividing ratio of frequency divider, to control the electric current of charge pump, make the current value of charge pump be inversely proportional to frequency divider frequency dividing ratio square, be namely inversely proportional to voltage controlled oscillator frequency of oscillation square.

Beneficial effect of the present invention is:

By arranging decoder, the electric current that control signal controls charge pump is produced according to the frequency dividing ratio of frequency divider, make the current value of charge pump be inversely proportional to frequency divider frequency dividing ratio square, thus coordinate the use of many biased voltage controlled oscillators, make phase-locked loop frequency integrator can have stable loop bandwidth.

Accompanying drawing explanation

Fig. 1 is typically based on the circuit diagram of the frequency synthesizer of charge pump phase lock loop;

Fig. 2 is the electrical block diagram of phase-locked loop frequency integrator of the present invention;

Fig. 3 is the circuit structure diagram of voltage controlled oscillator in Fig. 2;

Fig. 4 is the circuit structure diagram of the how biased MOS varactor in the voltage controlled oscillator of Fig. 3;

Fig. 5 is the circuit connection diagram in Fig. 2 between voltage controlled oscillator, frequency divider, phase detection discriminator, decoder and charge pump;

Fig. 6 is the spectrogram of phase-locked loop frequency integrator of the present invention when carrier frequency is 2.44GHZ;

Fig. 7 is the spectrogram of phase-locked loop frequency integrator of the present invention when carrier frequency is 2.56GHZ;

Fig. 8 is the spectrogram of phase-locked loop frequency integrator of the present invention when carrier frequency is 2.80GHZ.

Embodiment

Below, by reference to the accompanying drawings and embodiment, the present invention is described further:

As shown in Figure 2, the electrical block diagram of phase-locked loop frequency integrator 100 of the present invention, the structure of phase-locked loop frequency integrator 100 is roughly the same with prior art, but, described phase-locked loop frequency integrator 100 also comprises decoder 107, the input of described decoder 107 connects the 3rd output of frequency divider 106, output connects charge pump 103, control signal is produced for the frequency dividing ratio according to frequency divider 106, to control the electric current of charge pump 103, make the current value of charge pump 103 be inversely proportional to frequency divider 106 frequency dividing ratio square, namely be inversely proportional to voltage controlled oscillator 105 frequency of oscillation square.In the present embodiment, electric current is controlled with the direction of binary variation by controlling charge pump 103 electric current along with frequency dividing ratio.Described voltage controlled oscillator 105 adopts many biased MOS varactor, for being biased voltage controlled oscillator more.Described frequency divider 106 is integer frequency divider, carries out integral frequency divisioil, or is made up of integer frequency divider and decimal modulator, carries out integer and decimal mixing frequency division.In the present embodiment, comprise integer frequency divider 1061 for frequency divider 106 to be described (as shown in Figure 5) with decimal modulator 1062

Refer to Fig. 3 and Fig. 4, described voltage controlled oscillator 105 comprises the first metal-oxide-semiconductor M1, the second metal-oxide-semiconductor M2, the 3rd metal-oxide-semiconductor M3, the 4th metal-oxide-semiconductor M4, the 5th metal-oxide-semiconductor M5, the 6th metal-oxide-semiconductor M6, the 3rd electric capacity C3, the 4th electric capacity C4, the 5th electric capacity C5, the 6th electric capacity C6, inductance L and many biased MOS varactor 1051.The grid of M1 is as Section Point B, and drain electrode connects reference voltage V _dD, source electrode connects first node A as the grid of first node A, M2, and drain electrode connects reference voltage V _dD, source electrode connects Section Point B, inductance L is connected between first node A and Section Point B, the grid of M5 connects automatic frequency controller 109, source electrode is connected to Section Point B by C4, drain electrode is connected to first node A by C3, the grid of M6 connects automatic frequency controller 109, source electrode is connected to Section Point B by C6, drain electrode is connected to first node A by C5, many biased MOS varactor 1051 are connected between first node A and Section Point B, the grid of M3 connects Section Point B, grounded drain, source electrode connects first node A, the grid of M4 connects first node A, grounded drain, source electrode connects Section Point B.

Many biased MOS varactor 1051 comprise the 7th electric capacity C7, 8th electric capacity C8, 9th electric capacity C9, tenth electric capacity C10, 11 electric capacity C11, 12 electric capacity C12, 3rd resistance R3, 4th resistance R4, 5th resistance R5, 6th resistance R6, 7th resistance R7, 8th resistance R8, first MOS varactor Mos Var1, second MOS varactor MosVar2, 3rd MOS varactor Mos Var3, 4th MOS varactor Mos Var4, 5th MOS varactor Mos Var5 and the 6th MOS varactor Mos Var6, Mos Var1 one end is connected to first node A by C7, the other end is connected to Section Point B by Mos Var2 and C8, Mos Var3 one end is connected to first node A by C9, the other end is connected to Section Point B by Mos Var4 and C10, Mos Var5 one end is connected to first node A by C11, the other end is connected to Section Point B by Mos Var6 and C12, first reference voltage terminal Vbias1 is connected between C7 and Mos Var1 by the 3rd resistance R3, be connected between C8 and Mos Var2 by the 4th resistance R4, second reference voltage terminal Vbias2 is connected between C9 and Mos Var3 by the 5th resistance R5, be connected between C10 and Mos Var4 by the 6th resistance R6,3rd reference voltage terminal Vbias3 is connected between C11 and Mos Var5 by the 7th resistance R7, be connected between C12 and Mos Var6 by the 8th resistance R8, the control voltage end Vtune of voltage controlled oscillator 105 is connected between Mos Var1 and Mos Var2, be connected between Mos Var3 and Mos Var4, also be connected between Mos Var5 and Mos Var6.

Wherein, reference voltage terminal Vbias1, Vbias2 and Vbias3 provide the size of reference voltage not to be fixing respectively, and for the voltage controlled oscillator of different situations (as the situation such as supply voltage, technique is different), their value is different.Their determination needs to set according to actual needs, to reach, each MOS varactor to be tried one's best the object of linearisation emulation along with the change of voltage.

Refer to Fig. 5, in the present embodiment, the input word of described integer frequency divider 1061 adopts 8 bits to represent, i.e. Div<7:0>, the input word of decimal frequency divider 1062 adopts 19 bits to represent, i.e. inputword<18:0>, described charge pump 103 is the charge pump of 8, described decoder 107 is the decoder of 8, input word is Dinput<7:0>, low 5 high 5 as decoder input word of integer frequency divider 1061 input word, i.e. Div<4:0>=Dinput< 7:3>, high 3 low 3 as decoder input word of decimal frequency divider, i.e. inputword<18:16>=DinputLEssT. LTssT.LT2:0>.

Charge pump 103 comprises current source i _cp, current source 2i _cp, current source 4i _cp, current source 8i _cp, current source 16i _cp, current source 32i _cp, current source 64i _cp, current source 128i _cp, the 7th metal-oxide-semiconductor M7 and the 8th metal-oxide-semiconductor M8, current source i _cpone end ground connection, the other end is connected to node C by the first switch S 0, current source 2i _cpone end ground connection, the other end is connected to node C by second switch S1, current source 4i _cpone end ground connection, the other end is connected to node C by the 3rd switch S 2, current source 8i _cpone end ground connection, the other end is connected to node C by the 4th switch S 3, current source 16i _cpone end ground connection, the other end is connected to node C by the 5th switch S 4, current source 32i _cpone end ground connection, the other end is connected to node C by the 6th switch S 5, current source 64i _cpone end ground connection, the other end is connected to node C by the 7th switch S 6, and grid and the drain electrode of M7 are connected to node C, source ground respectively, and the grid of M8 is connected to node C, source ground, drains as the bias current output of charge pump 103.

The output of described decoder 107 to be respectively used to control in charge pump 103 first switch S 0 to the conducting or closed of the 8th switch S 7, with make the current value of charge pump 103 be inversely proportional to frequency divider frequency dividing ratio square.

In the present embodiment, concrete principle analysis is as follows, considers ω _-3dB=N ω _ref, wherein, N is the frequency dividing ratio that frequency divider is corresponding, has according to corresponding formula 4 of the prior art:

${\mathrm{\&omega;}}_{-3\mathrm{dB}}=\frac{I_{\mathrm{CP}}}{2\mathrm{\&pi;}}\&CenterDot;R_2\&CenterDot;\frac{L}{2}\&CenterDot;N^2\&CenterDot;{{\mathrm{\&omega;}}^3}_{\mathrm{ref}}\&CenterDot;\left|\frac{{\&PartialD;C}_{\mathrm{VAR}}}{{\&PartialD;V}_{\mathrm{CTRL}}}\right|$ . (formula 5)

Wherein, in LC voltage controlled oscillator 105, inductance L is less along with the change of technique, can not consider.In low-pass loop filter 104 R2 change can by with I _cPgeneration resistance disappear mutually and obtain.ω _reffor reference frequency, in a communications system, normally fixing, as the reference frequency of 16.386MHz can be used in GPS, the reference frequency of 30.72MHz can be used in LTE, the reference frequency of 26MHz can be used in gsm.Voltage controlled oscillator 105 adopts the mode of many biased varactors, then in order to obtain constant bandwidth, then need namely need wherein, I _cPofor the initial current of charge pump 103, i _cPfor the unit variable current of charge pump 103.And by determining I _cPo, i _cPwith the value of M to meet rear phase-locked loop frequency integrator of the present invention 100 can have constant bandwidth.

To I _cPo, i _cPas follows with the defining method of the value of M:

At reference frequency ω _ref, frequency dividing ratio N is set to maximum after determining by R2 and L value, and now, M=0, can obtain I _cPo.Frequency dividing ratio N is set to minimum value, the maximum current number Imax of charge pump can be obtained.Determine as M value, depend on the compromise between negative three dB bandwidth change (change of this road is because the precision of M is inadequate caused) and M, wherein, M value is larger, and bandwidth change is less.After M determines, just can obtain: i _cp=(I _max-I _cp0)/2 ^m.

In Fig. 5, the circuit connecting relation of phase-locked loop frequency integrator 100 can meet the operating frequency of voltage controlled oscillator at 2.43 ~ 2.80GHz, reference frequency ω _reffor the initial current I of 30.72MHz, charge pump _cPofor 410uA, unit variable current i _cPfor the working condition of 1uA.

Analyzed from above, the parameters such as the annexation of the input word figure place of frequency divider in the present invention, the figure place of charge pump, the figure place of decoder and frequency divider input word pin and decoder all need to set flexibly according to actual needs, if annexation finally can meet that above-mentioned length describes realize principle.

Following table is phase-locked loop frequency integrator 100 frequency dividing ratio, output frequency, charge pump current and deviation comparison diagram in Fig. 5, and what this deviation represented is because the precision of charge pump is limited, and the difference of loop theory bandwidth and actual bandwidth contrasts.Can find out, in frequency 2.43 ~ 2.9GHz, deviation is less than 2.8%.

Frequency dividing ratio	Output frequency (MHz)	Electric current (uA)	Deviation (%)
				79	2426.88	410	-2.29
79.125	2430.72	409	-2.22
				79.25	2434.56	408	-2.15
79.375	2438.4	407	-2.09
				79.5	2442.24	406	-2.02
79.625	2446.08	405	-1.95
				79.75	2449.92	404	-1.89
79.875	2453.76	403	-1.82
				80	2457.6	402	-1.76
80.125	2461.44	401	-1.70
				80.25	2465.28	400	-1.64

80.375	2469.12	399	-1.58
				80.5	2472.96	398	-1.52
80.625	2476.8	397	-1.46
				80.75	2480.64	396	-1.40
80.875	2484.48	395	-1.35
				81	2488.32	394	-1.29
81.125	2492.16	393	-1.24
				81.25	2496	392	-1.19
81.375	2499.84	391	-1.14
				81.5	2503.68	390	-1.09
81.625	2507.52	389	-1.04
				81.75	2511.36	388	-0.99
81.875	2515.2	387	-0.94
				82	2519.04	386	-0.89
82.125	2522.88	385	-0.85
				82.25	2526.72	384	-0.81
82.375	2530.56	383	-0.76
				82.5	2534.4	382	-0.72
82.625	2538.24	381	-0.68
				82.75	2542.08	380	-0.64
82.875	2545.92	379	-0.60
				83	2549.76	378	-0.57
83.125	2553.6	377	-0.53
				83.25	2557.44	376	-0.50
83.375	2561.28	375	-0.46
				83.5	2565.12	374	-0.43
83.625	2568.96	373	-0.40
				83.75	2572.8	372	-0.37
83.875	2576.64	371	-0.34
				84	2580.48	370	-0.31
84.125	2584.32	369	-0.29
				84.25	2588.16	368	-0.26
84.375	2592	367	-0.24
				84.5	2595.84	366	-0.21
84.625	2599.68	365	-0.19
				84.75	2603.52	364	-0.17
84.875	2607.36	363	-0.15
				85	2611.2	362	-0.13
85.125	2615.04	361	-0.11
				85.25	2618.88	360	-0.10
85.375	2622.72	359	-0.08
				85.5	2626.56	358	-0.07
85.625	2630.4	357	-0.06

85.75	2634.24	356	-0.05
				85.875	2638.08	355	-0.04
86	2641.92	354	-0.03
				86.125	2645.76	353	-0.02
86.25	2649.6	352	-0.01
				86.375	2653.44	351	-0.01
86.5	2657.28	350	0.00
				86.625	2661.12	349	0.00
86.75	2664.96	348	0.00
				86.875	2668.8	347	0.00
87	2672.64	346	0.00
				87.125	2676.48	345	0.00
87.25	2680.32	344	-0.01
				87.375	2684.16	343	-0.01
87.5	2688	342	-0.02
				87.625	2691.84	341	-0.03
87.75	2695.68	340	-0.03
				87.875	2699.52	339	-0.04
88	2703.36	338	-0.05
				88.125	2707.2	337	-0.07
88.25	2711.04	336	-0.08
				88.375	2714.88	335	-0.10
88.5	2718.72	334	-0.11
				88.625	2722.56	333	-0.13
88.75	2726.4	332	-0.15
				88.875	2730.24	331	-0.17
89	2734.08	330	-0.19
				89.125	2737.92	329	-0.21
89.25	2741.76	328	-0.24
				89.375	2745.6	327	-0.26
89.5	2749.44	326	-0.29
				89.625	2753.28	325	-0.32
89.75	2757.12	324	-0.35
				89.875	2760.96	323	-0.38
90	2764.8	322	-0.41
				90.125	2768.64	321	-0.44
90.25	2772.48	320	-0.48
				90.375	2776.32	319	-0.51
90.5	2780.16	318	-0.55
				90.625	2784	317	-0.59
90.75	2787.84	316	-0.63
				90.875	2791.68	315	-0.67
91	2795.52	314	-0.71

91.125	2799.36	313	-0.76
				91.25	2803.2	312	-0.80
91.375	2807.04	311	-0.85
				91.5	2810.88	310	-0.90
91.625	2814.72	309	-0.95
				91.75	2818.56	308	-1.00
91.875	2822.4	307	-1.05
				92	2826.24	306	-1.10
92.125	2830.08	305	-1.16
				92.25	2833.92	304	-1.22
92.375	2837.76	303	-1.27
				92.5	2841.6	302	-1.33
92.625	2845.44	301	-1.39
				92.75	2849.28	300	-1.46
92.875	2853.12	299	-1.52
				93	2856.96	298	-1.58
93.125	2860.8	297	-1.65
				93.25	2864.64	296	-1.72
93.375	2868.48	295	-1.79
				93.5	2872.32	294	-1.86
93.625	2876.16	293	-1.93
				93.75	2880	292	-2.00
93.875	2883.84	291	-2.08
				94	2887.68	290	-2.16
94.125	2891.52	289	-2.23
				94.25	2895.36	288	-2.31
94.375	2899.2	287	-2.39
				94.5	2903.04	286	-2.48
94.625	2906.88	285	-2.56
				94.75	2910.72	284	-2.65
94.875	2914.56	283	-2.73

Fig. 6, Fig. 7 and Fig. 8 are the spectrogram of phase-locked loop frequency integrator of the present invention when carrier frequency is respectively 2.44GHz, 2.56GHz and 2.80GHz.As can be seen from these 3 figure, within the scope of said frequencies, loop bandwidth remains on 90KHz, substantially constant, thus meets the demands.

For a person skilled in the art, according to technical scheme described above and design, other various corresponding change and distortion can be made, and all these change and distortion all should belong within the protection range of the claims in the present invention.

Claims (7)

1. phase-locked loop frequency integrator, comprise phase detection discriminator, charge pump, low-pass loop filter, voltage controlled oscillator, frequency divider and automatic frequency controller, described phase detection discriminator one input termination reference signal, first output of another input termination frequency divider, the input of charge pump described in the output termination of phase detection discriminator, electric charge delivery side of pump connects the input of described low-pass loop filter, the input of voltage controlled oscillator described in the output termination of low-pass loop filter, the input of the output termination frequency divider of voltage controlled oscillator, second output of an input termination frequency divider of automatic frequency controller, another input termination reference signal, output is for exporting control signal, to control the value of the switched capacitor array control word of voltage controlled oscillator, it is characterized in that, described phase-locked loop frequency integrator also comprises decoder, the input of described decoder connects the 3rd output of frequency divider, output connects charge pump, control signal is produced for the frequency dividing ratio according to frequency divider, to control the electric current of charge pump, make the current value of charge pump be inversely proportional to frequency divider frequency dividing ratio square, namely be inversely proportional to voltage controlled oscillator frequency of oscillation square,

Described voltage controlled oscillator comprises the first metal-oxide-semiconductor, the second metal-oxide-semiconductor, the 3rd metal-oxide-semiconductor, the 4th metal-oxide-semiconductor, the 5th metal-oxide-semiconductor, the 6th metal-oxide-semiconductor, the 3rd electric capacity, the 4th electric capacity, the 5th electric capacity, the 6th electric capacity, inductance and is biased MOS varactor more, the grid of the first metal-oxide-semiconductor is as Section Point B, and drain electrode connects reference voltage V _dD, source electrode is as first node A, and the grid of the second metal-oxide-semiconductor connects first node A, and drain electrode connects reference voltage V _dD, source electrode connects Section Point B, inductance is connected between first node A and Section Point B, the grid of the 5th metal-oxide-semiconductor connects automatic frequency controller, source electrode is connected to Section Point B by the 4th electric capacity, drain electrode is connected to first node A by the 3rd electric capacity, the grid of the 6th metal-oxide-semiconductor connects automatic frequency controller, source electrode is connected to Section Point B by the 6th electric capacity, drain electrode is connected to first node A by the 5th electric capacity, many biased MOS varactor are connected between first node A and Section Point B, the grid of the 3rd metal-oxide-semiconductor connects Section Point B, grounded drain, source electrode connects first node A, the grid of the 4th metal-oxide-semiconductor connects first node A, grounded drain, source electrode connects Section Point B.

2. phase-locked loop frequency integrator as claimed in claim 1, it is characterized in that, described frequency divider is integer frequency divider, or is made up of integer frequency divider and decimal modulator.

3. phase-locked loop frequency integrator as claimed in claim 2, is characterized in that, described voltage controlled oscillator adopts many biased MOS varactor, for being biased voltage controlled oscillator more.

4. phase-locked loop frequency integrator as claimed in claim 3, it is characterized in that, described frequency divider is made up of integer frequency divider and decimal modulator, the input word of integer frequency divider adopts 8 bits to represent, the input word of decimal frequency divider adopts 19 bits to represent, described charge pump is the charge pump of 8, described decoder is the decoder of 8, low 5 high 5 as decoder input word of integer frequency divider input word, high 3 low 3 as decoder input word of decimal frequency divider.

5. phase-locked loop frequency integrator as claimed in claim 4, it is characterized in that, charge pump comprises current source i _cp, current source 2i _cp, current source 4i _cp, current source 8i _cp, current source 16i _cp, current source 32i _cp, current source 64i _cp, current source 128i _cp, the 7th metal-oxide-semiconductor and the 8th metal-oxide-semiconductor, current source i _cpone end ground connection, the other end is connected to node C by the first switch S 0, current source 2i _cpone end ground connection, the other end is connected to node C by second switch S1, current source 4i _cpone end ground connection, the other end is connected to node C by the 3rd switch S 2, current source 8i _cpone end ground connection, the other end is connected to node C by the 4th switch S 3, current source 16i _cpone end ground connection, the other end is connected to node C by the 5th switch S 4, current source 32i _cpone end ground connection, the other end is connected to node C by the 6th switch S 5, current source 64i _cpone end ground connection, the other end is connected to node C by the 7th switch S 6, and grid and the drain electrode of the 7th metal-oxide-semiconductor are connected to node C, source ground respectively, and the grid of the 8th metal-oxide-semiconductor is connected to node C, source ground, drains as the bias current output of charge pump.

6. phase-locked loop frequency integrator as claimed in claim 5, it is characterized in that, the output of described decoder to be respectively used to control in charge pump the first switch S 0 to the conducting or closed of the 8th switch S 7, with make the current value of charge pump be inversely proportional to frequency divider frequency dividing ratio square.

7. phase-locked loop frequency integrator as claimed in claim 1, it is characterized in that, many biased MOS varactor comprise the 7th electric capacity, 8th electric capacity, 9th electric capacity, tenth electric capacity, 11 electric capacity, 12 electric capacity, 3rd resistance, 4th resistance, 5th resistance, 6th resistance, 7th resistance, 8th resistance, first MOS varactor, second MOS varactor, 3rd MOS varactor, 4th MOS varactor, 5th MOS varactor and the 6th MOS varactor, first MOS varactor one end is connected to first node A by the 7th electric capacity, the other end is connected to Section Point B by the second MOS varactor and the 8th electric capacity, 3rd MOS varactor one end is connected to first node A by the 9th electric capacity, the other end is connected to Section Point B by the 4th MOS varactor and the tenth electric capacity, 5th MOS varactor one end is connected to first node A by the 11 electric capacity, the other end is connected to Section Point B by the 6th MOS varactor and the 12 electric capacity, first reference voltage terminal is connected between the 7th electric capacity and the first MOS varactor by the 3rd resistance, be connected between the 8th electric capacity and the second MOS varactor by the 4th resistance, second reference voltage terminal is connected between the 9th electric capacity and the 3rd MOS varactor by the 5th resistance, be connected between the tenth electric capacity and the 4th MOS varactor by the 6th resistance, 3rd reference voltage terminal is connected between the 11 electric capacity and the 5th MOS varactor by the 7th resistance, be connected between the 12 electric capacity and the 6th MOS varactor by the 8th resistance, the control voltage end of voltage controlled oscillator is connected between the first MOS varactor and the second MOS varactor, be connected between the 3rd MOS varactor and the 4th MOS varactor, also be connected between the 5th MOS varactor and the 6th MOS varactor.