CN103022026B - Multi-chip module and manufacturing method thereof - Google Patents
Multi-chip module and manufacturing method thereof Download PDFInfo
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- CN103022026B CN103022026B CN201110289833.0A CN201110289833A CN103022026B CN 103022026 B CN103022026 B CN 103022026B CN 201110289833 A CN201110289833 A CN 201110289833A CN 103022026 B CN103022026 B CN 103022026B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 14
- 238000005070 sampling Methods 0.000 claims description 25
- 239000000758 substrate Substances 0.000 claims description 18
- 230000005669 field effect Effects 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 230000008878 coupling Effects 0.000 claims description 3
- 238000010168 coupling process Methods 0.000 claims description 3
- 238000005859 coupling reaction Methods 0.000 claims description 3
- 230000007246 mechanism Effects 0.000 description 4
- 230000017525 heat dissipation Effects 0.000 description 3
- 230000007812 deficiency Effects 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 208000032364 Undersensing Diseases 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
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- H—ELECTRICITY
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13062—Junction field-effect transistor [JFET]
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/13—Discrete devices, e.g. 3 terminal devices
- H01L2924/1304—Transistor
- H01L2924/1306—Field-effect transistor [FET]
- H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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Abstract
Description
技术领域 technical field
本发明涉及一种多芯片模块及其制造方法,特别是指一种将高压元件芯片与低压控制芯片固定于同一芯片座的多芯片模块及其制造方法。The invention relates to a multi-chip module and a manufacturing method thereof, in particular to a multi-chip module in which a high-voltage component chip and a low-voltage control chip are fixed on the same chip holder and a manufacturing method thereof.
背景技术 Background technique
图1显示一种典型的电源供应电路,其中,多芯片模块10中的低压控制芯片14,根据反驰式(flyback)的回授讯号FB,以及电流感测讯号CS,操作高压元件芯片12中的功率开关,以将输入电压Vin转换为输出电压Vout。FIG. 1 shows a typical power supply circuit, wherein the low-voltage control chip 14 in the multi-chip module 10 operates the high-voltage element chip 12 according to the flyback feedback signal FB and the current sensing signal CS. A power switch to convert the input voltage Vin to the output voltage Vout.
请参阅图2A,显示多芯片模块10一种现有技术的安排方式。如图所示,多芯片模块10包含高压元件芯片12与低压控制芯片14。其中,高压元件芯片12固定于专用的芯片座11上;且低压控制芯片14固定于另一个专用的芯片座13上。一般而言,高压元件与低压元件的制程不同,分别制造的成本较同时制造于同一基板上来得低,因此分别制造成为高压元件芯片12与低压控制芯片14是很普遍的方式;此外,高压元件若为垂直式的元件,则其基板表面具有电位,因此,高压元件芯片12与低压控制芯片14不宜同时固定于同一芯片座上,以免相互影响,甚至造成短路,其具体实施方式,如图2A所示,将高压元件芯片12与低压控制芯片14固定于不同的芯片座11与13上,并将其封装于同一模块中。这种现有技术的优点在于:整合高压元件芯片12与低压控制芯片14于单一封装之内,并避免芯片讯号相互的干扰影响。Please refer to FIG. 2A , which shows a prior art arrangement of the multi-chip module 10 . As shown in the figure, the multi-chip module 10 includes a high voltage element chip 12 and a low voltage control chip 14 . Wherein, the high-voltage component chip 12 is fixed on a dedicated chip holder 11 ; and the low-voltage control chip 14 is fixed on another dedicated chip holder 13 . Generally speaking, the manufacturing process of high-voltage components and low-voltage components is different, and the cost of manufacturing separately is lower than manufacturing on the same substrate at the same time. Therefore, it is very common to manufacture high-voltage component chips 12 and low-voltage control chips 14 separately; If it is a vertical component, the surface of the substrate has a potential. Therefore, the high-voltage component chip 12 and the low-voltage control chip 14 should not be fixed on the same chip holder at the same time, so as not to affect each other or even cause a short circuit. The specific implementation method is shown in Figure 2A As shown, the high-voltage element chip 12 and the low-voltage control chip 14 are fixed on different chip holders 11 and 13 and packaged in the same module. The advantage of this prior art is that it integrates the high-voltage component chip 12 and the low-voltage control chip 14 into a single package, and avoids mutual interference of chip signals.
图2B显示图2A中,AA切线的剖面图。如图所示,分开的芯片座11与芯片座13上,分别固定高压元件芯片12与低压控制芯片14,且其芯片间,利用金属导线15相互耦接,以传送讯号。这种现有技术的缺点是:芯片固定于单一专属芯片座,因此每一芯片座的面积相对于共享芯片座的安排方式小,如此一来,其散热的效率相对较差。此外,低压控制芯片14中的温度传感器(未示出)无法感测高压元件芯片12(或感测准确度较差)的温度,以于温度过高时启动过温保护(overtemperatureprotection,OTP)。上述现有技术例如可见于美国专利申请案第2007/0200537号。FIG. 2B shows a cross-sectional view of tangent line AA in FIG. 2A. As shown in the figure, the separate chip holder 11 and the chip holder 13 are respectively fixed with a high-voltage element chip 12 and a low-voltage control chip 14 , and the chips are connected to each other by metal wires 15 to transmit signals. The disadvantage of this prior art is that the chip is fixed on a single dedicated chip pad, so the area of each chip pad is smaller than that of the shared chip pad, so that the heat dissipation efficiency is relatively poor. In addition, the temperature sensor (not shown) in the low-voltage control chip 14 cannot sense the temperature of the high-voltage element chip 12 (or has poor sensing accuracy), so as to activate overtemperature protection (OTP) when the temperature is too high. The prior art described above can be found, for example, in US Patent Application No. 2007/0200537.
图3A-3C显示另一种多芯片模块20安排方式的现有技术。相较于前述现有技术,此现有技术是将高压元件与低压元件整合于单一(monolithic)芯片22中。如图3A所示,芯片座21将单一芯片22固定于其上,如此一来,芯片座21相较于前述的现有技术中,分开的芯片座11与13,本现有技术的散热面积较大,具有较佳的散热效果。图3B分别以简图显示单一芯片22的上视图,如图所示,高压元件221与低压元件222整合于单一芯片22中。图3C显示图2A中,AA切线的剖面图。但这种现有技术的缺点在于,高压元件需要与低压元件同时于同一基板上制造,其制造成本较高;此外,高压元件与低压元件于同一基板上,容易产生讯号相互影响的噪声问题,例如串扰(crosstalk)等问题。3A-3C show another prior art multi-chip module 20 arrangement. Compared with the aforementioned prior art, this prior art integrates the high voltage element and the low voltage element into a single (monolithic) chip 22 . As shown in FIG. 3A , the chip holder 21 fixes a single chip 22 thereon. In this way, compared with the aforementioned prior art, the chip holder 21 has separate chip holders 11 and 13, and the heat dissipation area of the prior art is smaller. Larger, with better cooling effect. FIG. 3B shows the top view of the single chip 22 in simplified diagrams. As shown in the figure, the high voltage element 221 and the low voltage element 222 are integrated in the single chip 22 . FIG. 3C shows a cross-sectional view of tangent line AA in FIG. 2A. However, the disadvantage of this prior art is that the high-voltage components and low-voltage components need to be manufactured on the same substrate at the same time, and the manufacturing cost is high; in addition, the high-voltage components and low-voltage components are on the same substrate, which is prone to the noise problem of signal interaction. Such as crosstalk (crosstalk) and other issues.
有鉴于此,本发明即针对上述现有技术的不足,提出一种将高压元件芯片与低压控制芯片固定于同一芯片座的多芯片模块及其制造方法,可改善芯片散热问题,并且不需要增加制造成本。In view of this, the present invention aims at the deficiencies of the above-mentioned prior art, and proposes a multi-chip module and its manufacturing method in which the high-voltage component chip and the low-voltage control chip are fixed on the same chip seat, which can improve the problem of chip heat dissipation, and does not need to increase manufacturing cost.
发明内容 Contents of the invention
本发明目的之一在于克服现有技术的不足与缺陷,提出一种多芯片模块。One of the objectives of the present invention is to overcome the deficiencies and defects of the prior art and propose a multi-chip module.
本发明另一目的在于,提出一种多芯片模块制造方法。Another object of the present invention is to provide a method for manufacturing a multi-chip module.
为达上述目的,就其中一观点言,本发明提供了一种多芯片模块,包含:一高压元件芯片,其具有至少一功率开关;一低压控制芯片,其通过金属导线与该高压元件芯片耦接;单一芯片座,用以将该高压元件芯片与该低压控制芯片固定于其上;以及多个引脚,通过该芯片座的一延伸部或金属导线与该单一芯片座耦接。In order to achieve the above object, from one point of view, the present invention provides a multi-chip module, comprising: a high-voltage component chip, which has at least one power switch; a low-voltage control chip, which is coupled to the high-voltage component chip through a metal wire. a single chip seat, used to fix the high voltage element chip and the low voltage control chip on it; and a plurality of pins, coupled with the single chip seat through an extension of the chip seat or metal wires.
在其中一种实施型态中,其中该高压元件芯片宜包括:一横向(lateral)金属氧化物半导体场效晶体管(metaloxidesemiconductorfieldeffecttransistor,MOSFET)功率开关;以及一横向空乏型启动开关。In one embodiment, the high-voltage device chip preferably includes: a lateral metal oxide semiconductor field effect transistor (MOSFET) power switch; and a lateral depletion-type start-up switch.
所述多芯片模块,其中该高压元件芯片可更包含一热二极管用以感测温度。In the multi-chip module, the high-voltage element chip may further include a thermal diode for sensing temperature.
在另一种实施型态中,其中该横向空乏型启动开关宜具有一横向空乏型MOSFET或一横向空乏型接面场效晶体管(junctionfieldeffecttransistor,JFET)。In another embodiment, the lateral depletion start switch preferably has a lateral depletion MOSFET or a lateral depletion junction field effect transistor (junction field effect transistor, JFET).
在另一种实施型态中,其中该功率开关具有一第一电流流入端、一第一控制端、以及一第一电流流出端,通过该第一控制端的操作,控制一开关电流流入该第一电流流入端,并自该第一电流流出端流出;该高压元件芯片更包括一取样晶体管,用以取样该开关电流,其包含:一第二电流流入端,包含于该第一电流流入端;一第二控制端,包含于该第一控制端;以及一第二电流流出端,与该第一电流流出端流出隔绝,并产生一与该开关电流具有一比例的取样电流。In another implementation mode, the power switch has a first current inflow terminal, a first control terminal, and a first current outflow terminal, through the operation of the first control terminal, a switch current is controlled to flow into the first A current inflow terminal, and flows out from the first current outflow terminal; the high voltage component chip further includes a sampling transistor, used to sample the switching current, which includes: a second current inflow terminal, included in the first current inflow terminal ; a second control terminal, included in the first control terminal; and a second current outflow terminal, isolated from the first current outflow terminal, and generating a sampling current proportional to the switch current.
就另一观点,本发明也提供了一种多芯片模块制造方法,包含:提供一高压元件芯片,其具有至少一功率开关;通过金属导线将该高压元件芯片耦接至一低压控制芯片;将该高压元件芯片与该低压控制芯片固定于单一芯片座;以及通过该芯片座的一延伸部或金属导线将该单一芯片座耦接至多个引脚。From another point of view, the present invention also provides a method for manufacturing a multi-chip module, including: providing a high-voltage element chip having at least one power switch; coupling the high-voltage element chip to a low-voltage control chip through metal wires; The high-voltage component chip and the low-voltage control chip are fixed on a single chip holder; and the single chip holder is coupled to a plurality of pins through an extension part or a metal wire of the chip holder.
下面通过具体实施例详加说明,当更容易了解本发明的目的、技术内容、特点及其所达成的功效。The following will be described in detail through specific embodiments, so that it is easier to understand the purpose, technical content, characteristics and effects of the present invention.
附图说明 Description of drawings
图第1显示一种典型的电源供应电路;Figure 1 shows a typical power supply circuit;
图2A-2B显示多芯片模块10一种现有技术的安排方式;2A-2B show a prior art arrangement of the multi-chip module 10;
图3A-3C显示另一种多芯片模块20安排方式的现有技术;3A-3C show another prior art multi-chip module 20 arrangement;
图4A-4B显示本发明第一个实施例;4A-4B show a first embodiment of the present invention;
图5A-5C显示本发明第二个实施例。5A-5C show a second embodiment of the present invention.
图中符号说明Explanation of symbols in the figure
10,20,30,40多芯片模块10, 20, 30, 40 multi-chip modules
11,13,15,21,31芯片座11, 13, 15, 21, 31 chip socket
12,16,32,42高压元件芯片12, 16, 32, 42 high voltage component chips
14,34,44低压控制芯片14, 34, 44 low voltage control chip
15,35金属导线15, 35 metal wire
22单一芯片22 single chip
221高压元件221 high voltage components
222低压元件222 low voltage components
37引脚37 pins
39延伸部39 extension
CS电流感测讯号CS current sense signal
Drain漏极Drain drain
DriftRegion漂移区DriftRegion drift area
FB回授讯号FB feedback signal
Gate栅极Gate grid
R电阻R resistance
S1功率开关S1 power switch
S2取样晶体管S2 sampling transistor
Source1,Source2源极Source1, Source2 source
Vin输入电压Vin input voltage
Vout输出电压Vout output voltage
具体实施方式 Detailed ways
请参阅图4A与4B,显示本发明第一个实施例,多芯片模块30中包含具有至少一功率开关的高压元件芯片32、低压控制芯片34、单一芯片座31与多个引脚37。如图4A所示,低压控制芯片34其通过金属导线35与高压元件芯片32耦接。并且,高压元件芯片32与低压控制芯片34皆固定于单一芯片座31上,如图4B所示的图4A中CC剖线的剖视图。此外,多个引脚37通过芯片座31的延伸部39或金属导线35与单一芯片座31上的高压元件芯片32与低压控制芯片34耦接。Please refer to FIGS. 4A and 4B , which show the first embodiment of the present invention. The multi-chip module 30 includes a high-voltage element chip 32 having at least one power switch, a low-voltage control chip 34 , a single chip holder 31 and multiple pins 37 . As shown in FIG. 4A , the low voltage control chip 34 is coupled to the high voltage element chip 32 through a metal wire 35 . Moreover, both the high-voltage component chip 32 and the low-voltage control chip 34 are fixed on a single chip holder 31 , as shown in FIG. 4B , which is a cross-sectional view taken along line CC in FIG. 4A . In addition, the plurality of pins 37 are coupled to the high-voltage element chip 32 and the low-voltage control chip 34 on the single chip holder 31 through the extension portion 39 of the chip holder 31 or the metal wire 35 .
为使高压元件芯片32与低压控制芯片34可固定于单一芯片座31上,且为避免如现有技术所述的垂直式高压元件的基板表面与低压控制芯片的基板表面具有不同的电位;本实施例的高压元件芯片32可以但不限于包括:横向金属氧化物半导体场效晶体管(metaloxidesemiconductorfieldeffecttransistor,MOSFET)功率开关;以及/或横向空乏型启动开关。由于横向高压元件与垂直式高压元件不同,其基板表面与低压控制芯片的基板表面具有相同电位(接地),因此可以固定于同一芯片座31上。In order to make the high-voltage element chip 32 and the low-voltage control chip 34 be fixed on a single chip seat 31, and to avoid the substrate surface of the vertical high-voltage element and the substrate surface of the low-voltage control chip as described in the prior art have different potentials; The high-voltage device chip 32 of the embodiment may include, but is not limited to: a lateral metal oxide semiconductor field effect transistor (MOSFET) power switch; and/or a lateral depletion-type start-up switch. Because the horizontal high-voltage element is different from the vertical high-voltage element, its substrate surface has the same potential (grounded) as the substrate surface of the low-voltage control chip, so it can be fixed on the same chip holder 31 .
其中,高压元件芯片32中,可以但不限于包括如热二极管(thermaldiode),可用以感测温度,进而对高压元件加以控制,以进一步避免芯片过热。Wherein, the high-voltage element chip 32 may include, but is not limited to, thermal diodes (thermal diodes), which can be used to sense temperature, and then control the high-voltage element to further prevent the chip from overheating.
此外,上述横向空乏型启动开关例如但不限于为横向空乏型MOSFET或横向空乏型接面场效晶体管(junctionfieldeffecttransistor,JFET),其用以操作于电路启动程序。In addition, the above-mentioned lateral depletion start-up switch is, for example but not limited to, a lateral depletion type MOSFET or a lateral depletion type junction field effect transistor (JFET), which is used to operate in the circuit start-up process.
图5A-5C显示本发明第二个实施例。如图5A所示,多芯片模块40中包含高压元件芯片42与低压控制芯片44。在本实施例中,高压元件芯片42例如包含功率开关S1与取样晶体管S2,取样晶体管S2用以感测功率开关S1的电流。取样晶体管S2的电流流入端耦接于功率开关S1的电流流入端。取样晶体管S2的控制端与功率开关S1的控制端,皆耦接于低压控制芯片44的控制接脚Gate。取样晶体管S2的电流流出端与电阻R的一端耦接,电阻R的另一端则耦接于地。(在NMOS的情况下,电流流入端为漏极、控制端为栅极、电流流出端为源极;在PMOS或双载子接面晶体管时则为对应的端子,此为相同技术领域中的具有通常知识者所熟知。)通过此种取样方式,可减少感测功率开关电流的功率损失,并提升效率,改善取样的精确度。此外,请参照图5B,显示通过取样晶体管S2感测功率开关S1电流,以达成过电流保护(overcurrentprotection,OCP)的机制,可以进一步省略低压控制芯片44的电流感测CS接脚。如图5B所示,将取样晶体管S2源极耦接至一比较器电路,与一设定值比较,并产生过电流保护讯号OCP,即可达成过电流保护机制,进而省略低压控制芯片44的电流感测CS接脚,以提高整合性,并降低制造成本。5A-5C show a second embodiment of the present invention. As shown in FIG. 5A , the multi-chip module 40 includes a high-voltage element chip 42 and a low-voltage control chip 44 . In this embodiment, the high voltage device chip 42 includes, for example, a power switch S1 and a sampling transistor S2 , and the sampling transistor S2 is used to sense the current of the power switch S1 . The current inflow terminal of the sampling transistor S2 is coupled to the current inflow terminal of the power switch S1. The control terminal of the sampling transistor S2 and the control terminal of the power switch S1 are both coupled to the control pin Gate of the low voltage control chip 44 . The current output end of the sampling transistor S2 is coupled to one end of the resistor R, and the other end of the resistor R is coupled to the ground. (In the case of NMOS, the current inflow terminal is the drain, the control terminal is the gate, and the current outflow terminal is the source; in the case of PMOS or bicarrier junction transistors, it is the corresponding terminal, which is the same technical field. Those with ordinary knowledge are well known.) Through this sampling method, the power loss of sensing the power switch current can be reduced, the efficiency can be improved, and the sampling accuracy can be improved. In addition, please refer to FIG. 5B , which shows a mechanism of sensing the current of the power switch S1 through the sampling transistor S2 to achieve an overcurrent protection (OCP) mechanism, and the current sensing CS pin of the low voltage control chip 44 can be further omitted. As shown in FIG. 5B , the source of the sampling transistor S2 is coupled to a comparator circuit, compared with a set value, and generates an over-current protection signal OCP to achieve an over-current protection mechanism, thereby omitting the low-voltage control chip 44. Current sense CS pin to improve integration and reduce manufacturing cost.
图5C显示取样晶体管S2与功率开关S1的上视图。如图5C所示,功率开关S1包含漏极Drain、漂移区、栅极Gate、以及源极Source1。在实际的做法中,可视为将源极Source1分割出一小段以作为取样晶体管S2的源极Source2,而漏极Drain、漂移区、与栅极Gate则与功率开关S1共享,也就是说,功率开关S1的漏极Drain(电流流入端)与栅极Gate(控制端)也分别作为或包含取样晶体管S2的漏极Drain(电流流入端)与栅极Gate(控制端),而取样晶体管S2的源极Source2(电流流出端)与功率开关S1的源极Source1(电流流出端)隔绝,但取样晶体管S2与功率开关S1整合成单一元件,以节约元件面积及简化元件制作程序。如此,可根据源极Source2与源极Source1的尺寸比例,与感测到的源极Source2电压或电流讯号,即可推导出功率开关S1的开关电流,以作为电流感测讯号CS或直接用以进行过电流保护机制。FIG. 5C shows a top view of the sampling transistor S2 and the power switch S1. As shown in FIG. 5C , the power switch S1 includes a drain Drain, a drift region, a gate Gate, and a source Source1 . In practice, it can be considered that the source Source1 is divided into a small section as the source Source2 of the sampling transistor S2, and the drain Drain, the drift region, and the gate Gate are shared with the power switch S1, that is, The drain Drain (current inflow terminal) and gate Gate (control terminal) of the power switch S1 also serve as or include the drain Drain (current inflow terminal) and gate Gate (control terminal) of the sampling transistor S2 respectively, and the sampling transistor S2 The source Source2 (current outflow end) of the power switch S1 is isolated from the source Source1 (current outflow end) of the power switch S1, but the sampling transistor S2 and the power switch S1 are integrated into a single component to save the component area and simplify the component manufacturing process. In this way, the switching current of the power switch S1 can be deduced according to the size ratio of the source Source2 and the source Source1, and the sensed source Source2 voltage or current signal, which can be used as the current sensing signal CS or directly used for Carry out overcurrent protection mechanism.
以上已针对较佳实施例来说明本发明,只是以上所述,仅为使本领域技术人员易于了解本发明的内容,并非用来限定本发明的权利范围。在本发明的相同精神下,本领域技术人员可以思及各种等效变化。例如,功率开关S1可为PMOS或NMOS晶体管;在所示各实施例电路中,可插入不影响讯号主要意义的元件,如其它开关等;又例如比较器或误差放大器的输入端正负可以互换,仅需对应修正电路的讯号处理方式即可;再例如本发明的多芯片模块可以应用于各种电源供应电路,例如功率因子校正(PFC)电路、返驰式功率因子校正电路、或半桥电路等,并非限于如各图所示的返驰式电路。凡此种种,皆可根据本发明的教示类推而得,因此,本发明的范围应涵盖上述及其它所有等效变化。The present invention has been described above with reference to preferred embodiments, but the above description is only for those skilled in the art to easily understand the content of the present invention, and is not intended to limit the scope of rights of the present invention. Under the same spirit of the present invention, various equivalent changes can be conceived by those skilled in the art. For example, the power switch S1 can be a PMOS or NMOS transistor; in the circuits shown in each embodiment, components that do not affect the main meaning of the signal can be inserted, such as other switches; and for example, the positive and negative inputs of the comparator or error amplifier can be interchanged , it only needs to correspond to the signal processing method of the correction circuit; another example, the multi-chip module of the present invention can be applied to various power supply circuits, such as power factor correction (PFC) circuits, flyback power factor correction circuits, or half bridges Circuits and the like are not limited to the flyback circuits shown in the respective figures. All of these can be deduced according to the teaching of the present invention, therefore, the scope of the present invention should cover the above and all other equivalent changes.
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| CN101378053A (en) * | 2007-08-31 | 2009-03-04 | 万国半导体股份有限公司 | High and low voltage side N channel metal oxide semiconductor field effect transistor combined package |
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