CN103066060B - The detection architecture of semiconductor device mismatch properties and detection method - Google Patents
The detection architecture of semiconductor device mismatch properties and detection method Download PDFInfo
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Abstract
A kind of detection architecture of semiconductor device mismatch properties and detection method, wherein, the detection architecture of described semiconductor device mismatch properties comprises: Semiconductor substrate, and be positioned at the some identical semiconductor device of semiconductor substrate surface, described semiconductor device angularly surrounds at least one annulus.Because the semiconductor device in the detection architecture of described semiconductor device mismatch properties has different angles, by contrasting difference or the standard deviation of different angles semiconductor device, judge that angles different is on a semiconductor wafer on the impact of semiconductor device mismatch properties, thus acquisition manufacture craft, the impact that the electrical parameter mismatch of semiconductor wafer on semiconductor device causes, thus the best putting position of semiconductor device is offered help when being designer's designing integrated circuit domain, and for the MOS transistor mismatch properties reducing to cause in manufacture process provides reference.
Description
Technical field
The present invention relates to semiconductor test technology, particularly a kind of detection architecture for detecting multiple identical semiconductor device mismatch properties and detection method.
Background technology
Along with the development of integrated circuit technique, the quantity of semiconductor device integrated in one chip is on the increase, and when carrying out integrated circuit (IC) design, usually needs the semiconductor device using some same electrical mathematic(al) parameters.Such as, when designing the memory cell of static random access memory (StaticRandomAccessMemory, SRAM), the MOS transistor of some same electrical mathematic(al) parameters is needed.The patent No. is the static random access memory U.S. patents disclosing a kind of 6 MOS transistor composition of US5744844.Please refer to Fig. 1, for the circuit diagram of the SRAM memory cell of described U.S. Patent Publication, described SRAM memory cell has four NMOS transistors 11,12,13,14 and two PMOS transistor 15,16, when carrying out SRAM design, nmos pass transistor 11 and 12 is needed to have identical electrical parameter, nmos pass transistor 13,14 has identical electrical parameter, and PMOS transistor 15,16 has identical electrical parameter.But; in the product of reality; nominally the electrical parameter of MOS transistor identical in SRAM memory cell usually can drift about; cause the electrical parameter mismatch (Mismatch) of MOS transistor that originally should be identical; namely matching properties declines, thus can cause the problems such as SRAM storage speed slows down, power consumption increases, clock is chaotic.
Therefore, the problem of semiconductor device mismatch properties is paid special attention in IC designer and chip manufacturing commercial city, to take appropriate measures improvement.The method of existing acquisition semiconductor device mismatch properties is generally realized by the method for computer simulation.Such as, the mismatch properties of MOS transistor is obtained by Monte-Carlo Simulation Method, specifically comprise: by choosing the electrical parameter (parameter such as such as channel length, width, threshold voltage, source and drain saturation current) of MOS transistor, and according to model, described electrical parameter is simulated, obtain the statistics of threshold voltage, the isoparametric deviation of source and drain saturation current.But, the method of the mismatch properties of the described identical MOS transistor utilizing computer simulation to obtain realizes based on Modling model, the process of Modling model is the approximate description to truth, the mismatch properties of product cannot be reflected truly comprehensively, more cannot analyze according to the mismatch properties of the semiconductor device recorded the reason causing electrical parameter mismatch, and then take corresponding measure to improve.
Summary of the invention
The problem that the present invention solves is to provide a kind of detection architecture and detection method of semiconductor device mismatch properties, mismatch properties detection is carried out to the semiconductor device with different angles and different interval, thus analyzes the reason causing the electrical parameter mismatch of semiconductor device.
For solving the problem, embodiments provide a kind of detection architecture of semiconductor device mismatch properties, comprise: Semiconductor substrate, be positioned at the some identical semiconductor device of semiconductor substrate surface, described semiconductor device angularly surrounds at least one annulus.
Optionally, when described semiconductor device surrounds multiple annulus, described semiconductor device surrounds donut, and described semiconductor device radially arranges.
Optionally, when described semiconductor device surrounds donut, away from the semiconductor device quantity on the annulus in the center of circle more than the semiconductor device quantity on the annulus in the center of circle, make the density away from the semiconductor device on the annulus in the center of circle identical with the density of the semiconductor device on the annulus near the center of circle.
Optionally, each annulus have four semiconductor device at least.
Optionally, the semiconductor device quantity on described each annulus is even number.
Optionally, the spacing between the semiconductor device in different annular is equal.
Optionally, described semiconductor device is field-effect transistor, bipolar junction transistor, diode or LED.
Optionally, when described semiconductor device is MOS transistor, the source electrode of described MOS transistor is unified to be positioned near the side in the center of circle or the unified side be positioned near the center of circle of the drain electrode of described MOS transistor.
The embodiment of the present invention additionally provides a kind of detection method of the semiconductor device mismatch properties utilizing the detection architecture of described semiconductor device mismatch properties to carry out detecting, and comprising:
The detection architecture of semiconductor device mismatch properties is provided;
Measure the electrical parameter of the semiconductor device in the detection architecture of described semiconductor device mismatch properties;
By the different manufacturing process of comparison in difference calculating the electrical parameter of described semiconductor device, different angles, device density to the influence degree of the electrical parameter mismatch of semiconductor device.
Optionally, described semiconductor device is field-effect transistor, bipolar junction transistor, diode or LED.
Optionally, when described semiconductor device is MOS transistor, described electrical parameter comprise threshold voltage, saturated drain current, cut-off drain current, conducting resistance, grid current, mutual conductance, source and drain conductance, voltage amplification coefficient wherein one or more.
Optionally, the difference calculating the electrical parameter of described semiconductor device comprises the standard deviation of the difference between electrical parameter and the electrical parameter of reference semiconductor device and the difference calculating and have each semiconductor device.
Optionally, when to there is different angles and after the semiconductor device be positioned on same annulus measures its electrical parameter, calculate the standard deviation of the difference between electrical parameter and the electrical parameter of reference semiconductor device or the difference with the semiconductor device of different angles, judge the impact that the crystal orientation of manufacturing process and semiconductor crystal wafer is caused semiconductor device mismatch properties.
Optionally.When to there is identical angles but being positioned at after semiconductor device different annular with different components density measures its electrical parameter, difference between the electrical parameter of the semiconductor device of calculating in different annular and the electrical parameter of reference semiconductor device or the standard deviation of difference, judge the impact that different components density causes semiconductor device mismatch properties.
Optionally, when to having identical angles, after identity unit density but the semiconductor device be positioned in different annular measure its electrical parameter, calculate semiconductor device in different annular electrical parameter and with reference to semiconductor device electrical parameter between difference or the standard deviation of difference, judge to be positioned at same ray and the impact that causes MOS transistor mismatch properties of the different MOS transistor in the distance center of circle.
Compared with prior art, the embodiment of the present invention has the following advantages:
The detection architecture of the semiconductor device mismatch properties of the embodiment of the present invention comprises some identical semiconductor device be positioned in Semiconductor substrate, described semiconductor device angularly surrounds at least one annulus, described semiconductor device is made to have different angles, by contrasting difference or the standard deviation of different angles semiconductor device, judge that angles different is on a semiconductor wafer on the impact of semiconductor device mismatch properties, thus acquisition manufacture craft, the impact that the electrical parameter mismatch of semiconductor wafer on semiconductor device causes, thus the best putting position of semiconductor device is offered help when being designer's designing integrated circuit domain, and for the MOS transistor mismatch properties reducing to cause in manufacture process provides reference.
Further, the described identical semiconductor device of the embodiment of the present invention surrounds several donuts, and described semiconductor device radially arranges, spacing between semiconductor device in different annular is different, by contrasting difference or the standard deviation of the semiconductor device of different spacing, judge that spacing different is on a semiconductor wafer to the difference of the influence degree of semiconductor device mismatch properties.
Further, the described semiconductor device of the embodiment of the present invention surrounds several donuts, away from the semiconductor device quantity on the annulus in the center of circle more than the semiconductor device quantity on the annulus in the center of circle, make the density away from the semiconductor device on the annulus in the center of circle identical with the density of the semiconductor device on the annulus near the center of circle, the impact that the difference eliminating MOS transistor density causes MOS transistor electric property, thus can judge more accurately to be positioned at same ray and the different MOS transistor in the distance center of circle to the difference of the influence degree of MOS transistor mismatch properties.
Accompanying drawing explanation
Fig. 1 is the circuit diagram of the SRAM memory cell of prior art;
Fig. 2, Fig. 3, Fig. 4 are the structural representations of the detection architecture of the semiconductor device mismatch properties of the present invention's three embodiments;
Fig. 5 is the schematic flow sheet of the detection method of the described semiconductor device mismatch properties of the embodiment of the present invention.
Embodiment
Have the integrated circuit comprising two or more identical semiconductor device manufactured after, the quality of the matching degree of described two or more identical semiconductor device judges one of major parameter of the performance of this integrated circuit often.Due in some integrated circuit to the difference of the electrical parameter of wherein identical semiconductor device and mismatch properties comparatively responsive, therefore need understand the reason that causes of mismatch properties and make mismatch properties diminish as far as possible.And the method obtaining semiconductor device mismatch properties in prior art is generally realized by the method for computer simulation, the method of the mismatch properties of the described same semiconductor device utilizing computer simulation to obtain realizes based on Modling model, the process of Modling model is the approximate description to truth, the mismatch properties of product cannot be reflected truly comprehensively, more cannot analyze according to the mismatch properties of the semiconductor device recorded the reason causing electrical parameter mismatch, and then take corresponding measure to improve.
Therefore, inventor is through research, propose a kind of detection architecture and detection method of semiconductor device mismatch properties, the detection architecture of described semiconductor device mismatch properties comprises: Semiconductor substrate, be positioned at the some identical semiconductor device of described semiconductor substrate surface, described semiconductor device angularly surrounds at least one annulus.Because described identical semiconductor device surrounds at least one annulus, the angles of the semiconductor device on annulus is different, by detecting the electrical parameter mismatch properties of the semiconductor device of different angles, obtain different manufacture craft, impact that the electrical parameter mismatch of semiconductor wafer on semiconductor device causes, and then take corresponding measure to improve.
For enabling above-mentioned purpose of the present invention, feature and advantage become apparent more, are described in detail the specific embodiment of the present invention below in conjunction with accompanying drawing.When describing the embodiment of the present invention in detail, for ease of illustrating, represent that the profile of device architecture can be disobeyed general ratio and be made partial enlargement, and described schematic diagram is example, it should not limit the scope of the invention at this.In addition, the three-dimensional space of length, width and the degree of depth should be comprised in actual fabrication.
Semiconductor device in the detection architecture of described semiconductor device mismatch properties is that field-effect transistor, bipolar junction transistor, diode, LED are wherein a kind of, or other semiconductor device.Convenient in order to describe, in embodiments of the present invention, described semiconductor device elaborates for MOS transistor, but in other embodiments, the semiconductor device in the detection architecture of described semiconductor device mismatch properties also can be the device of other types.Those skilled in the art can select the detection architecture with dissimilar semiconductor device according to the detection demand of different semiconductor device, and therefore the embodiment of the present invention explains for MOS transistor and should not limit the scope of the invention.
First embodiment of the invention provide firstly a kind of detection architecture of semiconductor device mismatch properties, please refer to Fig. 2, for the structural representation overlooking visual angle of the detection architecture of described semiconductor device mismatch properties, specifically comprise: Semiconductor substrate, be positioned at the some identical semiconductor device of described semiconductor substrate surface, described some identical semiconductor device angularly form annulus around the center of circle.In the present embodiment, described semiconductor device is MOS transistor 100, and 8 identical MOS transistor 100 angularly form annulus 110 around the center of circle, and the angle that adjacent mos transistors 100 and the center of circle are formed is all 45 °.
Described identical semiconductor device refers to that the geomery of semiconductor device is identical with formation process.In the present embodiment, described identical MOS transistor 100 refers to the shape, measure-alike of the corresponding figure of the mask plate forming described MOS transistor, the shape of the mask pattern that the grid structure namely forming each MOS transistor uses, measure-alike, the shape of the mask pattern that the source/drain region forming each MOS transistor uses, measure-alike; Meanwhile, described identical MOS transistor 100 also finger-type becomes the formation process of described MOS transistor identical, and the depositing operation, etching technics, ion implantation technology, annealing process etc. that are namely formed in each MOS transistor needed for MOS transistor are all identical.Because the geomery of described MOS transistor is all identical with formation process, the angle difference of just putting (being i.e. formed with certain angle between the straight line at the grid structure longer sides place of different MOS transistor), by measuring the electrical parameter of the different identical MOS transistor of angles, calculate the mismatch properties of described MOS transistor, thus can judge that semiconductor fabrication process is as etching, ion implantations etc. are in different directions to the difference of the influence degree of MOS transistor mismatch properties, and the crystal orientation of semiconductor wafer is to the difference of the influence degree of identical MOS transistor mismatch properties, thus can offer help for designer designs best angles, and for the MOS transistor mismatch properties reducing to cause in manufacture process provides reference.
In the present embodiment, 8 identical MOS transistor 100 angularly form annulus 110 around the center of circle, and described MOS transistor 100 comprises grid structure 102 and is positioned at the source/drain region 101 of described grid structure 102 both sides.The angle that adjacent mos transistors 100 and the center of circle are formed is all 45 °, and the longer sides of the grid structure of described MOS transistor 100 is parallel with the tangent line on the annulus being positioned at this point, the source electrode of described MOS transistor 100 is unified to be positioned near the side in the center of circle or the unified side be positioned near the center of circle of the drain electrode of described MOS transistor 100.In other embodiments, the longer sides of the grid structure of described MOS transistor can also be parallel with the ray through the center of circle.Rightmost MOS transistor is set as (the described setting with reference to MOS transistor is just for the ease of describing with reference to MOS transistor, also any one in other several MOS transistor can be set as in other embodiments with reference to MOS transistor), utilize described reference MOS transistor and other MOS transistor to compare.Because all the other 7 MOS transistor are followed successively by 45 °, 90 °, 135 °, 180 °, 225 °, 270 °, 315 ° with reference to MOS transistor angle in the counterclockwise direction, and the crystal orientation of semiconductor crystal wafer is determined, the crystal orientation of described semiconductor crystal wafer can to ion implantation and diffusion, have an impact to the wet etching etc. of wafer, and the final electrical parameter of the MOS transistor making to have different angles drifts about.Simultaneously, in the process of carrying out etching and ion implantation, due to plasma bombardment or not necessarily completely vertical when being injected into semicon-ductor structure surface, often have certain angle, even if what therefore utilize is identical etching or ion implantation technology, the profile graphics of the MOS transistor etching and ion implantation formation with different angles also has a little difference, and the final electrical parameter of the MOS transistor of different angles is drifted about.
In the present embodiment, be the straight line parallel that the longer sides of the MOS transistor of 180 ° and the described grid structure with reference to MOS transistor is corresponding with described with reference to MOS transistor angle in the counterclockwise direction, with described with reference to MOS transistor angle be in the counterclockwise direction 45 ° MOS transistor and with described be the straight line parallel that the grid structure longer sides of the MOS transistor of 225 ° is corresponding with reference to MOS transistor angle in the counterclockwise direction, with described with reference to MOS transistor angle be in the counterclockwise direction 90 ° MOS transistor and with described be the straight line parallel that the grid structure longer sides of the MOS transistor of 270 ° is corresponding with reference to MOS transistor angle in the counterclockwise direction, with described with reference to MOS transistor angle be in the counterclockwise direction 135 ° MOS transistor and with described be the straight line parallel that the grid structure longer sides of the MOS transistor of 315 ° is corresponding with reference to MOS transistor angle in the counterclockwise direction, but the source electrode due to described MOS transistor is unified to be positioned near the side in the center of circle or the unified side be positioned near the center of circle of the drain electrode of described MOS transistor, the position of the source/drain region of described MOS transistor is not identical, thus the crystal orientation of wafer can be checked, manufacturing process is respectively to source region, the impact that drain region is caused.
In other embodiments, the quantity being positioned at the MOS transistor of same annulus is 4,6,10 etc., it is the multiple of 2, the difference of the angles of described MOS transistor is different, not only can test the impact that different angles causes semiconductor device, and can simultaneously the crystal orientation of test verification wafer, manufacturing process respectively on the impact that source region, drain region are caused.
Second embodiment of the invention provides the detection architecture of another kind of semiconductor device mismatch properties, please refer to Fig. 3, for the structural representation overlooking visual angle of the detection architecture of described semiconductor device mismatch properties, specifically comprise: Semiconductor substrate, be positioned at the some identical semiconductor device of described semiconductor substrate surface, described some identical semiconductor device angularly form some donuts around the center of circle, and described some identical semiconductor device radially arrange.In the present embodiment, described semiconductor device is MOS transistor 200, described MOS transistor 200 angularly forms 3 donuts around the center of circle, comprise the first annulus 210, second annulus 220, 3rd annulus 230, each annulus is placed with 8 identical MOS transistor 200, have 24 identical MOS transistor 200, be positioned at the angle that adjacent mos transistors on same annulus 200 and the center of circle formed and be all 45 °, and described MOS transistor 200 radially arranges, adjacent equal angular 8 rays sent from center of circle place crossing with 3 donuts is all formed with MOS transistor 200.
In the present embodiment, because the MOS transistor 200 in the detection architecture of described semiconductor device mismatch properties is also angularly form several donuts around the center of circle, therefore, the angles being positioned at the described MOS transistor 200 on same annulus is different, by the mismatch properties of MOS transistor in the detection architecture of testing described semiconductor device mismatch properties, obtain the crystal orientation of semiconductor crystal wafer, the impact that the MOS transistor of concrete semiconductor fabrication process on different angles causes, and the drain electrode unification of the source electrode of described the MOS transistor unified side or described MOS transistor that are positioned at the close center of circle is positioned at the side near the center of circle, also can detect the crystal orientation of wafer simultaneously, manufacturing process is respectively to source region, the impact that drain region is caused.
In the present embodiment, identical MOS transistor 200 angularly forms several donuts around the center of circle, spacing between described adjacent rings is equal, and described MOS transistor 200 radially arranges, equal angular 8 rays sent from center of circle place crossing with donut is all formed with MOS transistor, make the angles of the MOS transistor be positioned on same ray identical, the crystal orientation of wafer can be avoided, impact that manufacturing process causes MOS transistor.MOS transistor on first annulus 210 is set as (the described setting with reference to MOS transistor is just for the ease of describing with reference to MOS transistor, also the MOS transistor on other annulus can be set as in other embodiments with reference to MOS transistor), due to the first annulus 210, second annulus 220, the spacing that MOS transistor on 3rd annulus 230 is separated by becomes large successively, make the density of the region MOS transistor near the center of circle larger, density away from the region MOS transistor in the center of circle is less, same ray is positioned at but the electrical parameter being positioned at the MOS transistor in different annular by measuring, the electrical parameter of the MOS transistor on the described electrical parameter with reference to MOS transistor and other annulus is compared, calculate the mismatch properties of described MOS transistor, thus the difference of the density of MOS transistor to the influence degree of MOS transistor mismatch properties can be judged.
In other embodiments, the quantity being positioned at the MOS transistor of same annulus is 4,5,6,7,9,10 etc., due to be positioned at the described MOS transistor of same annulus to put quantity different, thus the impact that the electrical parameter of different density of semiconductor devices on semiconductor device cause can be tested.
Third embodiment of the invention provides the detection architecture of another kind of semiconductor device mismatch properties, please refer to Fig. 4, for the structural representation overlooking visual angle of the detection architecture of described semiconductor device mismatch properties, specifically comprise: Semiconductor substrate, be positioned at the some identical semiconductor device of described semiconductor substrate surface, described some identical semiconductor device angularly form some donuts around the center of circle, away from the semiconductor device quantity on the annulus in the center of circle more than the semiconductor device quantity on the annulus in the center of circle, make the density away from the semiconductor device on the annulus in the center of circle identical with the density of the semiconductor device on the annulus near the center of circle.In the present embodiment, described semiconductor device is MOS transistor 300, described MOS transistor 300 angularly forms 3 donuts around the center of circle, near first annulus in the center of circle 310 is placed with 8 identical MOS transistor, farthest away from the 3rd annulus in the center of circle 330 is placed with 16 identical MOS transistor, the second annulus 320 between described first annulus 310 and the 3rd annulus 330 is placed with 12 identical MOS transistor, spacing between described MOS transistor is roughly the same, make the density away from the semiconductor device on the annulus in the center of circle identical with the density of the semiconductor device on the annulus near the center of circle.In other embodiments, the quantity of the semiconductor device on described annulus also can be other number, only needs to make the density away from the semiconductor device on the annulus in the center of circle identical with the density of the semiconductor device on the annulus near the center of circle.
In the present embodiment, because the MOS transistor in the detection architecture of described semiconductor device mismatch properties is also angularly form several donuts around the center of circle, therefore, the angles of described MOS transistor is different, by the mismatch properties of MOS transistor in the detection architecture of testing described semiconductor device mismatch properties, obtain the crystal orientation of semiconductor crystal wafer, the impact that the MOS transistor of concrete semiconductor fabrication process on different angles causes, and the drain electrode unification of the source electrode of described the MOS transistor unified side or described MOS transistor that are positioned at the close center of circle is positioned at the side near the center of circle, also can detect the crystal orientation of wafer simultaneously, manufacturing process is respectively to source region, the impact that drain region is caused.And because the angles of the MOS transistor in the detection architecture of the semiconductor device mismatch properties of the present embodiment is than the first embodiment, the angles of the MOS transistor in the second embodiment is many, make to utilize the detection architecture of described semiconductor device mismatch properties can measure the electrical parameter of the MOS transistor of more different angles, thus the mismatch properties of MOS transistor in the detection architecture of described semiconductor device mismatch properties can be tested better, obtain the crystal orientation of semiconductor crystal wafer better, the impact that the MOS transistor of semiconductor fabrication process on different angles causes.
In addition, due to identical with the density of the MOS transistor on the annulus in the center of circle away from the density of the MOS transistor on the annulus in the center of circle in the present embodiment, thus the impact that the density difference can eliminating MOS transistor causes MOS transistor electric property.MOS transistor on first annulus 310 is set as (the described setting with reference to MOS transistor is just for the ease of describing with reference to MOS transistor, also the MOS transistor on other annulus can be set as in other embodiments with reference to MOS transistor), when identical to angles but the electrical parameter being positioned at the MOS transistor in different annular is tested time, due to the impact that the difference eliminating MOS transistor density causes MOS transistor electric property, the electrical parameter of the MOS transistor on the described electrical parameter with reference to MOS transistor and other annulus is compared, calculate the mismatch properties of described MOS transistor, thus can judge more accurately to be positioned at same ray and the different MOS transistor in the distance center of circle to the difference of the influence degree of MOS transistor mismatch properties.
In other embodiments, MOS transistor can also be formed with in the center of circle, near the position in the center of circle, make the density of the MOS transistor of center of circle near zone identical with the density away from the MOS transistor on the annulus in the center of circle, the impact that the density difference more effectively eliminating MOS transistor causes MOS transistor electric property.
In other embodiments, the detection architecture of the semiconductor device mismatch properties that the figure providing several semiconductor device to arrange is identical, the spacing of different annular is different, by the mismatch properties of semiconductor device in the detection architecture that detects different semiconductor device mismatch properties, judge the impact that the electric property of different spacing on semiconductor device causes.
The embodiment of the present invention additionally provides a kind of detection method of the semiconductor device mismatch properties utilizing the detection architecture of semiconductor device mismatch properties to carry out detecting, please refer to Fig. 5, for the schematic flow sheet of the detection method of described semiconductor device mismatch properties, specifically comprise:
Step S101, provides the detection architecture of semiconductor device mismatch properties;
Step S102, measures the electrical parameter of the semiconductor device in the detection architecture of described semiconductor device mismatch properties;
Step S103, by the different manufacturing process of comparison in difference calculating the electrical parameter of described semiconductor device, different angles, device density to the influence degree of the electrical parameter mismatch of semiconductor device.
Be described in detail below in conjunction with the embodiment of a specific embodiment to the detection method of semiconductor device mismatch properties of the present invention.
Perform step S101, the detection architecture of semiconductor device mismatch properties is provided.
One in the detection architecture of the semiconductor device mismatch properties that the detection architecture of described semiconductor device mismatch properties provides for the embodiment of the present invention, different testing goals selects the detection architecture of different semiconductor device mismatch properties.
Perform step S102, measure the electrical parameter of the semiconductor device in the detection architecture of described semiconductor device mismatch properties.
Described electrical parameter comprises resistance, electric current etc.In embodiments of the present invention, described semiconductor device is MOS transistor, and described electrical parameter comprises threshold voltage, saturated drain current, cut-off drain current, conducting resistance, grid current, mutual conductance, source and drain conductance, voltage amplification coefficient wherein one or more.
Perform step S103, by the different manufacturing process of comparison in difference calculating the electrical parameter of described semiconductor device, different angles, device density to the influence degree of the electrical parameter mismatch of semiconductor device.
When to there is different angles and after the semiconductor device be positioned on same annulus measures its electrical parameter, calculate the difference between electrical parameter and the electrical parameter of reference semiconductor device with the semiconductor device of different angles, the standard deviation of the difference between the electrical parameter of the semiconductor device with different angles and the electrical parameter of reference semiconductor device can also be calculated, utilize described difference or standard deviation to weigh the mismatch of same semiconductor device.Contrast difference or the standard deviation of the semiconductor device of different angles, to judge that angles different is on a semiconductor wafer on the impact of semiconductor device mismatch properties, thus judge semiconductor fabrication process such as ion implantation, etchings etc. are in the difference of different directions to the influence degree of semiconductor device mismatch properties, and the crystal orientation of semiconductor crystal wafer is to the difference of the influence degree of semiconductor device mismatch properties, thus the best putting position of semiconductor device is offered help when being designer's designing integrated circuit domain, and for the MOS transistor mismatch properties reducing to cause in manufacture process provides reference.Relative to the method for the mismatch properties of the semiconductor device of computer simulation acquisition, the method of the embodiment of the present invention is more direct, and real reaction manufacturing process and semiconductor crystal wafer itself impact that mismatch properties is caused comparatively comprehensively, and then provide reference for layout design.
When to there is identical angles but being positioned at after semiconductor device different annular with different components density measures its electrical parameter, calculate the difference between the electrical parameter of the semiconductor device in different annular and the electrical parameter of reference semiconductor device, the standard deviation of the difference between the electrical parameter of the semiconductor device in different annular and the electrical parameter of reference semiconductor device can also be calculated, utilize described difference or standard deviation to weigh the mismatch of same semiconductor device.The difference of the semiconductor device in contrast different annular or standard deviation, to judge the impact of device densities different on a semiconductor wafer on semiconductor device mismatch properties.
When to having identical angles, after identity unit density but the semiconductor device be positioned in different annular measure its electrical parameter, calculate the difference between the electrical parameter of the semiconductor device in different annular and the electrical parameter of reference semiconductor device, the standard deviation of the difference between the electrical parameter of the semiconductor device in different annular and the electrical parameter of reference semiconductor device can also be calculated, utilize described difference or standard deviation to weigh the mismatch of same semiconductor device.The difference of semiconductor device in contrast different annular or standard deviation, with judge to be positioned at same ray and the different MOS transistor in the distance center of circle to the difference of the influence degree of MOS transistor mismatch properties.
To sum up, the detection architecture of the semiconductor device mismatch properties of the embodiment of the present invention comprises some identical semiconductor device be positioned in Semiconductor substrate, described semiconductor device angularly surrounds at least one annulus, described semiconductor device is made to have different angles, by contrasting difference or the standard deviation of different angles semiconductor device, to judge that angles different is on a semiconductor wafer on the impact of semiconductor device mismatch properties, thus acquisition manufacture craft, the impact that the electrical parameter mismatch of semiconductor wafer on semiconductor device causes, thus the best putting position of semiconductor device is offered help when being designer's designing integrated circuit domain, and for the MOS transistor mismatch properties reducing to cause in manufacture process provides reference.
Further, the described identical semiconductor device of the embodiment of the present invention surrounds several donuts, and described semiconductor device radially arranges, spacing between semiconductor device in different annular is different, by contrasting difference or the standard deviation of the semiconductor device of different spacing, to judge the difference of spacing different on a semiconductor wafer to the influence degree of semiconductor device mismatch properties.
Further, the described semiconductor device of the embodiment of the present invention surrounds several donuts, away from the semiconductor device quantity on the annulus in the center of circle more than the semiconductor device quantity on the annulus in the center of circle, make the density away from the semiconductor device on the annulus in the center of circle identical with the density of the semiconductor device on the annulus near the center of circle, the impact that the difference eliminating MOS transistor density causes MOS transistor electric property, thus can judge more accurately to be positioned at same ray and the different MOS transistor in the distance center of circle to the difference of the influence degree of MOS transistor mismatch properties.
Although the present invention with preferred embodiment openly as above; but it is not for limiting the present invention; any those skilled in the art without departing from the spirit and scope of the present invention; the Method and Technology content of above-mentioned announcement can be utilized to make possible variation and amendment to technical solution of the present invention; therefore; every content not departing from technical solution of the present invention; the any simple modification done above embodiment according to technical spirit of the present invention, equivalent variations and modification, all belong to the protection range of technical solution of the present invention.
Claims (14)
1. the detection architecture of a semiconductor device mismatch properties, it is characterized in that, comprise: Semiconductor substrate, be positioned at the some identical semiconductor device of semiconductor substrate surface, described semiconductor device angularly surrounds multiple donut, and described semiconductor device radially arranges, the ray sent from the center of circle of the described donut place crossing with described donut is formed with semiconductor device.
2. the detection architecture of semiconductor device mismatch properties as claimed in claim 1, it is characterized in that, when described semiconductor device surrounds donut, away from the semiconductor device quantity on the annulus in the center of circle more than the semiconductor device quantity on the annulus in the center of circle, make the density away from the semiconductor device on the annulus in the center of circle identical with the density of the semiconductor device on the annulus near the center of circle.
3. the detection architecture of semiconductor device mismatch properties as claimed in claim 1, is characterized in that each annulus having four semiconductor device at least.
4. the detection architecture of semiconductor device mismatch properties as claimed in claim 3, it is characterized in that, the semiconductor device quantity on described each annulus is even number.
5. the detection architecture of semiconductor device mismatch properties as claimed in claim 1, it is characterized in that, the spacing between the semiconductor device in different annular is equal.
6. the detection architecture of semiconductor device mismatch properties as claimed in claim 1, it is characterized in that, described semiconductor device is field-effect transistor, bipolar junction transistor, diode or LED.
7. the detection architecture of semiconductor device mismatch properties as claimed in claim 1, it is characterized in that, when described semiconductor device is MOS transistor, the source electrode of described MOS transistor is unified to be positioned near the side in the center of circle or the unified side be positioned near the center of circle of the drain electrode of described MOS transistor.
8. utilize the detection architecture of claim 1 to 3 wherein a kind of described semiconductor device mismatch properties to carry out a detection method for the semiconductor device mismatch properties detected, it is characterized in that, comprising:
The detection architecture of semiconductor device mismatch properties is provided;
Measure the electrical parameter of the semiconductor device in the detection architecture of described semiconductor device mismatch properties;
By the different manufacturing process of comparison in difference calculating the electrical parameter of described semiconductor device, different angles, device density to the influence degree of the electrical parameter mismatch of semiconductor device.
9. the detection method of semiconductor device mismatch properties as claimed in claim 8, it is characterized in that, described semiconductor device is field-effect transistor, bipolar junction transistor, diode or LED.
10. the detection method of semiconductor device mismatch properties as claimed in claim 8, it is characterized in that, when described semiconductor device is MOS transistor, described electrical parameter comprise threshold voltage, saturated drain current, cut-off drain current, conducting resistance, grid current, mutual conductance, source and drain conductance, voltage amplification coefficient wherein one or more.
The detection method of 11. semiconductor device mismatch properties as claimed in claim 8, it is characterized in that, the difference calculating the electrical parameter of described semiconductor device comprises the standard deviation of the difference between electrical parameter and the electrical parameter of reference semiconductor device or the difference calculating and have each semiconductor device.
The detection method of 12. semiconductor device mismatch properties as claimed in claim 11, it is characterized in that, when to there is different angles and after the semiconductor device be positioned on same annulus measures its electrical parameter, calculate the standard deviation of the difference between electrical parameter and the electrical parameter of reference semiconductor device or the difference with the semiconductor device of different angles, judge the impact that the crystal orientation of manufacturing process and semiconductor crystal wafer is caused semiconductor device mismatch properties.
The detection method of 13. semiconductor device mismatch properties as claimed in claim 11, it is characterized in that, when to there is identical angles but being positioned at after semiconductor device different annular with different components density measures its electrical parameter, difference between the electrical parameter of the semiconductor device of calculating in different annular and the electrical parameter of reference semiconductor device or the standard deviation of difference, judge the impact that different components density causes semiconductor device mismatch properties.
The detection method of 14. semiconductor device mismatch properties as claimed in claim 11, it is characterized in that, when to having identical angles, after identity unit density but the semiconductor device be positioned in different annular measure its electrical parameter, calculate semiconductor device in different annular electrical parameter and with reference to semiconductor device electrical parameter between difference or the standard deviation of difference, judge to be positioned at same ray and the impact that causes MOS transistor mismatch properties of the different MOS transistor in the distance center of circle.
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| CN1770166A (en) * | 2004-08-31 | 2006-05-10 | 英赛特半导体有限公司 | Design Analysis Methods of Existing Integrated Circuits |
| CN101281877A (en) * | 2007-04-03 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Method for measuring MOS transistor dismatching features, territory pattern and forming method thereof |
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| CN101281877A (en) * | 2007-04-03 | 2008-10-08 | 中芯国际集成电路制造(上海)有限公司 | Method for measuring MOS transistor dismatching features, territory pattern and forming method thereof |
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