CN103067013B - Craft imbalance non-sensitive cyclic analog-digital converter and conversion method - Google Patents

Abstract

The present invention relates to the field of integrated circuit design in microelectronics. In order to reduce the sensitivity of Cyclic ADC to process misadjustment and improve the linearity of Cyclic ADC, in order to achieve the above-mentioned purpose, the technical solution adopted by the present invention is that the non-sensitive cyclic analog-to-digital converter of process misalignment is performed by a multiplication digital-to-analog converter. Analog-to-digital conversion and circular multiplication by 2 operations, including digital correction circuits and registers; the multiplication digital-to-analog converter consists of 1.5bit sub-ADC, DAC, linkage switches S ₁ -S ₁₃ , linkage switches S _w1 -S _w2 and capacitor C _1P , Composed of C _1N , C _2P , C _2N , C _3P , and C _3N . The invention is mainly applied to integrated circuit design.

Description

Process offset insensitive cyclic analog-to-digital converter and conversion method

technical field

The invention relates to the field of integrated circuit design of microelectronics, in particular to a non-sensitive circulation analog-to-digital converter and a conversion method of process imbalance.

Background technique

Cyclic ADC (Cyclic Analog-to-Digital Converter, Cyclic Analog-to-Digital Converter) has the advantages of simple structure, high speed, low power consumption and small area, and it is widely used in various sensor readout circuits, such as CMOS image sensor. The equivalent circuit structure of a Cyclic ADC that outputs 1.5 bits per cycle is shown in Figure 1. The analog input signal is converted by MDAC (Multiplying Digital-to-analog, multiplication digital-to-analog) for analog-to-digital conversion and cycle multiplication by 2. All the cyclically output digital signals are processed by the RSD (Redundant Signed Digit) digital correction circuit and then restored to the final converted digital signal, which is finally output by the register. Cyclic ADC needs to accurately multiply the analog signal by 2 to ensure that the ADC has sufficient linearity. The multiplication by 2 circuit is generally implemented by a switched capacitor circuit, and the mismatch of the capacitance will affect the accuracy of the multiplication by 2. With the reduction of the feature size of the integrated circuit process, the power consumption of the integrated circuit is also gradually reduced, but the mismatch of the device becomes more serious, which further deteriorates the gain accuracy of the multiplied by 2 circuit in the Cyclic ADC, thereby reducing the Linearity of Cyclic ADC. In the prior art, a digital calibration method can be used to solve the problem of device mismatch, but this will inevitably increase the scale and complexity of the digital circuit. The Cyclic ADC offset elimination method provided by the prior art is to store the negative offset voltage in the cross-reverse connection of the feedback capacitor, and then superimpose and eliminate it with the positive offset of each cycle. This method can change the equivalent input offset voltage of the Cyclic ADC to is approximately 0, but there are positive and negative feedback loops in the system in the imbalance storage stage, and the negative feedback must be stronger than the positive feedback system to be stable, so there are unstable factors in the system, which reduces the stability of the system.

Contents of the invention

The present invention aims to overcome the deficiencies of the prior art, reduce the sensitivity of Cyclic ADC to process imbalance, and improve the linearity of CyclicADC. The multiplication digital-to-analog converter performs analog-to-digital conversion and circular multiplication by 2 operations, and also includes digital correction circuits and registers; the multiplication digital-to-analog converter consists of 1.5bit sub-ADC, DAC, linkage switches S ₁ -S ₁₃ , linkage switch S _w1 -S _w2 is composed of capacitors C _1P , C _1N , C _2P , C _2N , C _3P , and C _3N . V _inp is connected to the negative pole of capacitor C _1P via linkage switch S ₁ , and the positive pole of C _1P is divided into four via linkage switch S ₄ One way is connected to the non-inverting input terminal of the op amp through the linkage switch Sw ₁ , the other is connected to the inverting input terminal of the op amp through the linkage switch Sw ₂ , and the other way is connected to the positive terminal of the capacitor C _2P through the linkage switch S ₁₃ , and the negative terminal of the capacitor C _2P is linked The switch S ₁₁ is connected to the output terminal V _outP , one path is connected to the positive terminal of the capacitor C _3P through the linkage switch S ₁₀ , and the negative terminal of the capacitor C _3P is connected to the output terminal V _outP through the linkage switch S ₃ ; there are linkage switches at both ends of the capacitor C _3P S ₉ , the positive pole of capacitor C _3P is grounded through linkage switch S ₈ ;

V _inN is connected to the negative pole of capacitor C _1N through the linkage switch S ₁ , and the positive pole of C _1N is divided into four circuits through the linkage switch S _4. One path is connected to the non-inverting input terminal of the op amp through the linkage switch Sw ₂ , and the other path is connected to the op amp reverse terminal through the linkage switch Sw ₁ . Phase input terminal; one path is connected to the positive terminal of capacitor C _2N through linkage switch S ₁₃ , the negative terminal of capacitor C _2N is connected to output terminal V _outN through linkage switch S ₁₁ , one path is connected to the positive terminal of capacitor C _3N through linkage switch S ₁₀ , and the capacitor The negative terminal of C _3N is connected to the output terminal V _outN through the linkage switch S ₃ ; the linkage switch S ₉ is indirectly connected to both ends of the capacitor C _3N , and the positive pole of the capacitor C _3N is grounded through the linkage switch S ₈ ;

The positive pole of C _1N and the positive pole of C _1P are respectively grounded through the linkage switch S ₅ , the negative pole of C _1N and the negative pole of C _1P are respectively grounded through the linkage switch S ₂ ; the negative pole of C _1N and the negative pole of C _1P are respectively connected to the output terminal V through the grounding of the linkage switch S _{3 outN} , V _outP ;

The non-inverting and inverting input terminals of the operational amplifier are respectively connected to the negative and positive output terminals of the operational amplifier through the linkage switch _S1 ; the negative output terminals of the operational amplifier are respectively connected to the output terminals V _outP and V _outN through the linkage switches Sw ₁ and Sw ₂ ; The positive output terminals of the operational amplifier are respectively connected to the output terminals V _outN and V _outP through the linkage switches Sw ₁ and Sw ₂ ;

V _DAC+ of the DAC is connected to the negative terminals of capacitor C _1P and capacitor C _3P through linkage switches S ₆ and S ₇ respectively;

V _DAC- of the DAC is connected to the negative terminals of capacitor C _1N and capacitor C _3N through linkage switches S ₆ and S ₇ respectively;

The 1.5bit sub-ADC is respectively connected to the output terminals V _outN and V _outP .

The process offset-insensitive cyclic analog-to-digital conversion method is realized by means of the aforementioned converter, and includes the following steps:

By manipulating the linkage switches S ₁ -S ₁₃ and linkage switches S _w1 -S _w2 , the op amp can work in eight states in sequence:

a: V _inN and V _inp are respectively connected to the inverting and non-inverting input terminals of the op amp through the capacitors C _1N and C _1P respectively _. And grounded through the capacitor C _2N , the two ends of the capacitor C _3P and C _3N are shorted to the ground;

b: The ground is connected to the inverting and non-inverting input terminals of the op amp through the capacitors C _1N and C _1P , the non-inverting terminal of the op amp is connected to the negative feedback through the capacitor C _2P , the inverting terminal of the op amp is connected to the positive feedback through the capacitor C _2N , and the capacitor C _3P , C _3N both ends are shorted to ground;

c: The ground is connected to the inverting and non-inverting input terminals of the operational amplifier through capacitors C _{2N and} C _{2P .} The feedback terminals are respectively grounded through capacitors C _3P and C _3N ;

d: Capacitors C _1N and C _1P in b are replaced by capacitors C _3N and C _3P , and capacitors C _3N and C _3P correspond to capacitors C _1N and C _1P in b. The grounded plates are respectively connected to the positive and negative output V of the DAC _DAC+ , V _DAC- , capacitors C _1N , C _1P floating;

e: The non-inverting terminal of the operational amplifier is connected to the negative feedback through the capacitor C _1P , the inverting terminal of the operational amplifier is connected to the positive feedback through the capacitor C _1N , the positive and negative feedback terminals are respectively grounded through the capacitors C _3P and C _3N , and the capacitors C _2P and C _2N are floating ;

f: C _1P and C _3P , C _1N and C _3N in c are exchanged;

g: C _1P and C _3P , C _1N and C _3N in d are exchanged;

h: C _1P and C _3P , C _1N and C _3N in e are exchanged;

In the c state, the 1.5bit output of the first cycle is completed. In the f state, the 1.5bit output of the second cycle is completed. After the operation of the h state is completed, the operation of the c state is continued, that is, the third cycle is completed. 1.5bit output, and then continuously cycle from c state to h state until the required number of conversion bits is reached.

Technical characteristics and effects of the present invention:

Through the improved MDAC structure and control timing, the multiplied gain of the Cyclic ADC is independent of the ratio of the capacitor, and the positive and negative input and output terminals of the op amp are interchanged through the control of switches Sw1 and Sw2, thereby eliminating the offset voltage of the op amp. Ultimately, the output voltage value of each cycle of the Cyclic ADC is independent of the capacitance ratio and the offset of the operational amplifier, thereby reducing the sensitivity of the Cyclic ADC to process offsets, improving the linearity of the Cyclic ADC, and reducing its output offset.

Description of drawings

Figure 1 Schematic diagram of the structure of Cyclic ADC.

MDAC circuit structure in the Cyclic ADC described in the present invention of Fig. 2.

Fig. 3 is the timing diagram of Cyclic ADC control described in the present invention.

Fig. 4 is an equivalent circuit diagram of different states of the Cyclic ADC described in the present invention.

Detailed ways

The present invention improves the MDAC circuit structure in the Cyclic ADC, so that the gain accuracy multiplied by 2 has nothing to do with the mismatch of the capacitor, and eliminates the offset voltage introduced by the mismatch of the MOS device by flipping the positive and negative input and output of the op amp, thereby ensuring the stability of the circuit Under the premise, improve the linearity of Cyclic ADC and reduce its output offset, and reduce the sensitivity of Cyclic ADC to process offset.

The MDAC circuit structure in the Cyclic ADC described in the present invention is shown in Figure 2. The MDAC consists of a 1.5bit sub-ADC, a 1.5Bit sub-DAC, switches S ₁ -S ₁₃ , switches S _w1 -S _w2 and three sets of capacitors C _{1P, N} , C _{2P, N} , C _{3P, N} , where the two voltage sources V1 and V2 are used to simulate the equivalent input differential offset voltage of the op amp, and assume that the equivalent total offset voltage of the op amp is V _os . The control clock of this MDAC is shown in Figure 3. Under the control of this clock, the MDAC has eight states ah, and the equivalent circuit structures of these eight states are shown in Figure 4(a)-4(h). The working process of the Cyclic ADC described in the present invention is: in the c state of MDAC, the ADC completes the 1.5bit output of the first cycle, in the f state of MDAC, the ADC completes the 1.5bit output of the second cycle, and completes the h state of the MDAC After the operation, the operation of the c state is continued, that is, the 1.5bit output of the third cycle is completed, and then the MDAC is continuously cyclically transformed from the c state to the h state until the required number of conversion bits is reached. According to the charge conservation equation, the output expression when MDAC is in the c state can be obtained as:

V _outp1 -V _outn1 =V _inp -V _inn (1)

Also according to the charge conservation equation, the output expression of MDAC in f state can be obtained as:

V _outp2 -V _outn2 ＝2(V _outp1 -V _outn1 )-(V _DAC1 +-V _DAC1- ) (2)

Similarly, when MDAC enters the c state again, its output expression is:

V _outp3 -V _outn3 ＝2(V _outp2 -V _outn2 )-(V _DAC2+ -V _DAC2- ) (3)

It can be seen that MDAC completes the first cycle after passing through the three states a, b and c, and then completes a cycle every time it passes through the operations of three adjacent states until the required number of cycles is completed. It can be seen from formula 1-3 that the voltage value output by MDAC in each cycle is twice the output voltage value in the previous cycle, and this double gain has nothing to do with the capacitance ratio. In addition, the output of MDAC does not include the offset voltage of the op amp. .

The Cyclic ADC described in the present invention can work at a power supply voltage of 1.8V, and the usable positive and negative reference voltages Vrefp and Vrefn are 1.3V and 0.5V respectively, so the quantized input signal range is -0.8V~+0.8V. The capacitor in the MDAC can be a MIM capacitor with a size of 200fF. The operation time of each state of the MDAC is 100ns, and a 10-bit digital signal is output after 10 effective cycles. Because each finite-cycle MDAC needs to go through three-state operations, it takes 3 μs for the Cyclic ADC to complete a 10-bit analog-to-digital conversion, that is, the conversion time is 3 μs. The power consumption of Cyclic ADC is about 220μW.

Claims (2)

1. A non-sensitive circulating analog-to-digital converter of process offset, carries out analog-to-digital conversion and cycle by 2 operation by multiplication digital-to-analog converter, is characterized in that, also comprises digital correction circuit, register; Multiplication digital-to-analog converter is composed of Composed of 1.5bit sub-ADC, DAC, linkage switches S ₁ -S ₁₃ , linkage switches S _w1 -S _w2 and capacitors C _1P , C _1N , C _2P , C _2N , C _3P , and C _3N , V _inp passes through linkage switch S ₁ Connect to the negative pole of capacitor C _1P , and the positive pole of C _1P is divided into four circuits through the linkage switch _S4 , one path is connected to the non-inverting input terminal of the op amp through the linkage switch Sw ₁ , one path is connected to the inverting input terminal of the op amp through the linkage switch Sw ₂ , and one path is connected to the inverting input terminal of the op amp through the linkage switch Sw 2. The switch S ₁₃ is connected to the positive terminal of the capacitor C _2P , the negative terminal of the capacitor C _2P is connected to the output terminal V _outP through the linkage switch S ₁₁ , one path is connected to the positive terminal of the capacitor C _3P through the linkage switch S ₁₀ , and the negative terminal of the capacitor C _3P is connected to the linkage switch S ₃ is connected to the output terminal V _outP ; there is a linkage switch S ₉ indirectly at both ends of the capacitor C _3P , and the positive pole of the capacitor C _3P is grounded through the linkage switch S ₈ ; V _inN is connected to the negative pole of capacitor C _1N through the linkage switch S ₁ , and the positive pole of C _1N is divided into four circuits through the linkage switch S _4. One path is connected to the non-inverting input terminal of the op amp through the linkage switch Sw ₂ , and the other path is connected to the op amp reverse terminal through the linkage switch Sw ₁ . Phase input terminal; one path is connected to the positive terminal of capacitor C _2N through linkage switch S ₁₃ , the negative terminal of capacitor C _2N is connected to output terminal V _outN through linkage switch S ₁₁ , one path is connected to the positive terminal of capacitor C _3N through linkage switch S ₁₀ , and the capacitor The negative terminal of C _3N is connected to the output terminal V _outN through the linkage switch S ₃ ; the linkage switch S ₉ is indirectly connected to both ends of the capacitor C _3N , and the positive pole of the capacitor C _3N is grounded through the linkage switch S ₈ ; The positive pole of C _1N and the positive pole of C _1P are respectively grounded through the linkage switch S ₅ , the negative pole of C _1N and the negative pole of C _1P are respectively grounded through the linkage switch S ₂ ; the negative pole of C _1N and the negative pole of C _1P are respectively connected to the output terminal V _outN through the linkage switch S ₃ , V _outP ; The non-inverting and inverting input terminals of the operational amplifier are respectively connected to the negative and positive output terminals of the operational amplifier through the linkage switch _S1 ; the negative output terminals of the operational amplifier are respectively connected to the output terminals V _outP and V _outN through the linkage switches Sw ₁ and Sw ₂ ; The positive output terminals of the operational amplifier are respectively connected to the output terminals V _outN and V _outP through the linkage switches Sw ₁ and Sw ₂ ; V _DAC + of the DAC is respectively connected to the negative terminals of capacitor C _1P and capacitor C _3P via linkage switches S ₆ and S ₇ ; The V _DAC of the DAC is connected to the negative terminals of the capacitor C _1N and the capacitor C _3N through the linkage switches S ₆ and S ₇ respectively; The 1.5bit sub-ADC is respectively connected to the output terminals V _outN and V _outP . 2. A non-sensitive cyclic analog-to-digital conversion method for process imbalance, characterized in that it is realized by means of the aforementioned converter, and comprises the steps: By manipulating the linkage switches S ₁ -S ₁₃ and linkage switches S _w1 -S _w2 , the op amp can work in eight states in sequence: a: V _inN and V _inp are respectively connected to the inverting and non-inverting input terminals of the op amp through the capacitors C _1N and C _1P respectively _. And grounded through the capacitor C _2N , the two ends of the capacitor C _3P and C _3N are shorted to the ground; b: The ground is connected to the inverting and non-inverting input terminals of the op amp through the capacitors C _1N and C _1P , the non-inverting terminal of the op amp is connected to the negative feedback through the capacitor C _2P , the inverting terminal of the op amp is connected to the positive feedback through the capacitor C _2N , and the capacitor C _3P , C _3N both ends are shorted to ground; c: The ground is connected to the inverting and non-inverting input terminals of the operational amplifier through capacitors C _{2N and} C _{2P .} The feedback terminals are respectively grounded through capacitors C _3P and C _3N ; d: Capacitors C _1N and C _1P in b are replaced by capacitors C _3N and C _3P , and capacitors C _3N and C _3P correspond to capacitors C _1N and C _1P in b. The grounded plates are respectively connected to the positive and negative output V of the DAC _DAC+ , V _DAC- , capacitors C _1N , C _1P floating; e: The non-inverting terminal of the operational amplifier is connected to the negative feedback through the capacitor C _1P , the inverting terminal of the operational amplifier is connected to the positive feedback through the capacitor C _1N , the positive and negative feedback terminals are respectively grounded through the capacitors C _3P and C _3N , and the capacitors C _2P and C _2N are floating ; f: C _1P and C _3P , C _1N and C _3N in c are exchanged; g: C _1P and C _3P , C _1N and C _3N in d are exchanged; h: C _1P and C _3P , C _1N and C _3N in e are exchanged; In the c state, the 1.5bit output of the first cycle is completed. In the f state, the 1.5bit output of the second cycle is completed. After the operation of the h state is completed, the operation of the c state is continued, that is, the third cycle is completed. 1.5bit output, and then continuously cycle from c state to h state until the required number of conversion bits is reached.

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