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CN103109361A - Glue filling method and device in the semiconductor package - Google Patents

Glue filling method and device in the semiconductor package Download PDF

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CN103109361A
CN103109361A CN2011800044822A CN201180004482A CN103109361A CN 103109361 A CN103109361 A CN 103109361A CN 2011800044822 A CN2011800044822 A CN 2011800044822A CN 201180004482 A CN201180004482 A CN 201180004482A CN 103109361 A CN103109361 A CN 103109361A
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primer
substrate
flow
gap
coated
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CN103109361B (en
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金鹏
卢基存
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Peking University Shenzhen Graduate School
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    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
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Abstract

提供一种半导体器件封装中的底胶(4)填充方法和设备。底胶(4)被涂布基板上半导体器件或芯片的一边或多至四边,然后底胶(4)在芯片和基板之间的间隙流动直至填满该间隙。多个边缘涂有底胶(4)的器件移到真空烤箱里,底胶(4)在多个器件中同时进行批处理流动,从而减少总体的底胶(4)填充时间,大大提高生产效率。最后底胶(4)在真空炉烤箱中固化,消除了因底胶(4)流动形成气泡和底胶(4)本身固化时气体挥发等原因引起的空洞,提高了器件底胶(4)填充的质量和可靠性。

Figure 201180004482

Provided are a method and equipment for filling a primer (4) in a semiconductor device package. The primer (4) is coated on one side or up to four sides of the semiconductor device or chip on the substrate, and then the primer (4) flows in the gap between the chip and the substrate until the gap is filled. Multiple devices coated with primer (4) on the edges are moved into a vacuum oven, and the primer (4) is batch-processed and flowed among multiple devices at the same time, thereby reducing the overall primer (4) filling time and greatly improving production efficiency . Finally, the primer (4) is cured in a vacuum oven, which eliminates the voids caused by the formation of bubbles due to the flow of the primer (4) and the volatilization of the gas when the primer (4) itself is cured, and improves the filling of the device primer (4). quality and reliability.

Figure 201180004482

Description

一种半导体封装中的底胶填充方法及设备 Method and equipment for filling primer in semiconductor packaging 技术领域technical field

本发明涉及一种半导体封装中的底胶填充方法及设备。 The invention relates to a primer filling method and equipment in semiconductor packaging.

背景技术Background technique

表面贴装是目前将电子器件组装在基板或印刷电路板PCB的最流行的封装方法之一。在这种封装中,表面贴装器件与基板采用多元化金属焊点(如铅锡合金)互连,在贴装器件与基板之间存在间隙。如果贴装器件与基板热膨胀系数(CTE)不同,在温度变化时焊点中会产生应力和应变,使用过程中器件温度变化产生的应力和应变将导致焊点疲劳断裂而失效。要解决这种可靠性问题,电子行业的共同做法是在器件与基板间隙填充底胶材料,从而减少焊点的变形和应变,提高焊点的可靠性寿命,底胶的封装过程通常被称为底部填充。Surface mount is currently one of the most popular packaging methods for assembling electronic devices on a substrate or printed circuit board (PCB). In this package, the surface mount device is interconnected with the substrate using multiple metal solder joints (such as lead-tin alloy), and there is a gap between the mounted device and the substrate. If the thermal expansion coefficient (CTE) of the mounted device is different from that of the substrate, stress and strain will be generated in the solder joint when the temperature changes, and the stress and strain generated by the temperature change of the device during use will lead to fatigue fracture of the solder joint and failure. To solve this reliability problem, the common practice in the electronics industry is to fill the gap between the device and the substrate with primer material, thereby reducing the deformation and strain of the solder joints and improving the reliability of the solder joints. The packaging process is usually called Bottom padding.

需要底部填充的电子器件例子包括倒装芯片,芯片级封装(CSP)和球格阵列(BGA)封装等。其它形式的封装中的空气间隙(如电子器件叠加间的空隙)也可能需要填充底胶。在倒装芯片封装中,半导体芯片的有源面是“翻转”,通过球形焊点直接安装在印刷电路基板上。该芯片材料是硅、砷化镓等,其 CTE为2-4ppm/ ℃ ,基板材料是有机物(如FR-4、聚酰亚胺和BT, CTE为20ppm/ ℃ )或者无机材料(如氧化铝及低温共烧陶瓷,CTE为3-10 ppm/ ℃ ),由于芯片和基板之间热膨胀系数不匹配,工作中的温度变化会导致焊点上产生疲劳应力和应变,其结果是焊点断裂和焊点开路的发生。通常的做法是在芯片与基板的间隙处填充聚合物底胶。底胶填充有助于分散应力,减少焊接接头应变,从而提高焊点可靠性。在芯片级封装(CSP)和球格阵列(BGA)封装中,半导体芯片安装在由BT等材料制成的基板,基板再通过焊点与印刷电路板PCB连接。基板与印刷电路板的热膨胀系数不同, 它们之间的间隙也需要底胶填充,同时底胶填充可以大大提高焊点抵抗外部机械应力(如手机器件摔掉到地上时所受的应力)的能力。 Examples of electronic devices that require underfill include flip chip, chip scale package (CSP) and ball grid array (BGA) packages, among others. Air gaps in other forms of packaging, such as those between stacked electronics, may also require underfill. In flip-chip packaging, the active side of the semiconductor chip is "flipped" and mounted directly on the printed circuit substrate via solder balls. The chip material is silicon, gallium arsenide, etc., its CTE is 2-4ppm/ ℃, the substrate material is organic (such as FR-4, polyimide and BT, CTE is 20ppm/ ℃ ) or inorganic materials (such as alumina and low-temperature co-fired ceramics, CTE is 3-10 ppm/ ℃ ), due to the thermal expansion coefficient mismatch between the chip and the substrate, temperature changes during operation can cause fatigue stress and strain on the solder joints, resulting in solder joint fractures and solder joint open circuits. A common practice is to fill the gap between the chip and the substrate with a polymer primer. Primer filling helps distribute stress and reduce solder joint strain, thereby improving solder joint reliability. In Chip Scale Package (CSP) and Ball Grid Array (BGA) packages, the semiconductor chip is mounted on a substrate made of BT and other materials, and the substrate is then connected to the printed circuit board PCB through solder joints. The thermal expansion coefficient of the substrate and the printed circuit board are different, The gap between them also needs to be filled with primer, and the primer filling can greatly improve the ability of solder joints to resist external mechanical stress (such as the stress suffered when mobile phone components are dropped to the ground).

底胶填充是一个非常耗时的过程,尽管已出现多种底胶填充工艺如无流动与晶圆级工艺,但传统的毛细管流动底胶填充工艺在今天的工业界仍占主导地位。在传统的毛细管流动底胶填充工艺中,用针孔或喷嘴将液态的底胶材料涂在印刷电路板PCB或基板上的贴装器件四周,加热基板至一个底胶可以流动的温度(如70-90摄氏度)以降低底部填充胶的粘度。在毛细管力驱动下,底胶流动并填充器件与基板的间隙,以上工艺过程都是在点胶设备上的加热台上完成的。尽管底胶点滴的时间只需要一秒或更短,但是底胶流动及填充间隙(如0.05 - 0.15毫米的倒装芯片和为0.3 - 0.8毫米CSP)需要的时间较长。例如要填充一个10毫米的器件/基板间隙,底部填充流动的时间超过15秒,更大器件和更小间隙的底胶填充需要的时间更长。假设液态的底胶为牛顿液态,流动过程为二维层流,根据Navier-Stokos 方程,底胶的流动时间t为t= (3µL^2)/hrcosθ。其中µ是底胶的粘滞系数,L是流动距离,h是流动间隙高度,θ是底胶与基板的接触角度。底胶填充需要较长时间的原因除了单个器件中底胶的毛细血管流动速度慢以外,另一个主要原因是点胶机加热台的空间有限,器件又得在加热台上底胶流动结束后才能被移出点胶机,因而无法同时批处理大量器件,生产效率(以每小时底胶填充的器件UPH计)很低。底胶材料充满间隙之后,整个封装器件再移出点胶机, 到一个空气压力的烤箱和回流炉中以较高的底胶固化温度(如125-165 ℃ )进行加热固化,固化时间和温度取决于底部填充材料的性质。Underfill filling is a very time-consuming process. Although various underfill processes such as no-flow and wafer-level processes have emerged, the traditional capillary flow underfill process still dominates the industry today. In the traditional capillary flow primer filling process, the liquid primer material is applied around the printed circuit board PCB or the mounting device on the substrate with a pinhole or nozzle, and the substrate is heated to a temperature at which the primer can flow (such as 70 -90°C) to reduce the viscosity of the underfill. Driven by capillary force, the primer flows and fills the gap between the device and the substrate. The above processes are all completed on the heating table on the dispensing equipment. Although it takes only one second or less for the primer to drip, the primer will flow and fill the gap (such as 0.05 - 0.15 mm for flip-chip and 0.3- 0.8 mm CSP) takes longer. For example, to fill a 10mm device/substrate gap, the underfill flow time exceeds 15 seconds, and larger devices and smaller gaps take longer. Assuming that the liquid primer is a Newtonian liquid, the flow process is a two-dimensional laminar flow, according to Navier-Stokos Equation, the flow time t of primer is t= (3µL^2)/hrcosθ. where µ is the viscosity coefficient of the primer, L is the flow distance, h is the flow gap height, and θ is the contact angle between the primer and the substrate. The reason why the primer filling takes a long time is not only the slow capillary flow rate of the primer in a single device, but another main reason is that the space of the heating table of the dispenser is limited, and the device must be finished after the primer flow on the heating table. It is removed from the dispenser, so it is impossible to batch process a large number of devices at the same time, and the production efficiency (in UPH of devices filled with primer per hour) is very low. After the primer material fills the gap, the entire packaged device is moved out of the dispenser, Heat and cure in an air pressure oven and reflow oven at a higher primer curing temperature (such as 125-165 ℃). The curing time and temperature depend on the properties of the underfill material.

阻碍毛细管流动底胶填充工艺广泛运用的因素除了上述的工艺耗时长, 特别是底胶流动并填满器件与基板间隙所需要的时间过长之外,且底胶流动填充过程是一个一个器件单独完成,空洞发生从而影响底胶填充的质量和可靠性也是因素之一。下面对此进行说明。Factors hindering the widespread use of capillary flow primer filling process In addition to the long time-consuming process mentioned above, In particular, the time required for the primer to flow and fill the gap between the device and the substrate is too long, and the filling process of the primer flow is completed one by one, and the occurrence of voids is also one of the factors that affect the quality and reliability of the primer filling. . This is explained below.

毛细管流动底胶填充工艺的另一个主要问题是底胶材料中存在空洞,特别是对大的器件,较小的器件与基板间隙、以及较多焊点器件而言,空洞问题更为严重。液态的底胶材料在器件与基板的间隙中流动是不均匀的,在有焊点的区域流动速度变化,同时在靠近器件边缘的流动往往比中间快,另外器件和基板的表面环境变化如助焊剂和残留物的存在都可以改变底胶的流动速度。在底胶流动快与流动慢的区域之间就会出现气泡,气泡在底胶固化后就成为空洞。空洞的存在不仅改变了底胶体积,而且形成了底胶内部的压力集中点,同时湿气易在空洞中聚集,对器件的可靠性产生不良的影响。Another major problem with the capillary flow primer filling process is the presence of voids in the primer material, especially for large devices, small device-to-substrate gaps, and devices with many solder joints. The flow of liquid primer material in the gap between the device and the substrate is uneven, and the flow speed changes in the area with solder joints. At the same time, the flow near the edge of the device is often faster than the middle. In addition, the surface environment of the device and the substrate changes. The presence of flux and residue can alter the flow rate of the primer. Bubbles will appear between the fast-flowing and slow-flowing areas of the primer, and the bubbles will become cavities after the primer cures. The existence of voids not only changes the volume of the primer, but also forms a pressure concentration point inside the primer. At the same time, moisture is easy to accumulate in the voids, which has a negative impact on the reliability of the device.

以往的专利已经有一些提高底胶填充工艺效率和空洞的方法和设备。工艺效率的提高主要是利用真空吸附或空气压力提高单个器件中底胶的流动速度,减少底胶填充的时间。Previous patents have addressed methods and apparatus for improving the efficiency and voiding of the primer filling process. The improvement of process efficiency is mainly to use vacuum adsorption or air pressure to increase the flow rate of primer in a single device and reduce the filling time of primer.

美国专利6,048,656《Void-free underfill of surface mounted chips》阐述了一种底胶的真空吸附工艺和设备,基板上贴装的半导体器件边缘用阻挡材料密封起来,留下一个底胶入口以及一个出口。在出口处抽真空,加速底胶的流动,并去除器件与基板间的空气,减少最后底胶中的空洞。阻挡层和真空的吸附工具需要根据器件的大小而改变。类似的真空吸附工艺是在美国专利7,791,209B2《Method of underfill air vent for flipchip BGA》中,不同的是底胶是通过在基板的中央钻出的一个小孔流出。底胶在器件边缘涂布,通过真空快速从基板的小孔中吸附出来。主要的工艺困难在于需要在基板钻孔以及需要额外设备收集真空吸附出来的底胶。 US Patent 6,048,656 "Void-free underfill of surface mounted "chips" describes a vacuum adsorption process and equipment for the primer. The edge of the semiconductor device mounted on the substrate is sealed with a barrier material, leaving an inlet and an outlet for the primer. Vacuum is drawn at the outlet to accelerate the flow of the primer and remove the air between the device and the substrate, reducing the voids in the final primer. The adsorption tools for the barrier layer and vacuum need to be changed according to the size of the device. A similar vacuum adsorption process is described in U.S. Patent 7,791,209B2 "Method of underfill air vent for flipchip In BGA", the difference is that the primer flows out through a small hole drilled in the center of the substrate. The primer is applied on the edge of the device and is quickly absorbed from the small holes in the substrate by vacuum. The main process difficulty lies in the need to drill holes in the substrate and the need for additional equipment to collect the primer that is vacuum adsorbed.

另外一个提高底胶流动速度和减少气泡的方法是提高器件外部的空气压力。美国专利5,203,076《Vacuum infiltration of underfill material for flip-chip devices》阐述了在倒装芯片基板上加一个空腔盖子,芯片周围涂布底胶后,先对空腔抽真空然后加压,驱动底胶的流动,该方法的一个缺点是同时需要真空和加压设备。另一个利用底胶流动两侧空气压力不同驱动底胶流动的专利是美国专利6,895,666 B2《Underfill system for semiconductor package》,在器件的底胶出口处通过空气流动造成一个低压,整个工艺设备也较复杂。Another way to increase primer flow rate and reduce air bubbles is to increase the air pressure outside the device. US Patent 5,203,076 "Vacuum infiltration of underfill material for flip-chip "devices" describes adding a cavity cover on the flip-chip substrate. After coating the primer around the chip, the cavity is first vacuumed and then pressurized to drive the flow of the primer. A disadvantage of this method is that both vacuum and primer are required. pressurized equipment. Another patent that uses different air pressures on both sides of the primer flow to drive the primer flow is US Patent 6,895,666 B2 "Underfill system for semiconductor package", a low pressure is created by air flow at the primer outlet of the device, and the entire process equipment is also more complicated.

一些以往的发明专利仅仅减少底胶中的空洞。美国专利5,998,242《Vacuum assisted underfill process and apparatus for semiconductor package fabrication》是关于在单个器件基板上放一个真空腔,底胶通过一个穿透真空腔的针管涂布在器件的周围,再填满器件与基板的间隙。真空环境有利于减少底胶中的气泡,但针对器件定制的真空腔以及特别的底胶涂布设备是该方法的难点。美国专利6,653,172《Methods for providing void-free layers for semiconductor assemblies》说明了加压去除底胶气泡的方法, 同样需要特别的加压设备。 Some previous patented inventions only reduce voids in the primer. US Patent 5,998,242 "Vacuum assisted underfill process and apparatus for semiconductor package "fabrication" is about placing a vacuum chamber on a single device substrate. The primer is coated around the device through a needle that penetrates the vacuum chamber, and then fills the gap between the device and the substrate. The vacuum environment is beneficial to reduce the air bubbles in the primer, but the vacuum chamber customized for the device and the special primer coating equipment are the difficulties of this method. US Patent 6,653,172 "Methods for providing void-free layers for semiconductor assemblies" explains the method of removing the bubbles of the primer under pressure, Special pressurization equipment is also required.

综上所述,以往的发明主要是减少单个电子器件的底胶流动时间来提高工艺的效率。一个小空腔压在器件的基板上,空腔内的真空或高压加速器件周围底胶的流动和减少底胶中的气泡。它们有一些主要的工艺和设备的难点,需要针对器件的大小等特性定制空腔,器件改变以后,空腔的设计需要随之改变。另一个缺点是虽然底胶流动时间减少了, 但需要时间在器件基板上放空腔以及抽真空或加压。最主要的是底胶填充仍是一个器件接一个器件完成,总体工艺效率不高。因此迫切需要工艺和设备简单通用,并同时能达到高效率和无空洞的底胶填充方法。To sum up, previous inventions mainly reduce the primer flow time of a single electronic device to improve the efficiency of the process. A small cavity is pressed against the substrate of the device, and the vacuum or high pressure in the cavity accelerates the flow of primer around the device and reduces the air bubbles in the primer. They have some major process and equipment difficulties. The cavity needs to be customized according to the size and other characteristics of the device. After the device is changed, the design of the cavity needs to be changed accordingly. Another disadvantage is that while primer flow times are reduced, But it takes time to vent the cavity and evacuate or pressurize the device substrate. The most important thing is that underfill filling is still done one device after another, and the overall process efficiency is not high. Therefore, there is an urgent need for a primer filling method that is simple and versatile in process and equipment, and can achieve high efficiency and no voids at the same time.

技术问题technical problem

本发明要解决的主要技术问题是,提供一种半导体器件封装中的底胶填充方法及设备,能够缩短底胶填充工艺的耗时。本技术以半导体器件为例,但同样也可以用于其它如光电子等需要底胶填充工艺甚至顶部灌胶的器件。 The main technical problem to be solved by the present invention is to provide a primer filling method and equipment in semiconductor device packaging, which can shorten the time consumption of the primer filling process. This technology takes semiconductor devices as an example, but it can also be used for other devices such as optoelectronics that require underfill filling process or even top glue filling.

技术解决方案technical solution

为解决上述技术问题,本发明采用了如下技术方案: In order to solve the problems of the technologies described above, the present invention adopts the following technical solutions:

一种半导体封装中的底胶填充方法,用于在基板与封装在所述基板上的半导体器件之间的间隙填充底胶,包括: A method for filling an underfill in a semiconductor package, used for filling an underfill in a gap between a substrate and a semiconductor device packaged on the substrate, comprising:

底胶涂布:利用底胶涂布机器在所述基板上的半导体器件边缘涂布底胶; Primer coating: using a primer coating machine to coat the edge of the semiconductor device on the substrate with a primer;

底胶流动:将涂布好底胶的所述基板转移到烤箱中,以底胶流动温度进行加热,直至底胶填充到所述基板与所述半导体器件之间的间隙; Primer flow: transfer the substrate coated with primer to an oven, and heat at the primer flow temperature until the primer fills the gap between the substrate and the semiconductor device;

底胶固化:以底胶固化温度进行加热直至所述底胶固化。 Primer curing: heating at the primer curing temperature until the primer is cured.

在本发明的一种实施例中,在所述底胶流动时,维持所述烤箱内为真空环境。 其优点是底胶中无空洞,真空炉在底胶填充间隙之前就将器件与基板间的空气排空。即使是在进入真空炉前底胶就已经填充了间隙,只要底胶未固化则真空炉也会将底胶中的气泡驱除。因此,本发明对无气泡底胶填充的工艺窗口是很大的。 In one embodiment of the present invention, when the primer is flowing, a vacuum environment is maintained inside the oven. The advantage is that there are no voids in the primer, and the vacuum furnace evacuates the air between the device and the substrate before the primer fills the gap. Even if the primer has filled the gap before entering the vacuum furnace, as long as the primer is not cured, the vacuum furnace will drive out the air bubbles in the primer. Therefore, the process window of the present invention for bubble-free primer filling is very large.

在本发明的一种实施例中,底胶涂布时,以对称方式沿所述半导体器件四周涂布所述底胶。 In one embodiment of the present invention, when coating the primer, the primer is coated along the periphery of the semiconductor device in a symmetrical manner.

在本发明的一种实施例中,在所述底胶流动时,所述基板被倾斜放在所述烤箱内,以及在所述底胶流动之前,在所述半导体器件表面先覆盖一层非粘性层。 In one embodiment of the present invention, when the primer is flowing, the substrate is placed in the oven obliquely, and before the primer flows, a layer of non-woven fabric is first covered on the surface of the semiconductor device. sticky layer.

在本发明的一种实施例中,所述底胶包括液态底胶、固态底胶或者糊态底胶。 In one embodiment of the present invention, the primer includes a liquid primer, a solid primer or a paste primer.

在本发明的一种实施例中,液态底胶时,采用点滴工艺涂布到所述基板上; 固态底胶时,采用加热针管涂布和固体块放置的方法涂布到所述基板上;糊态底胶时,采用印刷工艺或针管涂布到所述基板上 。 In one embodiment of the present invention, when the liquid primer is used, it is applied to the substrate by a dripping process; In the case of solid primer, it is applied to the substrate by heating needle tube coating and solid block placement; in the case of paste primer, it is coated on the substrate by printing process or needle tube.

在本发明的一种实施例中,在所述底胶流动和底胶固化中,采用批处理方式同时对多块基板进行底胶流动和固化。 In an embodiment of the present invention, in the flow and curing of the primer, a batch process is adopted to simultaneously flow and cure the primer for multiple substrates.

本发明也提供了一种半导体封装中的底胶填充设备,用于在基板与封装在所述基板上的半导体器件之间的间隙填充底胶,包括: The present invention also provides a primer filling device in a semiconductor package, which is used for filling the gap between a substrate and a semiconductor device packaged on the substrate, including:

底胶涂布机,在所述基板上的半导体器件边缘涂布底胶; A primer coating machine for coating the primer on the edge of the semiconductor device on the substrate;

烤箱用于以底胶流动温度对置入其中的涂布好底胶的所述基板上的底胶进行加热,直至底胶填充到所述基板与所述半导体器件之间的间隙;以及以底胶固化温度对所述底胶进行加热直至所述底胶固化。 The oven is used to heat the primer on the substrate coated with primer placed therein at the flow temperature of the primer until the primer fills the gap between the substrate and the semiconductor device; Glue curing temperature The primer is heated until the primer is cured.

在本发明的一种实施例中,所述 用于进行底胶流动的 烤箱为真空烤箱或真空回流炉。 In one embodiment of the present invention, the oven used for the primer flow is a vacuum oven or a vacuum reflow oven.

在本发明的一种实施例中,所述 用于底胶固化的 烤箱为热板、传统烤箱或回流炉。 In one embodiment of the present invention, the oven used for curing the primer is a hot plate, a conventional oven or a reflow oven.

本发明可以有效缩短底胶流动所需时间,从而从整体上减少底胶填充工艺的耗时。 The invention can effectively shorten the time required for the primer to flow, thereby reducing the time consumption of the primer filling process as a whole.

附图说明Description of drawings

图 1是当前工业界普遍采用的毛细管流动底胶填充工艺图;其中,图1A 是在点胶机上液态底胶涂布工艺图;图1B是在点胶机上底胶流动填充芯片与基板间隙图;基板温度保持在底胶流动所需要的温度(如70-90℃);图1C是底胶固化图;固化温度通常在一个更高的温度(如125-165℃);Figure 1 is a capillary flow primer filling process diagram commonly used in the current industry; wherein, Figure 1A It is a drawing of the coating process of liquid primer on the dispenser; Figure 1B is a diagram of the flow of the primer on the dispenser to fill the gap between the chip and the substrate; the temperature of the substrate is kept at the temperature required for the flow of the primer (such as 70-90°C); 1C is the primer curing map; the curing temperature is usually at a higher temperature (such as 125-165°C);

图2是本发明实施例中的毛细管流动底胶填充工艺图;其中,图2A是在点胶机上液体底胶涂布工艺图;图2B是在烤箱中(真空烤箱或真空回流炉,温度70-90℃)底胶流动填充芯片与基板的间隙图;图2C是在烤箱中(真空烤箱或真空回流炉)底胶固化图;Fig. 2 is the capillary flow primer filling process diagram in the embodiment of the present invention; Wherein, Fig. 2A is the liquid primer coating process diagram on the glue dispenser; Fig. 2B is in the oven (vacuum oven or vacuum reflow oven, temperature 70 -90°C) primer flowing to fill the gap between the chip and the substrate; Figure 2C is a graph of primer curing in an oven (vacuum oven or vacuum reflow oven);

图 3是沿器件四周底胶对称涂布工艺图;其中,图3A是底胶沿器件四周均匀涂布的俯视图;图3B 是底胶沿器件四周均匀涂布的截面图。Fig. 3 is a symmetric coating process diagram of the bottom glue along the device; wherein, Fig. 3A is a top view of the bottom glue uniformly coated along the device; Fig. 3B is a cross-sectional view of primer uniformly applied around the device.

本发明的实施方式Embodiments of the present invention

下面通过具体实施方式结合附图对本发明作进一步详细说明。The present invention will be further described in detail below through specific embodiments in conjunction with the accompanying drawings.

本发明涉及半导体封装等器件中底胶填充的方法与设备。本文中的封装是指利用焊料等连接粘结材料将一个或多个半导体封装器件与印刷电路板基板互连或器件之间的互连。参见图1,传统的底胶填充是在一台机器上将底胶涂在封装元器件边缘,底胶再在空气环境下通过毛细血管作用流动并填充到衬底与器件之间的间隙,最后底胶在传统的空气加热炉中固化。传统方法主要缺点是单个元器件的底胶流动工艺时间长或生产效率低,以及因在空气中流动底胶材料而容易出现空洞。为此,参见图2,本发明给出了一种高效率无空洞的底胶填充方法及设备,具体如下:The invention relates to a method and equipment for filling primers in semiconductor packaging and other devices. Packaging herein refers to the interconnection of one or more semiconductor package devices with a printed circuit board substrate or interconnection between devices using solder and other bonding materials. Referring to Figure 1, the traditional primer filling is to apply the primer on the edge of the packaged components on a machine, and then the primer flows through capillary action in the air environment and fills the gap between the substrate and the device, and finally The primer is cured in a conventional air-heated oven. The main disadvantages of the traditional method are the long time or low production efficiency of the primer flow process for a single component, and the easy occurrence of voids due to the flow of the primer material in the air. For this reason, referring to Fig. 2, the present invention provides a kind of high-efficiency void-free primer filling method and equipment, specifically as follows:

一种半导体封装中的底胶填充方法,用于在基板与封装在所述基板上的半导体器件之间的间隙填充底胶,包括:A method for filling an underfill in a semiconductor package, used for filling an underfill in a gap between a substrate and a semiconductor device packaged on the substrate, comprising:

底胶涂布:利用底胶涂布机器在所述基板上的半导体器件边缘涂布底胶;Primer coating: using a primer coating machine to coat the edge of the semiconductor device on the substrate with a primer;

底胶流动:将涂布好底胶的所述基板转移到烤箱中,以底胶流动温度进行加热,直至底胶填充到所述基板与所述半导体器件之间的间隙;Primer flow: transfer the substrate coated with primer to an oven, and heat at the primer flow temperature until the primer fills the gap between the substrate and the semiconductor device;

底胶固化:以底胶固化温度进行加热直至所述底胶固化。Primer curing: heating at the primer curing temperature until the primer is cured.

可以看到,在底胶填充工艺流程中,包括底胶涂布过程、底胶流动过程、底胶固化过程,下面分别予以说明。It can be seen that the primer filling process includes the primer coating process, the primer flow process, and the primer curing process, which will be described separately below.

1、底胶涂布 1. Primer coating

现有技术中所用的底胶一般为液态底胶,是用胶针或喷泵和控制龙门沿器件上两侧进行涂布。Asymtek公司的C-720就是液体底胶涂布机的一个例子。The primer used in the prior art is generally a liquid primer, which is coated along both sides of the device with a glue needle or a spray pump and a control gantry. Asymtek's C-720 is an example of a liquid primer applicator.

在本发明的一种实施例中,底胶可以包括液态底胶、固态底胶或者糊态底胶,即除了传统的液态底胶外,本发明还能运用糊态及固态底胶材料填充。一般的,液体底部填充材料是由机器点滴方法沿器件的边缘涂布到基板上,固体和糊状底部填充材料分别用直接放置和印刷或涂布到基板上器件的周围,底胶可以像传统的工艺一样放在器件的一边或两边,也可以放器件的三边或四边。并底胶涂布时,点胶机的加热板可以不加热或稍稍加热,目的是使底胶粘在器件的边缘。 因未被加热,底胶粘滞系数仍大,点胶机上本发明的目的是底胶在器件与基板之间的间隙不流动或流动距离较小。 In one embodiment of the present invention, the primer may include a liquid primer, a solid primer or a paste primer, that is, in addition to the traditional liquid primer, the present invention can also be filled with paste and solid primer materials. Generally, the liquid underfill material is applied to the substrate along the edge of the device by the machine drop method, and the solid and paste underfill materials are directly placed and printed or coated around the device on the substrate respectively. The underfill can be as traditional The same process can be placed on one or both sides of the device, and it can also be placed on three or four sides of the device. When coating the primer, the heating plate of the dispenser can be unheated or slightly heated, so that the primer sticks to the edge of the device. Because it is not heated, the viscosity coefficient of the primer is still large. The purpose of the present invention on the glue dispenser is that the primer does not flow or the flow distance is small in the gap between the device and the substrate.

用于填充的底胶另一种可能的状态时室温下为固体(例如环氧树脂)。环氧树脂的优点在于一旦被固化,粘度会非常低并具有高比例无机填充物(如80%的SiO2颗粒), 更高比例的填充物具有更低的热膨胀系数和更高的可靠性。Another possible state of the primer used for filling is solid at room temperature (such as epoxy resin). The advantage of epoxy resins is that once cured, the viscosity is very low and has a high proportion of inorganic fillers (such as 80% SiO2 particles), A higher proportion of filler has a lower coefficient of thermal expansion and higher reliability.

固体底胶涂布有两种方式:(1)加热的针管或喷嘴涂布(2)固态涂布。对于针管涂布,底胶在注射器中加热到一个中等温度熔化成液态。在涂布时,在针管针头附近加热使底胶沿着器件边缘点滴下来, 也可使用加热的喷嘴涂布。底胶落到室温或低温的基板上时便冷却凝固成固体。对于固态涂布方式,先将底胶固体定型成基底器件大小的条状,用机械手将条状底胶沿着器件放置。通常采用加热基板或在基板上涂一层粘结材料以确保底胶与基板的粘结。在采用糊状底胶时,可采用带孔的模板如钢板印刷到基板上, 也可用或喷嘴涂布。There are two methods of solid primer coating: (1) heated needle or nozzle coating (2) solid state coating. For needle coating, the primer is heated in a syringe to a moderate temperature to melt to a liquid state. When coating, heat near the needle of the needle so that the primer drips down along the edge of the device, Heated nozzle application is also possible. When the primer falls on the substrate at room temperature or low temperature, it cools and solidifies into a solid. For the solid-state coating method, the primer solid is first shaped into a strip of the size of the substrate device, and the strip primer is placed along the device with a manipulator. Usually heating the substrate or coating a layer of bonding material on the substrate to ensure the bonding of the primer to the substrate. When using a paste primer, a template with holes such as a steel plate can be used to print on the substrate. It can also be applied with or nozzle.

综上所述,本发明中的底胶涂布工艺与现有技术的底胶涂布工艺有以下3个不同点:In summary, the primer coating process among the present invention has the following 3 differences with the primer coating process of the prior art:

1、 本发明中的印刷电路板基材可以加热或不加热。在现有技术的工艺中,需要加热基板降低底胶黏度,促进底胶流动。在本发明中,可以不对基板加热或仅加热到低于底胶流动需要的温度(低于70-90 ℃ )。因此,基板上涂布的底胶温度低、粘度高,这减弱了底胶涂布工艺中底胶的流动性。1, The printed circuit board substrate in the present invention may or may not be heated. In the prior art process, it is necessary to heat the substrate to reduce the viscosity of the primer and promote the flow of the primer. In the present invention, the substrate may not be heated or only heated to a temperature lower than that required for primer flow (lower than 70-90 °C). Therefore, the temperature of the primer coated on the substrate is low and the viscosity is high, which weakens the fluidity of the primer in the primer coating process.

2、 现有工艺一般采用液态底胶,而本发明除液态底胶外,固态和糊状底胶也可以得到应用。2. The existing technology generally adopts liquid primer, but in the present invention, besides liquid primer, solid and pasty primer can also be applied.

3、 本发明中,底胶可以沿器件的四边进行涂布,然而在现有工艺中,底胶只沿器件的一边或两边涂布以减少气泡产生。因此,工艺工程师并不需要为尽量减小气泡而进行大量的实验,通过涂布方案和衬底温度来进行调节。涂布时,胶针截面可以为小方形,涂布时的一个重要参数是底胶体积,它等于器件与基板间隙的体积加上器件边缘需要的底胶体积。 3. In the present invention, the primer can be coated along the four sides of the device, but in the prior art, the primer is only coated along one side or two sides of the device to reduce air bubbles. Therefore, process engineers do not need to conduct extensive experimentation to minimize air bubbles, adjusted by coating scheme and substrate temperature. When coating, the cross section of the glue needle can be a small square. An important parameter during coating is the volume of the primer, which is equal to the volume of the gap between the device and the substrate plus the volume of the primer required at the edge of the device.

在本发明中,有可能会使器件表面上也被涂布底胶。因此,将器件倾斜地放在烤箱中使表面上的底胶流动到器件的侧墙并将器件与基板间的间隙填充完。为防止底胶粘附到器件的表面,器件上表面需先覆盖一层非粘性层,例如如聚四氟乙烯。In the present invention, it is possible to have a primer coated on the surface of the device as well. Therefore, placing the device at an angle in the oven allows the primer on the surface to flow to the sidewalls of the device and fill the gap between the device and the substrate. In order to prevent the primer from adhering to the surface of the device, the upper surface of the device needs to be covered with a non-adhesive layer, such as polytetrafluoroethylene.

底胶涂布到PCB基板后,则要进行底胶流动。与在点胶机上加热台上底胶流动工艺不同,本发明中底胶的流动和固化都是在空气或真空环境的烤箱中进行。该烤箱例如可以是一个独立的回流炉或具有三到七个加热区和一个移动带的烤箱。底胶在烤箱中流动与固化的温度曲线分两个阶段。第一阶段的底胶流动温度(例如70~90 ℃ )是降低底胶粘度促进底胶流动。一旦底胶填充好间隙,被加热到第二阶段的底胶固化温度(如140-165℃),固化时间长短取决与底胶的固化速率。只要底胶在固化前能填充间隙,可以采用超过2阶段烤箱温度曲线。After the primer is applied to the PCB substrate, the primer must flow. Different from the bottom glue flow process on the heating platform on the dispenser, the flow and curing of the bottom glue in the present invention are all carried out in an oven in air or vacuum environment. The oven can be, for example, a stand-alone reflow oven or an oven with three to seven heating zones and a moving belt. The temperature curve of the primer flowing and curing in the oven is divided into two stages. The primer flow temperature in the first stage (for example, 70-90 ℃ ) is to reduce the viscosity of the primer to promote the flow of the primer. Once the primer fills the gap, it is heated to the second stage primer curing temperature (eg 140-165°C), the curing time depends on the curing rate of the primer. More than a 2-stage oven profile can be used as long as the primer fills the gaps before curing.

在底胶流动时,对于不易引发气泡的小器件封装,采用简单的传统烤箱和回流炉即可。而对于容易引发气泡的大器件封装,为了防止底胶流动中会产生气泡,可以采用将烤箱内维持为真空环境的方式,例如采用真空烤箱、真空回流炉或真空室进行底胶流动和固化。When the primer is flowing, simple traditional ovens and reflow ovens can be used for small device packages that are not prone to causing air bubbles. For large device packages that are prone to bubbles, in order to prevent bubbles from forming during the flow of the primer, a method of maintaining a vacuum environment in the oven can be used, such as using a vacuum oven, a vacuum reflow oven or a vacuum chamber for the flow and curing of the primer.

例如,底胶涂布完过后,器件和PCB板将从涂布机器上转移到真空烤箱中。烤箱的起始温度为室温到底胶流动温度(例如70-90℃)之间的某个温度或底胶流动温度。随后,将烤箱升至底胶流动温度并保持一段时间直到底胶填充完器件与基板的间隙并在器件周围形成圆角。最后,该封装体再由同一个个真空烤箱或另外的传统烤箱在底胶固化温度(例如125-165℃)进行烘烤或者经过紫外线固化。在固化过程中,可以使用也可以不使用真空炉。For example, after primer coating, the device and PCB board will be transferred from the coating machine to a vacuum oven. The starting temperature of the oven is a temperature between the primer flow temperature of room temperature (for example, 70-90°C) or the primer flow temperature. The oven is then raised to primer flow temperature and held there until the primer fills the device-to-substrate gap and fillets around the device. Finally, the package is baked in the same vacuum oven or another conventional oven at the primer curing temperature (for example, 125-165°C) or UV cured. During curing, a vacuum oven may or may not be used.

在真空烤箱中进行底胶流动的主要目的是在底胶填充间隙前将芯片与基板间的空气抽走;且即使已经将底胶涂布并填充了间隙,在真空烤箱中采用两个温度梯度曲线的加热方式也可以将空气赶走。真空回流炉同样可以应用于本发明中,器件底胶流动时可以在回流炉的某个区中用一个真空腔盖住。或者,将涂布好底胶的封装体放入可移动真空室,将一批封装体放置好,真空室开始抽空,然后将真空室内温度升到底胶流动温度,也可以真空室内温度一开始就维持在底胶流动温度,因基板升温需要时间,关键是底胶升温,在开始流动或流动很小距离时,烤箱处于真空环境中,底胶的流动过程处于真空中,从而避免了空气流动过程中的底胶气泡和固化后的空洞。最后底胶的固化可以在任何环境中,烘烤机器可以为热板,传统烤箱或回流炉。The main purpose of primer flow in a vacuum oven is to draw the air between the chip and the substrate before the primer fills the gap; and even after the primer has been applied and the gap is filled, two temperature gradients The heating pattern of the curve also drives the air away. A vacuum reflow furnace can also be applied to the present invention, and a vacuum chamber can be used to cover a certain area of the reflow furnace while the device primer is flowing. Alternatively, put the primer-coated package into a movable vacuum chamber, place a batch of packages, and start to evacuate the vacuum chamber, then raise the temperature in the vacuum chamber to the flow temperature of the primer, or the temperature in the vacuum chamber can be lowered from the beginning. Maintain the primer flow temperature, because it takes time for the substrate to heat up, the key is to heat up the primer. When it starts to flow or flows for a small distance, the oven is in a vacuum environment, and the flow process of the primer is in a vacuum, thus avoiding the air flow process Primer bubbles and voids after curing. The curing of the final primer can be in any environment, the baking machine can be a hot plate, a conventional oven or a reflow oven.

对于小器件(5mm或更少),底胶只要沿器件一边或两边涂布即可,然后将封装体放入传统烤箱或回流炉。由于小器件不易产生气泡,一般无需进行抽真空处理。烘烤温度也同样是一个中等的流动温度和一个较高的固化温度。将底胶流动工艺从点胶机上转移到烤箱中,底胶流动时间降低,工艺效率得到提升。For small devices (5mm or less), primer is simply applied along one or both sides of the device, and the package is placed in a conventional oven or reflow oven. Because small devices are not easy to generate air bubbles, it is generally not necessary to carry out vacuum treatment. The bake temperature is also a moderate flow temperature and a high cure temperature. The primer flow process is transferred from the dispenser to the oven, the primer flow time is reduced, and the process efficiency is improved.

将底胶流动工艺从点胶机转移到烤箱中的好处是可以明显地提高生产效率并降低设备投资。此外,在底胶流动中,可以在烤箱中采用批处理方式对多块基板进行底胶流动和填充间隙。而在点胶机,底胶流动只能逐个进行。例如,对100个倒装芯片进行底胶填充间隙需要20秒钟,而在点胶机上所需的总时间将是2000秒。同样的,底胶固化也可以在烤箱中采用批处理方式进行。The benefit of moving the primer flow process from the dispenser to the oven is a significant increase in productivity and reduced equipment investment. Additionally, in primer flow, multiple substrates can be primed and gap filled in batch mode in an oven. In the glue dispenser, the primer flow can only be carried out one by one. For example, it takes 20 seconds to underfill the gap for 100 flip chips, and the total time required on the dispenser will be 2000 seconds. Likewise, primer curing can be done in an oven in batch mode.

除了高效率和无气泡的优点,本发明还能实现器件四周边缘底胶体积的一致性。器件边缘底胶圆角是多余的底胶围绕器件四周形成的,它的横截面是圆弧形,底胶圆角的一致性有助于提高可靠性。该圆角的横截面通常为凹形,如果底胶涂布过量则为凸形。传统底胶的问题是底胶在器件周围不均匀,因为底胶在器件的一边或最多两边涂布,底胶从涂布的边缘流向没有涂布的边缘,最后往往涂布边缘的底胶多于未有涂布的边缘。 最坏的情况下没有涂布边缘没有底胶。为了达到一致性,目前行业中的做法是在底胶填充后再在器件四周涂布一层底胶,然而这增加了工艺步骤,降低了效率。参见图3,本发明则可以在底胶涂布时以对称方式沿器件的四周涂布底胶而保证底胶在器件边缘圆角的一致性。In addition to the advantages of high efficiency and no air bubbles, the present invention can also achieve consistent volume of underfill around the edges of the device. The rounded corners of the bottom glue on the edge of the device are formed by the redundant bottom glue around the device. Its cross section is arc-shaped, and the consistency of the bottom glue rounded corners helps to improve reliability. The fillet is generally concave in cross-section and convex if the primer is overcoated. The problem with conventional primers is that the primer is not uniform around the device, because the primer is applied on one or at most two sides of the device, the primer flows from the coated edge to the uncoated edge, and there is often more primer on the coated edge. on uncoated edges. Worst case no primer on uncoated edges. In order to achieve consistency, the current practice in the industry is to apply a layer of primer around the device after the primer is filled. However, this increases the process steps and reduces the efficiency. Referring to FIG. 3 , the present invention can apply the primer symmetrically along the periphery of the device during the coating of the primer so as to ensure the consistency of the primer at the rounded corners of the edge of the device.

不同于现有技术以点胶机一种设备完成整个底胶涂布和底胶流动工艺,本发明采用不同机器来分别处理底胶涂布和流动。这带来了诸多优势:Unlike the prior art, which uses a glue dispenser to complete the entire primer coating and primer flow process, the present invention uses different machines to handle the primer coating and flow separately. This brings a number of advantages:

1、底胶涂布时,可采用的底胶材料形式更广,并且可以对基板不进行加热或稍稍加热,相比于现有技术必须给基板加热可以简化工艺或节省耗能。此外,在底胶涂布时采用以对称方式沿器件的四周涂布底胶的方式可以在底胶涂布阶段即保证底胶填充工艺结束时的底胶圆角一致性。而现有技术需要增加工艺来保证该一致性。1. When coating the primer, a wider range of primer materials can be used, and the substrate can be heated without or slightly. Compared with the prior art, the substrate must be heated to simplify the process or save energy consumption. In addition, the method of coating the primer symmetrically along the periphery of the device can ensure the consistency of the fillet of the primer at the end of the primer filling process at the primer coating stage. However, in the prior art, a process needs to be added to ensure the consistency.

2、底胶流动在烤箱中进行,可以节省流动工艺耗时以及节约设备投资,尤其通过批处理方式同时处理多个器件的底胶流动工艺,更可大大减少一批次器件的总体底胶填充时间。此外,通过将烤箱内置为真空环境以在真空中完成底胶流动,可大大减少底胶填充中出现空洞的可能性。2. The primer flow is carried out in the oven, which can save time-consuming flow process and save equipment investment, especially the primer flow process of multiple devices can be processed at the same time by batch processing, which can greatly reduce the overall primer filling of a batch of devices time. Additionally, by building the oven into a vacuum environment to complete the primer flow in a vacuum, the possibility of voids in the primer fill is greatly reduced.

以上内容是结合具体的实施方式对本发明所作的进一步详细说明,不能认定本发明的具体实施只局限于这些说明。对于本发明所属技术领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干简单推演或替换,都应当视为属于本发明的保护范围。The above content is a further detailed description of the present invention in conjunction with specific embodiments, and it cannot be assumed that the specific implementation of the present invention is limited to these descriptions. For those of ordinary skill in the technical field of the present invention, without departing from the concept of the present invention, some simple deduction or replacement can be made, which should be regarded as belonging to the protection scope of the present invention.

Claims (10)

  1. A kind of primer fill method in semiconductor packages, primer is filled for the gap between substrate and encapsulation semiconductor devices on the substrate, it is characterised in that including:
    Primer is coated with:Primer is coated with using the semiconductor device edge of primer coating machine on the substrate;
    Primer flows:The substrate of coated primer is transferred in baking box, heated with primer flowing temperature, until primer is filled into the gap between the substrate and the semiconductor devices;
    Primer solidifies:Heating is carried out with primer solidification temperature until primer solidification.
  2. The method as described in claim 1, it is characterised in that when the primer flows, maintains to be vacuum environment in the baking box.
  3. The method as described in claim 1, it is characterised in that when primer is coated with, is coated with the primer along the semiconductor devices surrounding in a symmetrical.
  4. The method as described in claim 1, it is characterised in that when the primer flows, the substrate is inclined by being placed in the baking box, and before primer flowing, one layer of non-adhesive layer is first covered in the semiconductor device surface.
  5. The method as described in claim 1, it is characterised in that the primer includes liquid primer, solid-state primer or paste state primer.
  6. Method as claimed in claim 5, it is characterised in that during liquid primer, be applied to using drop technique on the substrate;During solid-state primer, the method placed using the coating of heating needle tubing and solid block is applied on the substrate;When pasting state primer, it is applied to using typography or needle tubing on the substrate.
  7. Method as described in claim 1-6 is any, it is characterised in that in primer flowing and primer solidification, primer flowing and solidification are carried out using batch processing mode to polylith substrate simultaneously.
  8. A kind of primer pad device in semiconductor packages, primer is filled for the gap between substrate and encapsulation semiconductor devices on the substrate, it is characterised in that including:
    Primer coating machine, semiconductor device edge coating primer on the substrate;
    Baking box, the primer on the substrate with primer flowing temperature to inserting coated primer therein is heated, until primer is filled into the gap between the substrate and the semiconductor devices;And heating is carried out until the primer solidifies to the primer with primer solidification temperature.
  9. Primer pad device as claimed in claim 8, it is characterised in that the baking box for being used to carry out primer flowing is vacuum oven or vacuum back-flow stove.
  10. Primer pad device as claimed in claim 8, it is characterised in that described is hot plate, conventional oven or reflow ovens for the baking box that primer solidifies.
CN201180004482.2A 2011-04-06 2011-04-06 Primer fill method in a kind of semiconductor packages and equipment Active CN103109361B (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104569109A (en) * 2014-12-31 2015-04-29 武汉邮电科学研究院 ISFET (Ion Sensitive Field Effect Transistor) sensor chip structure and integrated packaging method thereof
CN108108681A (en) * 2017-12-14 2018-06-01 江西合力泰科技有限公司 With high bio-identification module for resisting external force ability and preparation method thereof
WO2023105307A1 (en) * 2021-12-06 2023-06-15 International Business Machines Corporation Underfill vacuum process
CN119230425A (en) * 2024-09-27 2024-12-31 重庆鹰谷光电股份有限公司 Semiconductor chip packaging debubbling system and debubbling method

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030116864A1 (en) * 2001-12-21 2003-06-26 Intel Corporation Underfill process for flip-chip device
CN1574255A (en) * 2003-05-22 2005-02-02 台湾积体电路制造股份有限公司 Flip-chip packaging process and its substrates and non-solder printing screen
US20070111400A1 (en) * 2005-11-15 2007-05-17 Katsumi Terada Dispensing device and mounting system

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6391683B1 (en) * 2000-06-21 2002-05-21 Siliconware Precision Industries Co., Ltd. Flip-chip semiconductor package structure and process for fabricating the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030116864A1 (en) * 2001-12-21 2003-06-26 Intel Corporation Underfill process for flip-chip device
CN1574255A (en) * 2003-05-22 2005-02-02 台湾积体电路制造股份有限公司 Flip-chip packaging process and its substrates and non-solder printing screen
US20070111400A1 (en) * 2005-11-15 2007-05-17 Katsumi Terada Dispensing device and mounting system

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN104569109A (en) * 2014-12-31 2015-04-29 武汉邮电科学研究院 ISFET (Ion Sensitive Field Effect Transistor) sensor chip structure and integrated packaging method thereof
CN104569109B (en) * 2014-12-31 2018-01-02 武汉邮电科学研究院 A kind of chip structure and its integrated encapsulation method towards ISFET sensors
CN108108681A (en) * 2017-12-14 2018-06-01 江西合力泰科技有限公司 With high bio-identification module for resisting external force ability and preparation method thereof
WO2023105307A1 (en) * 2021-12-06 2023-06-15 International Business Machines Corporation Underfill vacuum process
GB2627717A (en) * 2021-12-06 2024-08-28 Ibm Underfill vacuum process
US12315775B2 (en) 2021-12-06 2025-05-27 International Business Machines Corporation Underfill vacuum process
CN119230425A (en) * 2024-09-27 2024-12-31 重庆鹰谷光电股份有限公司 Semiconductor chip packaging debubbling system and debubbling method

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