CN103117245A - Formation method of air-gap interconnection structure - Google Patents

Abstract

The invention discloses a method for forming an air-gap interconnection structure, the method comprising depositing a first dielectric layer on a base layer of a semiconductor integrated circuit; depositing a second dielectric layer on the first dielectric layer; depositing a second dielectric layer on the second dielectric layer Grooves are formed on the upper surface, and two adjacent trenches are separated by the second dielectric layer; a barrier layer and a main conductive layer are sequentially deposited on the surface of the second dielectric layer and in the groove; the surface of the main conductive layer is planarized and retained A certain thickness of the main conductive layer; use a stress-free polishing process to remove all the main conductive layers except the main conductive layer in the trench; use a stress-free removal barrier layer process to remove all barrier layers exposed outside the trench; remove the second dielectric Layer, a groove is formed between two adjacent grooves; a third dielectric layer is deposited on the groove wall and the exposed main conductive layer and barrier layer; a fourth dielectric layer is deposited in the third dielectric layer and the groove layers, air gaps are formed in the grooves. In the present invention, by adopting a stress-free polishing process and a stress-free barrier layer removal process, the air-gap interconnection structure can be formed in a semiconductor integrated circuit with an ultra-fine feature size structure.

Description

Method for forming air-gap interconnect structure

technical field

The present invention relates to a manufacturing method of a semiconductor integrated circuit, in particular to a method for forming an air-gap interconnection structure for reducing capacitance in the semiconductor integrated circuit.

Background technique

With the development of the semiconductor industry, Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) have been widely used. Compared with previous integrated circuits, VLSI and VLSI have more complex multi-layer structures and smaller feature sizes. As we all know, in a resistance-capacitance circuit, the circuit resistance and circuit capacitance determine the resistance-capacitance hysteresis (RCdelay) of the circuit and the energy consumption (E=CV ² f) of the circuit. Therefore, the resistance value and capacitance value of the integrated circuit directly determine the performance of the integrated circuit, especially the ultra-fine feature size integrated circuit. The performance development of existing very large and very large scale integrated circuits is limited by the resistance and capacitance hysteresis and energy consumption in the circuit. In order to reduce the resistance-capacitance hysteresis and energy consumption in the circuit, copper (Cu) has gradually replaced aluminum (Al) to form the metal structure in the integrated circuit due to its higher conductivity, and the low dielectric constant material (loW-k material, k<2.5), such as aromatics hydrocarbon thermosetting polymer (SILK), is also used to replace traditional dielectric materials such as SiO ₂ (k>4.0).

However, due to the weak mechanical strength of low-k dielectric materials, there is a huge difference in Young's modulus relative to copper, and the mechanical strength of the copper interconnect structure is proportional to its line width (as shown in Figure 1), when using chemical mechanical planarization When the (CMP) process planarizes the excess copper structure to the barrier layer, the downward pressure will destroy the dielectric layer structure of the low-k dielectric material, causing short circuit or open circuit of the copper wire, making the integrated circuit invalid, and the low-k dielectric material Mechanical performance deficiencies have hindered their widespread use in integrated circuits.

In order to overcome the defects of low-k dielectric materials, air-gap (air-gap) interconnection technology is introduced into the interconnection structure of integrated circuits. Air-gap technology, to be precise, the space inside the air-gap is a vacuum without air, because ordinary air must contain moisture, which may cause corrosion and degradation of the surrounding copper wires. The air gap technology can reduce the dielectric constant of the dielectric layer significantly by using the vacuum dielectric constant of 1 without changing the existing dielectric layer material, and without changing the existing process technology and equipment. In order to understand the function of the low-k dielectric material, the dielectric layer structure containing air gaps can be considered as a dielectric material structure containing a porous structure. However, the current air gap technology, as disclosed in US Patent No. US 7,501,347, US 7,629,268 and US 7,361,991, can only be applied to integrated circuits with a feature size of 90nm or more. When the feature size of the integrated circuit is reduced, the traditional Damascus The damascene process also faces the technical bottleneck of mechanical stress causing damage to the copper interconnection structure when the copper interconnection structure is planarized. How to break through the stress damage bottleneck in the planarization process becomes the key to the formation of air gap technology.

In order to solve the damage to the structure of the dielectric layer caused by the mechanical stress in the chemical mechanical planarization process, in the existing air gap formation process, a layer of hard mask film is usually deposited on the sacrificial layer to protect the material of the sacrificial layer. The masking film has high mechanical strength to resist the mechanical stress caused by the chemical mechanical planarization process, and the hard masking film is subsequently removed. This kind of process increases the steps of forming the air gap, which makes the process of forming the air gap more complicated.

At the same time, in order to avoid potential damage to the copper wire caused by the chemical mechanical planarization process, a part of the dielectric material will be reserved to protect the two wings of the copper wire. Therefore, the air gap cannot be formed in the narrow copper wire spacing region, or only a small air gap can be formed in the narrow copper wire spacing region. For this reason, the existing air-gap interconnect structure formation process cannot be used in integrated circuits with extremely small feature sizes. However, the smaller the feature size of integrated circuits, the more significant the dielectric constant has on the electrical performance of the circuit. Therefore, this technical problem needs to be solved urgently.

Contents of the invention

The object of the present invention is to provide a method for forming an air-gap interconnection structure in a semiconductor integrated circuit with an ultra-fine feature size structure in view of the defects in the above-mentioned background technology.

In order to achieve the above object, the present invention proposes a method for forming an air-gap interconnection structure, which includes the following steps:

Depositing a first dielectric layer on the base layer of the semiconductor integrated circuit;

depositing a second dielectric layer on the first dielectric layer;

Forming trenches on the second dielectric layer, two adjacent trenches are separated by the second dielectric layer;

sequentially depositing a barrier layer and a main conductive layer on the surface of the second dielectric layer and in the groove;

Planarizing the surface of the main conductive layer and retaining a certain thickness of the main conductive layer;

Using a stress-free polishing process to remove all the main conductive layers except the main conductive layer in the trench;

Using a stress-free barrier removal process to remove all barrier layers exposed outside the trench;

removing the second dielectric layer to form a groove between two adjacent grooves;

Depositing a third dielectric layer on the groove wall and the exposed main conductive layer and barrier layer;

A fourth dielectric layer is deposited over the third dielectric layer and in the groove, and an air gap is formed in the groove.

Preferably, the first dielectric layer may be made of one of SiCN, SiC, SiN and SiOC or a mixture thereof.

Preferably, the second dielectric layer may be made of an ultra-low K dielectric material or a low K dielectric material or a dielectric material.

Preferably, the dielectric material may be an organic material.

Preferably, the organic material may be SiLK.

Preferably, the barrier layer may be made of one of tantalum, tantalum nitride, titanium, titanium nitride or a mixture thereof.

Preferably, the barrier layer is deposited on the surface of the second dielectric layer and the inner wall of the trench by sputtering.

Preferably, the main conductive layer is made of copper.

Preferably, a thin seed layer is deposited on the barrier layer by chemical vapor deposition, and then a copper layer is deposited on the thin seed layer and in the trench by an electrochemical copper plating process.

Preferably, the surface of the main conductive layer is planarized by using a chemical mechanical polishing planarization process with low down pressure, and the main conductive layer with a thickness of 100nm to 200nm is retained.

Preferably, XeF2 vapor phase etching process is used to remove all barrier layers exposed outside the trench.

Preferably, the second dielectric layer is removed by a plasma etching process to form the groove, and the first dielectric layer serves as an etching stop layer.

Preferably, the characteristic size of the groove is between 10nm and 250nm.

Preferably, the third dielectric layer may be made of one of SiCN, SiC, SiN, SiOC or a mixture thereof.

Preferably, the fourth dielectric layer is deposited using a non-conformal chemical vapor deposition process.

Preferably, the fourth dielectric layer may be made of one of SiOF, SiOC or a mixture thereof.

To sum up, the method for forming an air-gap interconnection structure of the present invention removes the redundant main conductive layer and the redundant barrier layer by using stress-free polishing, since there is no mechanical stress, thus it will not affect the semiconductor integrated circuit. In particular, the remaining main conductive layer, barrier layer and dielectric layer in the semiconductor integrated circuit cause any damage. Therefore, the air gap interconnection structure can be formed in a semiconductor integrated circuit with an ultra-fine feature size structure, for example, the feature size is less than 65nm and In the following semiconductor integrated circuits. By forming the relatively large air gap, the dielectric constant of the dielectric layer in the semiconductor integrated circuit is further reduced, thereby reducing the capacitance value in the semiconductor integrated circuit, so as to improve the performance of the semiconductor integrated circuit. Compared with the existing technology, the invention has simple technology and does not need to develop new materials, and by depositing the fourth dielectric layer, the overall structure of the semiconductor integrated circuit has good mechanical strength and can withstand the pressure of subsequent packaging.

Description of drawings

Figure 1 shows a schematic diagram of the relationship between copper wire width and its mechanical strength.

FIG. 2 is a cross-sectional schematic view of the present invention after sequentially depositing a first dielectric layer, a second dielectric layer, an anti-reflection film and a photolithographic blocking mask on the base layer of a semiconductor integrated circuit according to the process.

FIG. 3 is a cross-sectional schematic view of the present invention after performing pattern exposure on a photolithography blocking mask according to the process and forming a patterned anti-reflection film.

FIG. 4 is a schematic cross-sectional view of the present invention after forming trenches on the second dielectric layer according to the process.

FIG. 5 is a cross-sectional schematic view of the present invention after sequentially depositing a barrier layer and a main conductive layer according to the procedures.

FIG. 6 is a cross-sectional schematic view of the present invention after preliminary planarization of the surface of the main conductive layer according to the process.

FIG. 7 is a cross-sectional schematic view of the present invention after stress-free polishing and planarization of the surface of the main conductive layer according to the process.

FIG. 8 is a schematic diagram of a cross-section after etching the barrier layer exposed outside the trench according to the process of the present invention.

FIG. 9 is a schematic cross-sectional view of the present invention after removing the second dielectric layer and depositing the third dielectric layer according to the process.

FIG. 10 is a cross-sectional schematic diagram of depositing a fourth dielectric layer and forming an air gap according to the process of the present invention.

Detailed ways

In order to describe the technical content, structural features, achieved goals and effects of the present invention in detail, the following will be described in detail in conjunction with the embodiments and accompanying drawings.

Please refer to FIG. 2 to FIG. 10 in sequence. The method for forming an air-gap interconnection structure of the present invention includes the following steps:

Step 1: Deposit a first dielectric layer 302 on the base layer 301 of the semiconductor integrated circuit. The first dielectric layer 302 can be made of one of SiCN, SiC, SiN and SiOC or a mixture thereof.

Step 2: depositing a second dielectric layer 303 on the first dielectric layer 302 as a sacrificial layer. The second dielectric layer 303 may be made of an ultra-low-K dielectric material or a low-K dielectric material or a dielectric material, and the dielectric material may be an organic material, such as SiLK material.

Step 3: depositing an anti-reflection film 304 on the second dielectric layer 303 .

Step 4: depositing a photolithographic blocking mask 305 on the anti-reflection film 304 .

Step 5: Perform pattern exposure on the photolithography blocking mask 305 to form a patterned photolithography blocking mask, and then selectively remove the anti-reflection film 304 by dry etching process, so that the pattern is formed on the anti-reflection film 304 (as shown in Figure 3).

Step 6: Using the patterned photolithographic blocking mask 305 as an etching mask, the second dielectric layer 303 is selectively removed by a dry etching process, and grooves 100 are formed on the second dielectric layer 303, with two adjacent grooves The groove 100 is isolated by the second dielectric layer 303 , and then the photolithographic blocking mask 305 and the anti-reflection film 304 are all removed (as shown in FIG. 4 ).

Step 7: Sputter-deposit a barrier layer 306 on the surface of the second dielectric layer 303 and the inner wall of the trench 100, the barrier layer 306 can be made of one of tantalum, tantalum nitride, titanium, titanium nitride or their mixture, and then deposit a main conductive layer 307 (as shown in FIG. 5 ) on the barrier layer 306 and in the trench 100. The main conductive layer 307 can be made of copper. In this case, a thin seed layer needs to be deposited on the barrier layer 306 by chemical vapor deposition, and then a copper layer is deposited on the thin seed layer and in the trench 100 by an electrochemical copper plating process.

Step 8: Polish the main conductive layer 307 by using a chemical mechanical polishing planarization process with a low down pressure to partially planarize the main conductive layer 307 and retain a certain thickness of the main conductive layer 307 (as shown in FIG. 6 ). In this embodiment, the preferred main conductive layer 307 is a copper layer, and correspondingly, the thickness of the remaining copper layer is optimally 100nm-200nm.

Step 9: Remove all copper layers except the copper layer in the trench 100 (as shown in FIG. 7 ) by using a stress-free polishing process. The stress-free polishing process is based on the principle of electrochemical polishing, and the semiconductor to be polished is integrated The copper structure on the surface of the circuit is used as the anode, and the polishing liquid nozzle is used as the cathode. A voltage is applied between the anode and the cathode, and the polishing liquid nozzle sprays the polishing liquid onto the copper surface, and the copper is dissolved in the polishing liquid and removed. The stress-free polishing process can selectively remove the redundant copper structure, and will not cause erosion and deformation to the dielectric layer and barrier layer, completely avoiding the damage of copper, low-k dielectric layer and ultra-low-k dielectric layer by mechanical stress, fundamentally Above all, it solves the process problem of integrating low-K dielectric materials or ultra-low-K dielectric materials with copper. At the same time, in the stress-free polishing system, since the polishing liquid can be recycled, it not only reduces the cost but also reduces environmental pollution.

Step 10: Remove all the barrier layer 306 exposed outside the trench 100 by using a stress-free barrier layer removal process, and only retain the barrier layer 306 in the trench 100 (as shown in FIG. 8 ). In this embodiment, the The barrier layer 306 is made of one of tantalum, tantalum nitride, titanium, titanium nitride or a mixture thereof. Therefore, in this embodiment, a XeF ₂ vapor phase etching process is used to remove all the barrier layer 306 exposed outside the trench 100. XeF ₂ The etching chemical reaction can spontaneously and selectively occur with the barrier layer 306 made of one of tantalum, tantalum nitride, titanium, titanium nitride or their mixture under certain temperature and pressure conditions. In this embodiment, the temperature of the etching process can be 0° C. to 300° C., and 25° C. to 200° C. is the optimum reaction temperature. The XeF ₂ gas pressure can be 0.1 Torr to 100 Torr, and the optimum reaction pressure is 0.5 Torr to 20 Torr. XeF ₂ has good selectivity for copper and the second dielectric layer 303 made of dielectric materials, especially for Si-COH as the base material and a dielectric constant of 1.2 to 4.2, wherein the dielectric constant of 1.3 to 2.4 is An optimally formed second dielectric layer 303 has better selectivity. During the entire vapor phase etching process, no mechanical stress is exerted on the barrier layer 306 and the second dielectric layer 303 , so there is no damage to the copper film and the second dielectric layer 303 . Moreover, XeF ₂ reacts with the barrier layer 306 to obtain gas phase reactants, such as Xe and volatile tantalum fluoride produced under a certain reaction temperature and pressure, so there is no residual substance attached to the surface of the semiconductor integrated circuit.

Step 11: Remove the second dielectric layer 303 by using a plasma etching process to form a groove 1007 between the two adjacent trenches 100, the first dielectric layer 302 serves as an etching stop layer, and the characteristics of the groove 1007 The size can be between 10nm and 250nm. The plasma reducing gas selected in the plasma etching process may be NH ₃ or H ₂ or N ₂ . During the etching process, the barrier layer 306 and the main conductive layer 307 will not suffer any damage. Next, deposit a third dielectric layer 308 on the surface of the entire semiconductor integrated circuit. The third dielectric layer 308 covers the surface of the entire semiconductor integrated circuit as a sealing dielectric layer. The third dielectric layer 308 can be made of SiCN, SiC, One of SiN, SiOC or their mixture (as shown in Figure 9).

Step 12: Depositing a fourth dielectric layer 309 on the third dielectric layer 308 by non-conformal chemical vapor deposition to form an air gap 200 in the groove 1007 . The size and shape of the air gap 200 can be optimized according to the feature size of the semiconductor integrated circuit, so as to reduce the dielectric constant of the dielectric layer of the semiconductor integrated circuit. The fourth dielectric layer 309 can be made of one of SiOF, SiOC or a mixture thereof.

As can be seen from the above, the present invention adopts stress-free polishing technology to remove excess copper layer and stress-free removal of excess barrier layer 306. During the implementation of these two process steps, no mechanical stress is generated, so it will not affect semiconductor integrated circuits, especially semiconductor integrated circuits. The remaining copper film, barrier layer and dielectric layer in the circuit cause any damage. Therefore, the air gap 200 can be formed in a semiconductor integrated circuit with an ultra-fine feature size structure, such as a semiconductor integrated circuit with a feature size of less than 65nm and below . By forming the relatively large air gap 200, the dielectric constant of the dielectric layer in the semiconductor integrated circuit is further reduced, thereby reducing the capacitance value in the semiconductor integrated circuit, so as to improve the performance of the semiconductor integrated circuit. Compared with the existing technology, the technology of the present invention is simple and does not require the development of new materials, and by depositing the fourth dielectric layer 309, the overall structure of the semiconductor integrated circuit has good mechanical strength and can withstand the pressure of subsequent packaging.

To sum up, the method for forming an air-gap interconnection structure of the present invention has disclosed the relevant technology in detail and in detail through the above-mentioned embodiments and related drawings, so that those skilled in the art can implement it accordingly. The above-mentioned embodiments are only used to illustrate the present invention, rather than to limit the present invention, and the scope of rights of the present invention should be defined by the claims of the present invention. Changes in the number of elements described herein or substitution of equivalent elements should still fall within the scope of the present invention.

Claims (16)

1. the formation method of an air-gap interconnect architecture, is characterized in that: comprise the steps:

Deposit first medium layer on the basalis of semiconductor integrated circuit;

Deposit second medium layer on the first medium layer;

Form groove on the second medium layer, adjacent two grooves are kept apart by the second medium layer;

Barrier layer and main conductive layer successively in the surface of second medium layer and groove;

Main conductive layer is carried out flattening surface, and keep certain thickness main conductive layer;

Adopt non-stress polishing technique removal all main conductive layers except the main conductive layer in groove;

Adopt unstressed removal barrier layer technique to remove to be exposed to all outer barrier layers of groove;

Remove the second medium layer, form a groove between adjacent two grooves;

Deposit the 3rd dielectric layer on groove walls and exposed main conductive layer and barrier layer;

Deposit the 4th dielectric layer in the 3rd dielectric layer and groove, air-gap is formed in groove.

2. the formation method of air-gap interconnect architecture as claimed in claim 1, it is characterized in that: described first medium layer can be made of one of SiCN, SiC, SiN and SiOC or their mixture.

3. the formation method of air-gap interconnect architecture as claimed in claim 1 is characterized in that: described second medium layer can be made of ultralow K dielectric material or low-K dielectric material or dielectric material.

4. the formation method of air-gap interconnect architecture as claimed in claim 3, it is characterized in that: described dielectric material can be organic material.

5. the formation method of air-gap interconnect architecture as claimed in claim 4, it is characterized in that: described organic material can be SiLK.

6. the formation method of air-gap interconnect architecture as claimed in claim 1, it is characterized in that: described barrier layer can be made of one of tantalum, tantalum nitride, titanium, titanium nitride or their mixture.

7. the formation method of air-gap interconnect architecture as claimed in claim 6 is characterized in that: described barrier layer is to adopt sputtering technology to be deposited on the surface and trench wall of second medium layer.

8. the formation method of air-gap interconnect architecture as claimed in claim 1, it is characterized in that: described main conductive layer is to be made of copper.

9. the formation method of air-gap interconnect architecture as claimed in claim 8 is characterized in that: adopt the thin Seed Layer of CVD (Chemical Vapor Deposition) method deposit one deck on described barrier layer, then adopt Cu electroplating technique to be deposited on the copper layer on described thin Seed Layer and groove in.

10. the formation method of air-gap interconnect architecture as claimed in claim 1, is characterized in that: adopt the chemico-mechanical polishing flatening process of low downforce to carry out flattening surface to main conductive layer, and keep the main conductive layer of 100nm to 200nm thickness.

11. the formation method of air-gap interconnect architecture as claimed in claim 1 is characterized in that: adopt XeF2 vapor phase etchant technique to remove all barrier layers that are exposed to outside groove.

12. the formation method of air-gap interconnect architecture as claimed in claim 1 is characterized in that: adopt plasma etching process to remove the second medium layer to form described groove, described first medium layer is as etching stopping layer.

13. the formation method of air-gap interconnect architecture as described in claim 1 or 12 is characterized in that: the characteristic size of described groove is between 10nm to 250nm.

14. the formation method of air-gap interconnect architecture as claimed in claim 1 is characterized in that: described the 3rd dielectric layer can be made of one of SiCN, SiC, SiN, SiOC or their mixture.

15. the formation method of air-gap interconnect architecture as claimed in claim 1 is characterized in that: adopt non-conformal chemical vapor deposition method deposit the 4th dielectric layer.

16. the formation method of air-gap interconnect architecture as described in claim 1 or 15 is characterized in that: described the 4th dielectric layer can be made of one of SiOF, SiOC or their mixture.

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