CN103138715A - High speed D trigger based on transistor - Google Patents
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Abstract
本发明公开了一种基于晶体管器件的高速D触发器，主要解决现有D触发器相位噪声高和工作频率低的问题。其主要由第一锁存器（1）、第二锁存器（2）、预置电路（3）、第一电流源电路（4a）和第二电流源电路（4b）组成。由差分电路构成的预置电路（3）分别与第二锁存器（2）的输出端和第二锁存器（2）的电流输入端相连，预置电路（3）受外部信号控制实现预置功能；第一电流源电路（4a）与第一锁存器（1）的电流输入端相连，为第一锁存器（1）提供稳定的电流，第二电流源电路（4b）与第二锁存器（2）的电流输入端相连，为第二锁存器（2）提供稳定的电流。本发明电路简单，具有相位噪声低及工作频率高等优点，可应用于高速程序分频器中。
The invention discloses a high-speed D flip-flop based on a transistor device, which mainly solves the problems of high phase noise and low operating frequency of the existing D flip-flop. It mainly consists of a first latch (1), a second latch (2), a preset circuit (3), a first current source circuit (4a) and a second current source circuit (4b). The preset circuit (3) composed of a differential circuit is respectively connected to the output terminal of the second latch (2) and the current input terminal of the second latch (2), and the preset circuit (3) is controlled by an external signal. Preset function; the first current source circuit (4a) is connected to the current input terminal of the first latch (1) to provide a stable current for the first latch (1), and the second current source circuit (4b) is connected to the current input terminal of the first latch (1). The current input ends of the second latch (2) are connected to provide a stable current for the second latch (2). The invention has the advantages of simple circuit, low phase noise and high operating frequency, and can be applied to high-speed program frequency dividers.
Description
Technical field
The invention belongs to the integrated circuit (IC) design technical field, relate to trigger, relate in particular to a kind of high speed d type flip flop based on transistor HBT device, can be used in program divider.
Technical background
Program divider is the important part in phase-lock frequency synthesizer, many key properties of frequency synthesizer are all relevant with the performance of program divider, limited the highest frequency of frequency synthesizer output signal such as the operating rate of program divider, its phase noise affects the in-band phase noise of frequency synthesizer.Therefore promote the speed of program divider, the phase noise of reduction program divider, just seem extremely important for a high performance frequency synthesizer.
The fundamental difference of program divider and fixed frquency divider is exactly the frequency dividing ratio continuous variable within the specific limits of program divider, and frequency dividing ratio is programmable.The structural representation of general procedure frequency divider as shown in Figure 1, it adopts the asynchronous counting structure of simple binary system to realize division function, mainly consists of by presetting d type flip flop.One contains the program divider that the N level can preset d type flip flop and can realize 2 ~ 2
NThe continuous variable frequency division of random natural number, its frequency dividing ratio control mode are N position binary value input, wherein N 〉=2.
Be the Main Ingredients and Appearance that forms program divider due to d type flip flop, just can improve the performance of program divider so improve the performance of d type flip flop, and then improve the performance of frequency synthesizer.Fig. 2 is existing circuit unit schematic diagram based on transistorized high speed d type flip flop.
The high speed d type flip flop that can preset at present, generally all adopts metal-oxide-semiconductor to build.Reported that as document " 2003IEEE Conference on Electron Devices and Solid-State Circuits; pp.269-272 " A2GHz programmable counter with new re-loadable D flip-flop " " one by the people such as M.A.DO, X.P.Yu and J.G. Ma design can be preset d type flip flop, this d type flip flop adopts true phase structure, and it is built by 21 metal-oxide-semiconductors.This can preset d type flip flop because the employing metal-oxide-semiconductor is built, thereby has following shortcoming:
1) operating rate is slow, is not suitable for being applied to the high-speed procedure frequency divider;
2) phase noise is high, makes the phase noise of whole program divider high;
3) operating frequency is low, is not suitable for being applied to the program divider of high band.
Summary of the invention
The object of the invention is to avoid the deficiency of above-mentioned prior art, propose a kind ofly based on transistorized high speed d type flip flop, to reduce phase noise, improve operating rate and operating frequency.
For achieving the above object, the present invention includes the first latch 1, the second latch 2, prewired circuit 3 and current source circuit 4, the preset signal that described prewired circuit 3 is used for input to external world carries out signal sampling, thus the preparatory function of realization; Input in described the second latch 2 is connected with the output of the first latch 1, and the output of the second latch 2 is connected with prewired circuit 3, and current source circuit 4 is connected with the second latch 2 with the first latch 1;
It is characterized in that:
Current source circuit is made as two, and the first current source circuit 4a is connected with the current input terminal of the first latch 1, for the first latch 2 provides stable electric current, the second current source circuit 4b is connected with the current input terminal of the second latch 2, for the second latch 2 provides stable electric current;
As preferably, described the first latch 1 comprises the first difference channel Q1, Q2, the second difference channel Q5, Q6 and the first cross-couplings circuit Q3, Q4, this first difference channel Q1, the collector electrode of Q2 and the first cross-couplings circuit Q3, the collector electrode of Q4 is connected, Q5 collector electrode in the second difference channel and the first difference channel Q1, the emitter of Q2 is connected, the Q6 collector electrode in the second difference channel and the first cross-couplings circuit Q3, and the emitter of Q4 is connected.
As preferably, described the second latch 2 comprises the 3rd difference channel Q9, Q10, the 4th difference channel Q13, Q14 and the second cross-couplings circuit Q11, Q12, the 3rd difference channel Q9, the collector electrode of Q10 and the second cross-couplings circuit Q11, the collector electrode of Q12 is connected, Q13 collector electrode in the 4th difference channel and the 3rd difference channel Q9, the emitter of Q10 is connected, Q14 collector electrode and the second cross-couplings circuit Q11 in the 4th difference channel, and the emitter of Q12 is connected.
As preferably, described the first current source circuit 4a comprises transistor Q7, transistor Q8 and resistance R 5; Be connected with resistance R 5 after the base stage of transistor Q7 is connected with the base stage of transistor Q8, consist of the first mirror current source; The collector electrode of transistor Q8 and the second difference channel Q5, the emitter of Q6 is connected.
As preferably, described the second current source circuit 4b comprises transistor Q15, transistor Q16 and resistance R 6; Be connected with resistance R 6 after the base stage of transistor Q15 is connected with the base stage of transistor Q16, consist of the second mirror current source; The collector electrode of transistor Q16 and the 4th difference channel Q13, the emitter of Q14 is connected.
As preferably, all transistors in described the first latch 1, the second latch 2, prewired circuit 3, the first current source circuit 4a and the second current source 4b all adopt heterojunction bipolar transistor HBT.
The present invention compared with prior art has following advantage:
1) prewired circuit that is consisted of by differential configuration due to employing in the present invention, and only consisted of by two transistors, thereby circuit is simple, is easy to realize; Simultaneously because prewired circuit directly is connected with the output of the second latch and the current input terminal of the second latch, the ghost effect of having avoided complicated interconnection to cause has improved the speed of whole d type flip flop;
2) the present invention owing to adopting two current source circuits to be respectively the first latch and the second latch provides electric current, has avoided interfering with each other of the first latch and the second latch circuit, has improved the stability of the first latch, the second latch circuit work; Because current source all adopts the image current source structure, current source is insensitive to other interference signals, has improved the stability of current source simultaneously;
3) because the present invention has adopted heterojunction bipolar transistor HBT, this transistor phase noise characteristic is good, frequency characteristic good, so low with the phase noise of its high speed d type flip flop circuit of building, operating frequency is high.
Description of drawings
Fig. 1 is the structural representation of existing program divider;
Fig. 2 is existing circuit unit schematic diagram based on transistorized high speed d type flip flop;
Fig. 3 is the structured flowchart that the present invention is based on transistorized high speed d type flip flop circuit;
Fig. 4 is the circuit theory diagrams that the present invention is based on transistorized high speed d type flip flop;
Fig. 5 is simulation result figure of the present invention.
Embodiment
For making technical scheme of the present invention clearer, below in conjunction with specific embodiment, and with reference to accompanying drawing, the present invention is described in more detail.
With reference to Fig. 3, high speed d type flip flop provided by the invention comprises the first latch 1, the second latch 2, prewired circuit 3, the first current source circuit 4a and the second current source circuit 4b.Wherein, the input of the second latch 2 is connected with the output of the first latch 1; The output of the second latch 2 is connected with prewired circuit 3, and this prewired circuit 3 adopts differential configuration, and its preset signal to the external circuit input is sampled and exports; The first current source circuit 4a, the second current source circuit 4b respectively with the first latch, the second latch is connected and provide stabling current for it; Outside input signal is controlled prewired circuit, realizes the conversion of circuit function.
With reference to Fig. 4, described based in transistorized high speed d type flip flop, the structure of unit circuit is as follows:
The first latch, mainly by the first difference channel Q1, Q2, the second difference channel Q5, Q6, the first cross-couplings circuit Q3, Q4, biasing resistor R1, R2 forms.This first difference channel Q1, the collector electrode of Q2 respectively with biasing resistor R1, R2 is connected, biasing resistor R1, R2 is the first difference channel Q1, and Q2 provides direct current biasing, simultaneously, Q1 in the first difference channel, the collector electrode of Q2 respectively with the first cross-couplings circuit Q3, the collector electrode of Q4 is connected, so that the first difference channel Q1, the signal that the Q2 sampling obtains is exported to the first cross-couplings circuit Q3, Q4; Q1 in the collector electrode of Q5 and the first difference channel in the second difference channel, the emitter of Q2 is connected, Q3 in the collector electrode of Q6 and the first cross-couplings circuit in the second difference channel, the emitter of Q4 is connected.Two differential clock signal CLK, CLKN inputting by the outside control the second difference channel Q5, the switching of Q6, thus realize passing through the first difference channel Q1, Q2 and the first cross-couplings circuit Q3, the control of Q4 size of current.When trigger mode of operation, when the clock signal clk of input is high level, and clock signal clk N is when being low level, and the differential data signals D of 1 pair of input of the first latch, DN sample, and export to the second latch; When the clock signal clk of input is low level, and clock signal clk N is when being high level, and the first difference channel is sampled data no longer, the first cross-couplings circuit Q3, and Q4 passes to the second latch with the signal that latchs.
The second latch 2, mainly by the 3rd difference channel Q9, Q10, the 4th difference channel Q13, Q14, the second cross-couplings circuit Q11, Q12, biasing resistor R3, R4 forms.The 3rd difference channel Q9, the collector electrode of Q10 respectively with biasing resistor R3, R4 is connected, make biasing resistor R3, R4 is the 3rd difference channel Q9, and Q10 provides direct current biasing, simultaneously, Q9 in the 3rd difference channel, the collector electrode of Q10 respectively with the second cross-couplings circuit Q11, the collector electrode of Q12 is connected, so that the 3rd difference channel Q9, the signal that Q10 obtains sampling is exported to the second cross-couplings circuit Q11, Q12; Q9 in the collector electrode of Q13 and the 3rd difference channel in the 4th difference channel, the emitter of Q10 is connected, Q11 in the collector electrode of Q14 and the second cross-couplings circuit, the emitter of Q12 is connected, the differential clock signal CLK and the clock signal clk N that input by the outside control the 4th difference channel Q13, the switching of Q14, thus realize passing through the 3rd difference channel Q9, Q10 and the second cross-couplings circuit Q11, the control of Q12 size of current.When trigger mode of operation, when the clock signal clk of input is low level, and clock signal clk N is when being high level, and the second latch is to the rear output of sampling of the data-signal of the first latch input; When the clock signal clk of input is high level, and clock signal clk N is when being low level, and the 3rd difference channel is sampled data no longer, the second cross-couplings circuit Q11, the signal of Q12 output latch.
The first current source circuit 4a, by transistor Q7, transistor Q8 and resistance R 5 consist of, the second difference channel Q5 in the collector electrode of Q8 and the first latch, the emitter of Q6 is connected, and the first current source circuit 4a provides stable electric current for the first latch.
The second current source circuit 4b, by transistor Q15, transistor Q16 and resistance R 6 consist of, the 4th difference channel Q13 in the collector electrode of Q16 and the second latch, the emitter of Q14 is connected, and the second current source circuit 4b provides stable electric current for the second latch.
All crystals pipe in above-described the first latch 1, the second latch 2, prewired circuit 3, current source circuit 4, be transistor Q1 ~ Q18, all adopt heterojunction bipolar transistor HBT, characteristic is good, frequency characteristic good because this transistor is made an uproar mutually, so low by the d type flip flop phase noise in its present invention who builds, operating frequency is high.
Operation principle of the present invention is as follows:
When the voltage signal RE of outside input and RE1 were differential signal, d type flip flop of the present invention was operated under prepattern, and the differential voltage signal of output is respectively Q and QN.When the voltage signal RE of input is high level, when the voltage signal RE1 of input is low level, transistor Q18 opens, transistor Q17 turn-offs, the differential voltage signal Q of output directly is communicated with current source 4b, this moment, the differential voltage signal Q of output was low level, and the differential voltage signal QN of output is high level, has realized clear 0 function of prewired circuit.When the voltage signal RE of input is low level, when the voltage signal RE1 of input is high level, transistor Q18 turn-offs, transistor Q17 opens, the differential voltage signal QN of output directly is communicated with current source 4b, this moment, the differential voltage signal Q of output was high level, and the differential voltage signal QN of output is low level, realizes 1 function of putting of prewired circuit.The d type flip flop level that is operated in prepattern output signal of lower time changes with preset signal and changes as known from the above, has realized preparatory function.
When the voltage signal RE of outside input and RE1 were low level, d type flip flop of the present invention was operated under trigger mode.Transistor Q17 and transistor Q18 all turn-off, the first latch and the normal operation of the second latch.The differential clock signal of outside input is CLK and CLKN, and the differential data signals of outside input is D and DN.When the differential clock signal CLK of outside input is high level, and the differential clock signal CLKN of outside input is when being low level, the differential data signals D of the outside input of the first 1 pair of latch and the differential data signals DN of outside input sample and export, the signal that latchs in second latch 2 output the second cross-couplings circuit Q11 and Q12 simultaneously; When the differential clock signal CLK of outside input is low level, and the differential clock signal CLKN of outside input is when being high level, the signal that latchs in first latch 1 output the first cross-couplings circuit Q3 and Q4, the signal of 2 pairs of the first latch 1 inputs of the second latch is simultaneously sampled and exports.As the above analysis, after sampling to the differential data signals D of outside input and DN, the differential clock signal CLKN rising edge of input externally, described d type flip flop respectively by differential voltage signal Q and QN output, namely realized the function of trigger.
Effect of the present invention can further illustrate by following emulation:
1. simulated conditions: in Microwave simulation software ADS, it is the square-wave signal that single spin-echo, frequency are 4GHz that the differential clock signal CLK of the outside input of d type flip flop and the differential clock signal CLKN of outside input are set; It is that single spin-echo, cycle are the square-wave signal of 1.6ns that the differential data signals D of outside input and the differential data signals DN of outside input are set; The voltage signal RE1 that outside input is set is that the cycle is 12ns, and duty ratio is 1/3, and time-delay is the square-wave signal of 16ns, and the voltage signal RE that outside input is set is that the cycle is 12ns, and duty ratio is 1/3, and time-delay is the square-wave signal of 8ns.
2. emulation content and result
Under above-mentioned simulated conditions, the high speed d type flip flop based on HBT of the present invention is carried out Transient, the signal output waveform that emulation obtains is as shown in Figure 5.
As seen from Figure 5, after stable output signal, when 4 ~ 8ns and 12 ~ 16ns, the voltage signal RE1 of the voltage signal RE of outside input and outside input is low level, when externally the differential clock signal CLKN rising edge of input arrives, the level of the differential voltage signal Q of output changes along with the differential data signals D level of outside input, and as seen this high speed d type flip flop has been realized the function of d type flip flop; At 8 ~ 12ns, the voltage signal RE of outside input is high level, and during the outside voltage signal RE1 low level of inputting, the differential voltage signal Q of output keeps low level, and as seen this d type flip flop has been realized clear 0 function; At 16 ~ 20ns, the voltage signal RE of outside input is low level, and when the voltage signal RE1 of outside input was high level, the differential voltage signal Q of output kept high level, and as seen this d type flip flop has realized putting 1 function.
By above simulation result as can be known, the present invention can realize the function of d type flip flop, and operating frequency is high, can be operated in 4GHz at least, is applicable in the high-speed procedure frequency divider.
Above description is only example of the present invention; obviously for those skilled in the art; after having understood content of the present invention and principle; all may be in the situation that do not deviate from the principle of the invention, structure; carry out various corrections and change on form and details, but these are based on the correction of inventive concept with change still in claim protection range of the present invention.
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| CN2013100280436A CN103138715A (en) | 2013-01-24 | 2013-01-24 | High speed D trigger based on transistor |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104935301A (en) * | 2015-07-01 | 2015-09-23 | 东南大学 | RS Flip-Flop Based on Si-Based Low Leakage Current Cantilever Floating Gate |
| CN111600598A (en) * | 2020-05-25 | 2020-08-28 | 中国电子科技集团公司第十三研究所 | Sync counter |
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| CN85109461A (en) * | 1986-05-03 | 1987-11-11 | 岳云书 | High anti-interference multifunctional trigger |
| CN1058123A (en) * | 1990-07-07 | 1992-01-22 | 西安电子科技大学 | Low-loss thyristor zero-voltage trigger |
| CN1337781A (en) * | 2000-06-06 | 2002-02-27 | 德克萨斯仪器股份有限公司 | Improvement of tirgger design |
| CN102324913A (en) * | 2011-06-30 | 2012-01-18 | 西安电子科技大学 | Presettable D flip-flop based on HBT device |
-
2013
- 2013-01-24 CN CN2013100280436A patent/CN103138715A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85109461A (en) * | 1986-05-03 | 1987-11-11 | 岳云书 | High anti-interference multifunctional trigger |
| CN1058123A (en) * | 1990-07-07 | 1992-01-22 | 西安电子科技大学 | Low-loss thyristor zero-voltage trigger |
| CN1337781A (en) * | 2000-06-06 | 2002-02-27 | 德克萨斯仪器股份有限公司 | Improvement of tirgger design |
| CN102324913A (en) * | 2011-06-30 | 2012-01-18 | 西安电子科技大学 | Presettable D flip-flop based on HBT device |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104935301A (en) * | 2015-07-01 | 2015-09-23 | 东南大学 | RS Flip-Flop Based on Si-Based Low Leakage Current Cantilever Floating Gate |
| CN104935301B (en) * | 2015-07-01 | 2017-05-31 | 东南大学 | The rest-set flip-flop of silicon substrate low-leakage current cantilever beam floating gate |
| CN111600598A (en) * | 2020-05-25 | 2020-08-28 | 中国电子科技集团公司第十三研究所 | Sync counter |
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Application publication date: 20130605 |