CN103151336B - Circuit substrate structure and manufacturing method thereof - Google Patents

Abstract

The invention discloses a circuit substrate structure and a manufacturing method thereof. Each of the conductive lines vertically passes through the silicon oxide substrate layer. The silicon oxide substrate layer and the plurality of wires of the circuit substrate structure can replace the functions of the existing silicon spacing layer and silicon through hole so as to be used for the electrical connection between the upper surface circuit and the lower surface circuit of a spacing piece. Compared with the existing silicon through hole which is time-consuming in manufacturing, the invention combines the routing process and the sol-gel method to manufacture the lead and the silicon oxide substrate layer, thereby saving the processing time and reducing the manufacturing cost.

Description

Circuit substrate structure and manufacturing method thereof

technical field

The present invention relates to a structure of a circuit substrate and a manufacturing method thereof, in particular to a structure of a circuit substrate combining a wire-bonding process and a sol-gel method instead of through-silicon vias and a manufacturing method thereof.

Background technique

In the existing semiconductor technology field, the through-silicon via (TSV, Through-Silicon Via) technology is often used in the electrical connection between the upper and lower surface circuits of the same chip or silicon spacer (interposer), so as to be applied in stacked In chip packaging, TSVs are beneficial to the development of 3D stacked packaging technology, and can effectively improve the integration and performance of chips.

The existing TSV method is to etch a columnar hole on a silicon substrate (such as a silicon wafer), and first form an insulating wall (such as chemical vapor deposition, Chemical Vapor Deposition, CVD) on the hole wall. The insulating wall is, for example, two silicon oxide; then, filling the holes with metal (such as copper) to form conductive metal pillars, and grinding or etching the bottom of the silicon substrate to expose the conductive metal pillars. However, the insulating walls of the TSVs formed by chemical vapor deposition (CVD) often have insufficient or uneven thicknesses, which may cause leakage short circuits, thus affecting the yield and quality of the TSVs to a certain extent. Electrical transmission quality. In order to solve the above problems, an improved technology for making TSVs was subsequently developed. It uses two dry etching processes to make secondary silicon deep holes for filling in insulating walls and metal pillars in sequence. The problem of insufficient insulation wall thickness can be effectively improved. However, dry etching using plasma (plasma) can only be performed on one silicon substrate at a time, and it is time-consuming to manufacture silicon deep holes, so that the time and cost of the entire TSV processing are relatively greatly increased.

Therefore, it is necessary to provide a circuit substrate structure and a manufacturing method thereof to solve the problems existing in the prior art.

Contents of the invention

The main purpose of the present invention is to provide a circuit substrate structure and its manufacturing method. Compared with the time-consuming manufacturing of the existing TSVs, the present invention combines the wire bonding process and the sol-gel (sol-gel) method to make wires. and a silicon oxide (SiO ₂ ) substrate layer, which can replace the existing manufacturing method of the silicon spacer layer structure of the TSV, and can save processing time and reduce manufacturing cost.

In order to achieve the foregoing objectives of the present invention, the present invention provides a circuit substrate structure, which mainly includes a silicon oxide substrate layer and a plurality of wires. The silicon oxide substrate layer has a first surface and a second surface on the corresponding side; and each of the wires vertically passes through the silicon oxide substrate layer from the first surface to the second surface.

In addition, the present invention provides a method for manufacturing a circuit substrate, which includes the following steps: providing a wire bonding carrier board; vertically bonding a plurality of wires on the wire bonding carrier board in a wire bonding manner, and each wire is placed on the wire bonding carrier board. A knotting ball is produced on the wire bonding carrier plate, and then cut vertically upwards to a preset length; impregnating multiple wires on the wire bonding carrier plate with a tetraethoxysilane sol-gel composite solution; solidifying the sol-gel composite solution to form a silicon oxide substrate layer; grinding and thinning the upper surface of the silicon oxide substrate layer until the upper ends of the plurality of wires are exposed to form a first silicon oxide substrate layer a surface; and removing the wire bonding carrier plate and grinding and thinning the lower surface of the silicon oxide substrate layer until the wire bonding balls at the lower ends of the wires are removed and the lower ends of the plurality of wires are exposed, so as to form the A second surface of the silicon oxide substrate layer.

Description of drawings

FIG. 1 is a side sectional view of a circuit board structure according to an embodiment of the present invention.

2A-2H are schematic diagrams of a manufacturing method of a circuit substrate structure according to an embodiment of the present invention.

3 is a side cross-sectional view of another embodiment of the present invention in which the circuit substrate structure is applied to a stacked chip package structure.

detailed description

In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments of the present invention are exemplified below and described in detail in conjunction with the accompanying drawings. Furthermore, the directional terms mentioned in the present invention are, for example, up, down, top, bottom, front, back, left, right, inside, outside, side, surrounding, central, horizontal, transverse, vertical, longitudinal, axial, The radial direction, the uppermost layer or the lowermost layer, etc. are only directions referring to the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention. It is specifically stated here that the objects depicted in the figure are not in accordance with the standard ratios of the objects (such as the ratio of substrates, chips, wires, and circuit layers), and are only for illustration purposes.

Please refer to FIG. 1 . FIG. 1 is a side cross-sectional view of a circuit substrate structure according to an embodiment of the present invention. As shown in FIG. 1, a circuit substrate structure 100 mainly includes a silicon oxide substrate layer 110, and the silicon oxide substrate layer 110 has a first surface (upper surface) 111 and a second surface (lower surface) 112 on the corresponding side. . A first circuit layer 120 is provided on the first surface 111, and the first circuit layer 120 includes a solder resist layer 121 and a plurality of solder pads 122, and the first solder resist layer 121 exposes each of the first A part of the pad 122; the second surface 112 is provided with a second circuit layer 130, the second circuit layer 130 includes a solder resist layer 131 and a plurality of solder pads 132, the second solder resist layer 131 exposes a portion of each of the second pads 132 .

Furthermore, the circuit substrate structure 100 includes a plurality of wires 140 , and the wires 140 are wires used in a semiconductor wire bonding process. Generally, each of the wires 140 vertically passes through the silicon oxide substrate layer 110 from the first surface 111 to the second surface 112 . In detail, the plurality of first pads 122 of the first circuit layer 120 are respectively arranged on one end (upper end) of the plurality of wires 140 located on the first surface 111, and the plurality of pads of the second circuit layer 130 The second welding pads 132 are respectively arranged on one end (lower end) of the plurality of wires 140 located on the second surface 112, and the plurality of first welding pads 122 and the plurality of second welding pads 132 pass through the plurality of second welding pads 132 respectively. The plurality of wires 140 are electrically connected.

In summary, the silicon oxide substrate layer 110 and the multiple wires 140 of the circuit substrate structure 100 of this embodiment can replace the functions of the existing silicon spacer layer and through-silicon via (TSV, Through-Silicon Via) to be used in a The electrical connection between the upper and lower surface circuits of the spacer (interposer).

Please refer to FIGS. 2A-2H , which are schematic views of a manufacturing method of a circuit substrate structure according to an embodiment of the present invention. The manufacturing method of the circuit substrate structure according to an embodiment of the present invention includes the following steps:

As shown in FIG. 2A, in a step (a), a wire bonding carrier 10 is firstly provided. The wire bonding carrier 10 is, for example, a round or square substrate, and can be a wafer or a metal plate. . If the wire-bonding carrier plate 10 is a wafer, its surface can be plated with a metal material (such as gold Au or aluminum Al) to facilitate subsequent wire-bonding operations;

As shown in Figure 2B, in a step (b), a plurality of wires 20 are vertically punched on the wire bonding carrier board 10 in a wire bonding manner, each of the wires 20 is placed on the wire bonding carrier board 10 Generate a knotted ball 21, then cut it vertically upwards for a preset length, the preset length is, for example, between 50 and 500 microns;

As shown in FIG. 2C, in a step (c), a container mold 30 is provided, and the wire bonding carrier plate 10 and a plurality of wires 20 combined thereon are put into the container mold 30;

Next, as shown in FIG. 2D, a tetraethoxysilane sol-gel hybrid solution (TEOSsol-gelpolymer hybrid solution) 40 is poured into the container mold 30, and the height of the sol-gel composite solution 40 is about higher than (also may be equal to or slightly less than) the height of the plurality of wires 20, so as to impregnate the plurality of wires 20 on the wire bonding carrier board 10;

Then, as shown in FIG. 2E, in a step (d), the sol-gel composite solution 40 in the container mold 30 is solidified to form a silicon oxide substrate layer 110, and a cover plate 31 can be used in this step The container mold 30 is temporarily covered. The sol-gel process (sol-gel process) is an existing known technology for making inorganic silicate glass at room temperature. Its principle is to use silane compound (silane) to carry out hydrolysis continuously ) and condensation (condensation) reaction is completed. This production method reacts quickly and can be completed at room temperature;

Afterwards, as shown in FIG. 2F , the silicon oxide substrate layer 110 is taken out from the container mold 30;

As shown in Figure 2G, in a step (e), the upper surface of the silicon oxide substrate layer 110 is ground and thinned until the upper surface of the silicon oxide substrate layer 110 is aligned with the upper ends of the plurality of wires 20 flat (that is, the upper ends of the plurality of wires 20 are exposed), so as to form a first surface 111 of the silicon oxide substrate layer 110;

As shown in FIG. 2H , in a step (f), remove the wire bonding carrier plate 10 and grind and thin the lower surface of the silicon oxide substrate layer 110 until the wire bonding ball at the lower end of the wire 20 is removed. 21 and expose the lower ends of the plurality of wires 20 to form a second surface 112 of the silicon oxide substrate layer 110, so that the outer diameters of the upper ends and lower ends of the plurality of wires 20 (140) are consistent.

In summary, through the various steps of the method for manufacturing the above-mentioned circuit substrate structure, the silicon oxide substrate layer 110 in the circuit substrate structure 100 shown in FIG. 140 can replace the functions of the existing silicon spacers and through-silicon vias (TSVs), and compared with the existing TSVs, which are more time-consuming to manufacture, the present invention combines the wire bonding process and the sol-gel method to replace the existing silicon The manufacturing method of the circuit substrate structure with through holes can save processing time and reduce manufacturing cost.

In addition, since the wire 140 is a wire used in the semiconductor chip bonding process, and its material can be selected from gold, silver or copper, the wire can have a metal purity of 99.9%. Method Electroplated metal pillars with insulating walls can achieve relatively higher metal purity. Moreover, the arrangement of the plurality of wires 140 can be designed according to the circuit requirements of the first circuit layer 120 and the second circuit layer 130; or the first circuit layer 120 and the second circuit layer 130 The lines of the wires 140 can be designed according to the arrangement of the plurality of wires 140 .

Please refer to FIG. 3 . FIG. 3 is a side cross-sectional view of a circuit substrate structure applied to a stacked chip package structure according to another embodiment of the present invention. A circuit substrate structure 100 of the present invention can be further applied in a 3D stacked chip packaging structure as a spacer layer. As shown in FIG. 3 , a chip 200 is stacked above the circuit substrate structure 100 and the circuit substrate structure 100 is stacked on a circuit board 300 . Wherein, the first circuit layer 120 on the upper surface of the circuit substrate structure 100 is electrically connected to the pad (not marked) corresponding to the chip 200 through a plurality of bumps 151; and the circuit substrate structure 100 on the lower surface The second circuit layer 130 is electrically connected to the corresponding pad (not marked) of the circuit board 300 through a plurality of bumps 152, so that the circuit substrate structure 100 of the present invention can be disposed in the silicon oxide substrate layer 110 The plurality of wires 140 are electrically connected to the chip 200 and the circuit board 300 , which is beneficial to the development of 3D stack packaging technology and can effectively improve the integration and performance of the chip.

The present invention has been described by the above-mentioned related embodiments, however, the above-mentioned embodiments are only examples for implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the claims are included in the scope of the present invention.

Claims (3)

1. a manufacture method for circuit substrate, is characterized in that: described manufacture method comprises following steps:

A () provides a routing loading plate;

B multiple wire is vertically beaten on described routing loading plate in routing mode by (), wire described in each produces a thread tacking ball on described routing loading plate, then blocks after a preset length vertically upward;

C () utilizes the multiple wires on routing loading plate described in the impregnation of a kind of tetraethoxysilane collosol and gel composite solution;

D () makes described collosol and gel composite solution solidify formation silica substrate layer;

E the upper surface of silica substrate layer described in () grinding thinning, until the upper end of exposed described multiple wire, to form a first surface of described silica substrate layer; And

F () removes the lower surface of silica substrate layer described in described routing loading plate and grinding thinning, until remove the routing balling of described wire lower end and the lower end of exposed described multiple wire, to form a second surface of described silica substrate layer.

2. the manufacture method of circuit substrate as claimed in claim 1, it is characterized in that: after (f) step, described manufacture method separately comprises:

G () arranges a first line layer at the first surface of described silica substrate layer, described first line layer comprises multiple first weld pad and one first welding resisting layer, and wherein said multiple first weld pad is located at one end that described multiple wire is positioned at described first surface respectively; Described first welding resisting layer exposes the some of the first weld pad described in each to the open air.

3. the manufacture method of circuit substrate as claimed in claim 2, it is characterized in that: after (f) or (g) step, described manufacture method separately comprises:

H () arranges one second line layer at the second surface of described silica substrate layer, described second line layer comprises multiple second weld pad and one second welding resisting layer, and wherein said multiple second weld pad is located at one end that described multiple wire is positioned at described second surface respectively; Described second welding resisting layer exposes the some of the second weld pad described in each to the open air.