CN103165553A - Semiconductor wafer and semiconductor package - Google Patents

Abstract

A semiconductor wafer and a semiconductor package are provided. The semiconductor wafer comprises a plurality of chips, each chip is provided with an active surface and a plurality of connecting pads formed on the active surface; an insulating layer formed on the active surface of the chip and having a plurality of opening structures correspondingly exposing the pads, wherein the opening structures include a central opening and at least two extension slots, the aperture of the central opening is smaller than the diameter of the pads, and the extension slots radially extend outwards from the edge of the central opening and keep a distance with the edge of the pads; a plurality of under bump metallurgy layers respectively formed on the opening structure and electrically connected to the pads; and a plurality of conductive bumps respectively formed on the under bump metallurgy layer. The opening structure of the insulating layer is beneficial to enhancing the stress buffering effect and increasing the combination area of the under bump metal layer and the connecting pad.

Description

Semiconductor wafer and semiconductor package structure

technical field

The invention relates to a semiconductor structure, in particular to a semiconductor wafer with bumps and a semiconductor packaging structure.

Background technique

Nowadays, the semiconductor packaging industry has developed various types of packaging structures to meet various demands. In terms of flip chip technology, basically a plurality of conductive bumps are placed on the pads on the active surface of the chip, and then the chip is turned over so that the chip is placed on a substrate through the bumps, and then packaged Adhesive wrapping operation to complete the fabrication of semiconductor packaging structure.

The above process of disposing bumps on the pads on the active surface of the chip can usually be performed directly on the wafer. Generally speaking, an Under-Bump Metallization (UBM) layer is firstly provided on the pad to strengthen the connection between the bump and the pad. The pads on the active surface will cause stress to concentrate on the UBM layer and the peripheral position of the pads and directly transfer to the insulating layer (made of fragile low dielectric material) between the active circuits in the active surface of the chip. Therefore, an insulating layer is provided on the active surface of the chip, so that the UBM layer is electrically connected to the pad on the active surface through the opening of the insulating layer, so as to achieve the effect of buffering stress through the insulating layer.

However, in order to increase the buffering effect, although the opening of the insulating layer can be reduced to increase the buffering area provided by the insulating layer on the pad, this will cause cracks on the connection surface between the UBM layer and the pad. The growth path is shortened, which in turn accelerates the generation of cracks in the metal layer under the bump; and reduces the bonding area and reduces the reliability of the connection between the pad and the bump.

Therefore, it is necessary to provide a semiconductor wafer and a semiconductor package structure to solve the problems existing in the prior art.

Contents of the invention

The main purpose of the present invention is to provide a semiconductor wafer, which is provided with an insulating layer with a specific shape opening structure on the pad of the active surface of the chip, which helps to strengthen the stress buffering effect and increase the bonding reliability.

To achieve the aforementioned object, an embodiment of the present invention provides a semiconductor wafer, the semiconductor wafer includes: a plurality of chips, each of which has an active surface and a plurality of chips formed on the active surface Pad; an insulating layer formed on the active surface of the chip, and has a plurality of opening structures corresponding to expose the pad, the opening structure includes a central opening and at least two extending slots, the central The aperture of the opening is smaller than the diameter of the pad, and the extending slot radially extends outward from the edge of the central opening and maintains a distance from the edge of the pad; a plurality of UBM layers are respectively formed on the pads The pad is electrically connected to the opening structure; and a plurality of conductive bumps are respectively formed on the UBM layer.

Another embodiment of the present invention provides a semiconductor packaging structure, the semiconductor packaging structure includes: a packaging substrate; a chip, electrically connected to a surface of the packaging substrate through a plurality of conductive bumps, the chip has a Active surface and a plurality of pads formed on the active surface, an insulating layer is provided on the active surface, the insulating layer has a plurality of opening structures corresponding to the exposed pads, the opening structure It includes a central opening and at least two extending slots, the diameter of the central opening is smaller than the diameter of the pad, and the extending slots radially extend outward from the edge of the central opening and maintain an alignment with the edge of the pad. spacing; each of the opening structures is provided with an under bump metal layer, and the under bump metal layer is electrically connected to the pad and the conductive bump; and a packaging adhesive is provided on the packaging substrate The chip is coated on the surface of the chip.

Since the opening structure of the insulating layer has a central opening and an extended slot, the smaller central opening can provide more buffer area for the insulating layer, and the extended slot can increase the bonding area between the metal layer under the bump and the pad, and at the same time It can also increase the crack growth path of the UBM layer, and delay the failure time of the UBM layer structure.

Description of drawings

FIG. 1 is a partial top view of a semiconductor wafer according to an embodiment of the present invention.

FIG. 2 is a partially enlarged schematic diagram of FIG. 1 .

FIG. 3A is a schematic cross-sectional view taken along line A-A of FIG. 2 .

FIG. 3B is a schematic cross-sectional view taken along line B-B in FIG. 2 .

FIG. 4 is a schematic cross-sectional view of a semiconductor wafer according to another embodiment of the present invention.

FIG. 5 is a schematic partial cross-sectional view of a semiconductor package structure according to an embodiment of the present invention.

6A-6D are schematic diagrams of the fabrication process of conductive bumps on a semiconductor wafer according to an embodiment of the present invention.

Detailed ways

In order to make the above objects, features and advantages of the present invention more comprehensible, preferred embodiments of the present invention are exemplified below and described in detail in conjunction with the accompanying drawings. Furthermore, the directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., It is only for orientation with reference to the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present invention, but not to limit the present invention.

Please refer to Fig. 1, Fig. 2, Fig. 3A and Fig. 3B, Fig. 1 is a partial top view of a semiconductor wafer according to an embodiment of the present invention; Fig. 2 is a partially enlarged schematic view of Fig. 1; Fig. 3A is along A-A of Fig. 2 3B is a schematic sectional view viewed along the line B-B in FIG. 2 . The semiconductor wafer 1 disclosed in the present invention includes a plurality of undiced chips 10 , an insulating layer 13 , a plurality of UBM layers 17 and a plurality of conductive bumps 15 .

As shown in FIG. 3A , each chip 10 has an active surface and a plurality of pads 16 formed on the active surface, and the pads 16 may be aluminum pads. The active surface of each chip 10 is provided with a passivation layer 11, as shown in FIG. The lip of the opening 110 of the passivation layer 11 on the pad 16 partially covers the edge of the pad 16 , and the range of the opening 110 of each passivation layer 11 is smaller than the diameter of the pad 16 . The passivation layer 11 can be, for example, silicon dioxide.

2, FIG. 3A and FIG. 3B, the insulating layer 13 is a non-conductive organic polymer material, such as polyimide (Polyimide), which is formed on the active surface of the chip 10. , and has a plurality of opening structures 14 corresponding to the bare pads 16, the opening structure 14 includes a central opening 140 and at least two extending slots 141, the central opening 14 is concentrically arranged on the pads 16 and The aperture of the central opening 14 is smaller than the diameter of the bonding pad 16 , and the extending slot 141 extends radially outward from the edge of the central opening 140 and maintains a distance from the edge of the bonding pad 16 with a width less than Aperture of the central opening 140 . In this embodiment, the opening structure 14 includes four extending slots 141 , wherein the angle between any two adjacent extending slots 141 is approximately 90 degrees, that is, the extending slots 141 are arranged in a cross shape. As shown in FIG. 2 , in one embodiment, when the diameter of the central opening 140 is d1 and the total length of the two opposite extending slots 141 plus the diameter of the central opening 140 is d2, d2 and d1 The ratio of may be, for example, between 110% and 130%. For example, when the diameter of the central opening 140 is 85 microns, the total length of the two opposite extending slots 141 plus the diameter of the central opening 140 may be between 95 microns and 112 microns. It should be noted that, as shown in FIG. 2 , the total length of the two opposite extending slots 141 plus the diameter of the central opening 140 , that is, the maximum opening range of the opening structure 14 , is still less than the total length of the opening. The area range of the pad 16 is described above.

The extending slots 141 of the opening structure 14 are not limited to the arrangement and number of the embodiment shown in FIG. One extension slot 141, wherein the angle between any two adjacent extension slots 141 is approximately 120 degrees; or eight extension slots 140, the angle between any two adjacent extension slots 141 is approximately The angle is 45 degrees, that is, the extending slots 141 are arranged in the shape of a rice.

Referring to FIG. 3A and FIG. 3B , the UBM layers 17 are respectively formed on the opening structures 14 and electrically connected to the pads 16 . The UBM layer 17 can be, for example, a nickel/gold composite layer, a titanium/copper composite layer or a solder material.

Referring to FIG. 3A and FIG. 3B , the conductive bumps 15 are respectively formed on the UBM layers 17 . The conductive bump 15 is a lead-free tin bump or a tin-lead bump in this embodiment.

In the above-mentioned semiconductor wafer, since the opening structure 14 of the insulating layer 13 has a central opening 140 and an extended groove 141, as shown in FIG. 3A, the insulating layer 13 outside the edge of the central opening 140 with a smaller aperture It has a larger overlapping area with the UBM layer 17, which can provide more stress buffering areas between the UBM layer 17 and the pad 16; and as shown in FIG. 3B, the bump The under-block metal layer 17 forms a main contact joint area with the contact pad 16 through the central opening 140 of the insulating layer 13, and the main contact joint area has a relatively small contact joint; however, the under-bump The metal layer 17 passing through the extended slot 141 can relatively increase the contact bonding area between the UBM layer 17 and the pad 16, thereby increasing the reliability of the conductive bump 15 to electrically connect the pad 16 indirectly. At the same time, the stress can be dispersed at the connection between the UBM layer 17 and the extending slot 141, especially concentrated at the outermost edge of the extending slot 141, which makes the UBM Cracks in the metal layer 17 are generated at these secondary connection locations without affecting the above-mentioned primary contact bonding areas. Therefore, the extending groove 141 also helps to increase the crack growth path between the UBM layer 17 and the pad 16 , thereby delaying the structural failure time of the UBM layer 17 . Therefore, the semiconductor wafer of the present invention can simultaneously enhance the effect of stress buffering and increase the reliability of the electrical connection of the conductive bump 15 .

Please refer to FIG. 4 , which is a schematic cross-sectional view of a semiconductor wafer according to another embodiment of the present invention. Compared with the semiconductor wafer in the embodiment in FIG. 3A , the difference in the embodiment in FIG. 4 is that the conductive bumps are copper stud bumps 18 , and a nickel layer 19 and a solder material 20 can be further sequentially formed on the top surface thereof. .

Please refer to FIGS. 6A to 6D , which respectively briefly reveal the structural schematic diagrams of the conductive bumps of the semiconductor wafer made in the embodiment of FIG. 4 . The slot 141 and central opening 140 are extended for comparison.

Referring to FIG. 6A , firstly, the insulating layer 13 is formed on the chip 10 of the semiconductor wafer, and the opening structure 14 including the central opening 140 and the extending groove 141 is formed through a photolithography process, so that the opening structure 14 is correspondingly exposed. The contact pad 16 on the active surface of the chip 10; then further form the UBM layer 17 on the insulating layer 13 (together with the opening structure 14);

Next, please refer to FIG. 6B , coat photoresist 22 on the surface of the UBM layer 17 , and then remove part of the photoresist 22 through steps such as exposure and development, so that the bump corresponding to the position of the opening structure 14 The metal layer 17 under the block is exposed;

Subsequently, referring to FIG. 6C , electroplating copper post bumps 18 on the exposed UBM layer 17 as the conductive bumps, and sequentially forming a nickel layer on the top surface of the copper post bumps 18 19 and a solder material 20;

Then, referring to FIG. 6D , the remaining photoresist 22 is then removed, and an etching process is performed on the exposed UBM layer 17 after removing the remaining photoresist 22, so that the adjacent copper pillar bumps 18 are insulated and separated, and finally through the reflow step, the conductive bump structure of the semiconductor wafer of the embodiment of the present invention shown in FIG. 4 is completed.

Further referring to FIG. 5 , FIG. 5 is a schematic partial cross-sectional view of a semiconductor package structure according to an embodiment of the present invention. The semiconductor package structure includes not only the chips 10 cut from the above-mentioned semiconductor wafer, but also includes a package substrate 30 and a package adhesive 33 .

The packaging substrate 30 can be formed by glass fiber and epoxy resin to form its insulating layer first, and then alternately stack the insulating layer and the circuit layer. The upper surface of the packaging substrate 30 is provided with several electrical connection parts 31 , such as copper bumps, and the lower surface is provided with solder balls 32 . The chip 10 is electrically connected to several electrical connection portions 31 on the upper surface of the packaging substrate 30 through the conductive bumps 15 .

The encapsulation material 33 can be, for example, epoxy resin, which is disposed on the surface of the encapsulation substrate 33 to cover the chip 10 .

Compared with the existing semiconductor wafers, which cannot simultaneously improve the stress buffering effect and the bonding reliability of the bumps, the semiconductor wafer and the semiconductor package structure of the present invention have a central opening and an extended slot through the opening structure of the passivation layer. The passivation layer can provide more buffer areas with a smaller central opening, and the bonding area between the metal layer under the bump and the pad can be increased by extending the groove, so the present invention can provide a better stress buffer effect and increase the bump The crack growth path of the under-bump metal layer delays the failure time of the under-bump metal layer structure, thereby enhancing the reliability of the bump bonding.

The present invention has been described by the above-mentioned related embodiments, however, the above-mentioned embodiments are only examples for implementing the present invention. It must be pointed out that the disclosed embodiments do not limit the scope of the invention. On the contrary, modifications and equivalent arrangements included in the spirit and scope of the claims are included in the scope of the present invention.

Claims (10)

1. A semiconductor wafer, characterized in that: the semiconductor wafer comprises: a plurality of chips, each of the chips having an active surface and a plurality of pads formed on the active surface; An insulating layer is formed on the active surface of the chip, and has a plurality of opening structures corresponding to the exposed pads, the opening structure includes a central opening and at least two extending slots, and the aperture of the central opening is smaller than the diameter of the pad, the extending slot radially extends outward from the edge of the central opening and maintains a distance from the edge of the pad; A plurality of UBM layers are respectively formed on the opening structure and electrically connected to the pad; and A plurality of conductive bumps are respectively formed on the UBM layer. 2. The semiconductor wafer as claimed in claim 1, wherein at least two of the extended slots face each other at 180 degrees. 3 . The semiconductor wafer according to claim 1 , wherein the opening structure of the insulating layer comprises four extending slots, and the angle between any two adjacent extending slots is 90 degrees. 4 . 4 . The semiconductor wafer according to claim 1 , wherein the opening structure of the insulating layer comprises eight extending slots, and the angle between any two adjacent extending slots is 45 degrees. 5 . The semiconductor wafer according to claim 1 , wherein: the insulating layer is a non-conductive organic polymer material; and the conductive bumps are tin bumps or copper pillar bumps. 6. The semiconductor wafer according to claim 1, wherein the UBM layer is a nickel/gold composite layer, a titanium/copper composite layer or a solder material. 7. A semiconductor package structure, characterized in that: the semiconductor package structure comprises: a packaging substrate; A chip is electrically connected to a surface of the packaging substrate through a plurality of conductive bumps, the chip has an active surface and a plurality of pads formed on the active surface, the active surface An insulating layer is provided, the insulating layer has a plurality of opening structures corresponding to the exposed pads, the opening structure includes a central opening and at least two extending slots, and the diameter of the central opening is smaller than the diameter of the pads , the extending groove radially extends outward from the edge of the central opening and maintains a distance from the edge of the pad; each of the opening structures is provided with an under bump metal layer, and the under bump metal layer electrically connecting the pad and the conductive bump; and An encapsulation adhesive is provided on the surface of the encapsulation substrate to cover the chip. 8. The semiconductor package structure as claimed in claim 7, wherein at least two of the extending slots are opposite to each other at 180 degrees. 9 . The semiconductor package structure according to claim 7 , wherein the opening structure of the insulating layer comprises four extending slots, and the angle between any two adjacent extending slots is 90 degrees. 10 . The semiconductor package structure according to claim 7 , wherein the opening structure of the insulating layer comprises eight extending slots, and the angle between any two adjacent extending slots is 45 degrees. 11 .

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