CN103176941B - Communication method between cores and agent apparatus - Google Patents

Abstract

Embodiments of the present invention provide an inter-core communication method and a proxy device. The method includes that the proxy device receives the access request sent by the core that initiates the access; the proxy device determines the accessed core corresponding to the access request according to the pre-configured correspondence; the proxy device initiates an access request to the accessed core communication, so as to realize the communication between the access-initiating core and the accessed core; wherein, the proxy device is interposed between the access-initiating core and the accessed core. The embodiments of the present invention can improve the processing performance of multi-core communication.

Description

Inter-core communication method and proxy device

technical field

The invention relates to communication technology, in particular to an inter-core communication method and agent device.

Background technique

A multi-core processor can also be called a chip multi-processor (ChipMulti-Processor, CMP). Its structure is mainly to simplify the superscalar structure and integrate multiple relatively simple superscalar processor cores into one chip. In order to improve the performance of multi-core processors, it is necessary to adopt different interconnection methods and technologies for multi-processor cores with different numbers and structures to achieve optimal performance. At present, multi-core interconnection communication mainly includes core series communication, shared bus structure, and crossbar interconnection.

Core serial communication means that after the communication from core 1 to core 2 is completed, core 2 initiates communication to core 3, and so on, to complete the communication of all specified cores, and the communication is reported by interruption. The structural advantage of this system is that Simple, but slow to process. The shared bus structure (ShareBusFabric, SBF) can use the bus interconnection method of the linear array, which can enable the processing unit, memory, and external devices to use the bus in different segments at the same time, reducing the delay caused by the competition between the modules to use the bus. When , the efficiency of bus usage is greatly improved, but when there are many connected processor cores, the competition will still be serious. The crossbar interconnection can be composed of a crossbar and crossbar interface logic, each crossbar is composed of some address lines and data lines, and the crossbar interface logic is mainly composed of some load queues. The crossbar can enable the nodes connected to the switch structure to exchange data at the same time, which ensures the parallelism of data processing by the multi-core processor in space, and greatly improves the bandwidth of the bus. However, its structural complexity is high, and once the number of integrated cores is large, the performance will decrease.

Contents of the invention

In view of this, an embodiment of the present invention provides an inter-core communication method and a proxy device to solve the problems of slow processing speed or complex structure and low performance in the prior art.

In a first aspect, an inter-core communication method is provided, including:

The proxy device receives the access request sent by the core that initiates the access;

The proxy device determines the accessed core corresponding to the access request according to the pre-configured correspondence;

The agent device initiates communication with the accessed core, so as to realize the communication between the access-initiating core and the accessed core;

Wherein, the proxy device is located between the access-initiating core and the accessed core.

With reference to the first aspect, in a first possible implementation manner of the first aspect, the proxy device determines the accessed core corresponding to the access request according to a pre-configured correspondence, including:

The proxy device determines a hardware unit corresponding to the access request, wherein the hardware unit is pre-configured in the proxy device;

The proxy device determines the core to be accessed corresponding to the access request according to the pre-configured correspondence in the hardware unit.

With reference to the first aspect, in a second possible implementation manner of the first aspect, the proxy device determines the accessed core corresponding to the access request according to a pre-configured correspondence, including:

The agent device judges whether the number of times of triggering the programmable unit reaches a preset number of times, wherein the programmable unit is pre-configured in the agent device, and each valid access request triggers the programmable unit once;

When the judging result is that the preset number of times is reached, the agent device determines the core to be accessed corresponding to the access request according to a pre-configured correspondence.

With reference to the first or second possible implementation of the first aspect, in a third possible implementation of the first aspect, the access request is an instruction, and the instruction includes the Processor core ID and/or address information, described method also comprises:

The proxy device judges whether the access request is valid according to the processor core ID and/or address information, so as to determine the accessed core corresponding to the access request according to a pre-configured correspondence relationship if valid.

With reference to the second possible implementation of the first aspect, in the fourth possible implementation of the first aspect, the access request is a message, and the determination of whether the number of times the programmable unit is triggered reaches the preset number of times , the method also includes:

performing a bitwise OR operation on all or part of the bits contained in the message and a preset first bit string;

The bit string after the bitwise OR operation is compared with the preset second bit string, and if they are the same, it is determined that the access request is valid.

In a second aspect, a proxy device is provided, the proxy device is located between a core that initiates an access and a core that is accessed, and the device includes:

A receiving module, configured to receive an access request sent by the core that initiates the access;

a processing module, configured to determine the accessed core corresponding to the access request received by the receiving module according to a pre-configured correspondence;

A sending module, configured to initiate communication with the accessed core determined by the processing module, so as to realize communication between the access-initiating core and the accessed core.

With reference to the second aspect, in a first possible implementation manner of the second aspect, the processing module includes:

A determining unit, configured to determine a hardware unit corresponding to the access request, wherein the hardware unit is pre-configured in the proxy device;

The hardware unit is configured to determine the accessed core corresponding to the access request according to its pre-configured correspondence.

With reference to the second aspect, in a second possible implementation manner of the second aspect, the processing module includes:

A programmable unit, which includes a counter and a determination unit;

The counter is used to judge whether the number of times of triggering the programmable unit reaches a preset number of times, wherein each valid access request triggers the programmable unit once;

The determining unit is configured to determine the accessed core corresponding to the access request according to a pre-configured correspondence relationship when the determination result of the counter reaches a preset number of times.

With reference to the first or second possible implementation of the second aspect, in a third possible implementation of the second aspect, the access request is an instruction, and the instruction includes the Processor core ID and/or address information, the device also includes:

A first judging module, configured to judge whether the access request is valid according to the processor core ID and/or address information, so as to determine the accessed core corresponding to the access request according to a pre-configured correspondence when valid .

With reference to the second possible implementation of the second aspect, in a fourth possible implementation of the second aspect, the access request is a message, and the device further includes:

The second decision module is used to perform a bitwise OR operation on all or part of the bits contained in the message and a preset first bit string; and perform a bitwise OR operation on the bitwise OR-operated bit string with a preset second bit Strings are compared, and if they are the same, it is determined that the access request is valid.

Through the above technical solution, an agent device is set between the core that initiates the access and the core that is accessed, and the corresponding relationship is pre-configured in the agent device, and the communication between the core that initiates the access and the core that is accessed can be realized according to the corresponding relationship, The processing speed can be increased and the complexity can be reduced, thereby improving the processing performance of inter-core communication.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings that need to be used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained based on these drawings without any creative effort.

FIG. 1 is a schematic flowchart of an inter-core communication method provided by an embodiment of the present invention;

FIG. 2 is a schematic flowchart of another inter-core communication method provided by an embodiment of the present invention;

FIG. 3a is a schematic diagram of inter-core communication using an interrupt mode in a 1-to-1 scenario when a hardware unit is configured in an embodiment of the present invention;

FIG. 3b is a schematic diagram of inter-core communication using message mode in a 1-to-1 scenario when hardware units are configured in an embodiment of the present invention;

FIG. 4a is a schematic diagram of inter-core communication using an interrupt mode in a 1-to-many scenario when a hardware unit is configured in an embodiment of the present invention;

FIG. 4b is a schematic diagram of inter-core communication using message mode in a 1-to-many scenario when hardware units are configured in an embodiment of the present invention;

FIG. 5a is a schematic diagram of inter-core communication using an interrupt mode in a many-to-one scenario when configuring hardware units in an embodiment of the present invention;

FIG. 5b is a schematic diagram of inter-core communication using message mode in a many-to-one scenario when hardware units are configured in an embodiment of the present invention;

FIG. 6a is a schematic diagram of inter-core communication using an interrupt mode in a many-to-many scenario when configuring hardware units in an embodiment of the present invention;

FIG. 6b is a schematic diagram of inter-core communication using message mode in a many-to-many scenario when hardware units are configured in an embodiment of the present invention;

FIG. 7 is a schematic flowchart of another inter-core communication method provided by an embodiment of the present invention;

Fig. 8a is a schematic diagram of inter-core communication in an interrupt mode when a programmable unit is configured and the access request is an instruction in an embodiment of the present invention;

Fig. 8b is a schematic diagram of inter-core communication in message mode when the programmable unit is configured and the access request is an instruction in the embodiment of the present invention;

FIG. 9 is a schematic flowchart of another inter-core communication method provided by an embodiment of the present invention;

FIG. 10 is a schematic diagram of validating an access request when the access request is a message in an embodiment of the present invention;

Figure 11a is a schematic diagram of inter-core communication in an interrupt mode when a programmable unit is configured and the access request is a message in an embodiment of the present invention;

Fig. 11b is a schematic diagram of inter-core communication using a message mode when a programmable unit is configured and the access request is a message in an embodiment of the present invention;

FIG. 12 is a schematic structural diagram of an agent device provided by an embodiment of the present invention;

FIG. 13 is a schematic structural diagram of another agent device provided by an embodiment of the present invention.

detailed description

In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments It is a part of embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

FIG. 1 is a schematic flow diagram of an inter-core communication method provided by an embodiment of the present invention, including:

11: The proxy device receives the access request sent by the core that initiates the access;

Wherein, the proxy device is a newly added device arranged between the core that initiates the access and the core that is accessed. The communication between the core that initiates the access and the core that is accessed can be completed through the proxy device.

Optionally, the access request may be an instruction, that is, it does not contain specific content, but only contains the processor core ID of the core that initiates the access and/or the address information of the address to be accessed. or,

Optionally, the access request may be a message, which is different from the instruction in that the message contains specific content, for example, a 32-bit bit string.

12: The proxy device determines the accessed core corresponding to the access request according to the pre-configured correspondence;

Optionally, the corresponding relationship may be configured in a hardware unit, and the hardware unit is pre-configured in the agent device. The number of hardware units can be in one-to-one correspondence with the cores that initiate access. For example, if the core that initiates access is core 0, then the corresponding hardware unit can be hardware unit 0, and the core that initiates access is core 1, then the corresponding hardware unit can be It is hardware unit 1, and so on.

Optionally, the corresponding relationship may be configured in a programmable unit, and the programmable unit is pre-configured in the agent device. A counter can also be configured in the programmable unit, so that when the value of the counter reaches a pre-configured number of times, corresponding communication is initiated according to the corresponding relationship.

13: The proxy device initiates communication with the accessed core, so as to implement communication between the access-initiating core and the accessed core.

Optionally, the proxy device determines the accessed core corresponding to the access request according to a pre-configured correspondence, including:

The proxy device determines a hardware unit corresponding to the access request, wherein the hardware unit is pre-configured in the proxy device;

The proxy device determines the core to be accessed corresponding to the access request according to the pre-configured correspondence in the hardware unit.

Optionally, the proxy device determines the accessed core corresponding to the access request according to a pre-configured correspondence, including:

The agent device judges whether the number of times of triggering the programmable unit reaches a preset number of times, wherein the programmable unit is pre-configured in the agent device, and each valid access request triggers the programmable unit once;

When the judging result is that the preset number of times is reached, the agent device determines the core to be accessed corresponding to the access request according to a pre-configured correspondence.

Optionally, the access request is an instruction, the instruction includes the processor core ID and/or address information of the core that initiates the access, and the method further includes:

The proxy device judges whether the access request is valid according to the processor core ID and/or address information, so as to determine the accessed core corresponding to the access request according to a pre-configured correspondence relationship if valid.

Optionally, the access request is a message, and the method further includes:

performing a bitwise OR operation on all or part of the bits contained in the message and a preset first bit string;

The bit string after the bitwise OR operation is compared with the preset second bit string, and if they are the same, it is determined that the access request is valid.

In this embodiment, an agent device is set between the core that initiates the access and the core that is accessed, and the corresponding relationship is pre-configured in the agent device. According to the corresponding relationship, the communication between the core that initiates the access and the core that is accessed can be realized. The processing speed is increased and the complexity can be reduced, thereby improving the processing performance of inter-core communication.

FIG. 2 is a schematic flowchart of another inter-core communication method provided by an embodiment of the present invention. This embodiment takes the configuration of hardware units as an example. This embodiment includes:

21: The core that initiates the access sends an access request to the proxy device;

The access request may be an instruction, which includes processor core ID and/or address information of the core that initiates the access.

22: The proxy device judges whether the access request is valid, if yes, execute 23, otherwise execute 25.

Wherein, the proxy device can judge whether the access request is valid according to the processor core ID and/or address information included in the access request. For example, the proxy device can pre-configure a list of valid processor core IDs. When the device core ID belongs to the list of processor core IDs, the judgment result is that the access request is valid; or, an effective address information list can be pre-configured in the agent device, and when the address information contained in the access request belongs to the address information list , then the judgment result is that the access request is valid; or, the proxy device can be pre-configured with a valid processor core ID list and address information list, when the processor core ID contained in the access request belongs to the processor core ID list, and When the address information contained in the access request belongs to the address information list, the determination result is that the access request is valid.

23: The agent device determines the corresponding hardware unit according to the access request.

After it is determined that the access request is valid, the corresponding hardware unit may be determined according to the processor core ID and/or address information carried in the access request. For example, the corresponding relationship between processor cores and hardware units can be configured in advance, for example, processor core 0 is configured to correspond to hardware unit 0, and processor core 1 is corresponding to hardware unit 1. Therefore, when the processor core ID is 0, the corresponding The hardware unit is hardware unit 0. Alternatively, address information is configured for each hardware unit. For example, the address information of hardware unit 0 is address 0. When the address information included in the access request is address 0, it can be determined that the corresponding hardware unit is hardware unit 0. Of course, the corresponding corresponding relationship may also be jointly configured in combination with the processor ID and address information.

24: The corresponding hardware unit determines the accessed core corresponding to the access request according to the pre-configured correspondence, and initiates communication with the accessed core.

For example, when the corresponding hardware unit is hardware unit 0, hardware unit 0 receives the access request, and the corresponding relationship can be pre-configured in hardware unit 0, for example, the core to be accessed corresponding to hardware unit 0 is processor core 20, then when After receiving the access request, the hardware unit 0 can initiate access to the processor core 20 .

In addition, when there are multiple cores that initiate access, identification signals may be set in corresponding hardware units, and when the identification signals of all corresponding hardware units are valid, communication with the accessed cores is initiated. Wherein, each hardware unit may mark the identification signal of its corresponding hardware unit as valid after receiving the access request. For example, processor core 10 and processor core 11 initiate access, and the corresponding hardware units are hardware unit 0 and hardware unit 1, then when hardware unit 0 receives the access request sent by processor core 10, hardware unit 0 can The identification signal of itself is set to valid, and after the hardware unit 1 receives the access request sent by the processor core 11, the hardware unit 1 can set the identification signal of itself to be valid, when the identification signal of the hardware unit 0 and the identification signal of the hardware unit 1 After the signals are valid, the hardware unit 0 can initiate communication to the corresponding accessed core according to the corresponding relationship configured by itself, and the hardware unit 1 can initiate communication to the corresponding accessed core according to the corresponding relationship configured by itself.

The above-mentioned setting identification signal can be effective at high level, and the latter is active at low level.

The communication initiated by the hardware unit and the accessed core can be in interrupt mode or in message mode. When it is a message, a cross switch needs to be set between the agent device and the core to be accessed.

25: End.

In the following embodiments, the initiating access core is at least one of a central processing unit (CentralProcessUnit, CPU), a digital signal processor (DigitalSignalProcessor, DSP), a hardware accelerator (HardwareAccelerator, HAC) and a direct memory access (DirectMemoryAccess, DMA), The core to be accessed is at least one of CPU0, CPU1, DSP0 and DSP1.

Referring to FIG. 3 a and FIG. 3 b , schematic diagrams of inter-core communication in an interrupt mode and in a message mode during 1-to-1 access are respectively shown. In this embodiment, the core that initiates access is DMA.

In the first step, the DMA sends an access request to the proxy device.

In the second step, after receiving the access request, the proxy device can judge whether the access request is valid, and determine the corresponding hardware unit. For specific processing procedures, refer to 22 and 23 above.

Assume that the corresponding hardware unit is hardware unit 0.

In the third step, hardware unit 0 receives the access request.

In the fourth step, the hardware unit 0 initiates communication according to the pre-configured corresponding relationship, and the accessed processor core specified by the corresponding relationship.

For example, if the pre-configured and corresponding accessed processor core in hardware unit 0 is CPU0, communication is initiated to CPU0.

Fig. 3a shows the way of using interrupt, in this way, the proxy device can directly initiate an interrupt to CPU0 through the interrupt interface.

Figure 3b shows the method of using messages. Usually there is only one message interface, that is, there is only one outgoing interface of the proxy device. At this time, a crossbar can be used to send messages to the corresponding processor cores. For example, through the crossbar The switch sends the message to CPU0.

Referring to FIG. 4 a and FIG. 4 b , schematic diagrams of inter-core communication in an interrupt mode and in a message mode for one-to-many access are respectively shown. In this scenario, there is one processor core that initiates the access, which is DMA, and there are multiple processor cores that are accessed, namely CPU0 and CPU1. Unlike the 1-to-1 scenario, a 1-to-many relationship can be pre-configured in hardware unit 0. For example, the configured accessed processor cores include CPU0 and CPU1, and the accessed cores that initiate communication include CPU0 and CPU1. For the rest of the process, please refer to the 1-to-1 scenario.

Referring to FIG. 5 a and FIG. 5 b , schematic diagrams of inter-core communication in an interrupt mode and in a message mode are respectively shown during the many-to-one access. In this scenario, there are multiple processor cores that initiate access, namely DMA, HAC, and DSP, and one processor core that is accessed is CPU0. Different from the 1-to-1 scenario, since there are multiple processors that initiate access, multiple hardware units may also be triggered, for example, hardware unit 0, hardware unit 1, and hardware unit 2 respectively. In addition, the accessed processor cores corresponding to the corresponding relationship of each hard disk unit configuration are the same. For example, the accessed processor core configured by hardware unit 0 is CPU0, the accessed processor core configured by hardware unit 1 is also CPU0, and the accessed processor core configured by hardware unit 2 is also CPU0. For the rest of the process, please refer to the 1-to-1 scenario.

Referring to FIG. 6 a and FIG. 6 b , schematic diagrams of inter-core communication in an interrupt mode and in a message mode for many-to-many access are respectively shown. In this scenario, there are multiple processor cores that initiate access, namely DMA, HAC, and DSP, and multiple processor cores that are accessed, namely CPU0, CPU1, and DSP0. Different from the 1-to-1 scenario, since there are multiple processor cores that initiate access, multiple hardware units may be triggered, for example, hardware unit 0, hardware unit 1, and hardware unit 2, respectively. In addition, the processor cores to be accessed corresponding to the corresponding relationships configured by each hard disk unit are different. For example, the accessed processor core configured by hardware unit 0 is CPU0, the accessed processor core configured by hardware unit 1 is CPU1, and the accessed processor core configured by hardware unit 2 is DSP0. For the rest of the process, please refer to the 1-to-1 scenario.

In this embodiment, by configuring the hardware unit, after the core that initiates the access sends the access request, the core to be accessed can be determined according to the corresponding relationship configured in the hardware unit, so as to realize inter-core communication. The overall performance can be improved through the proxy device. Multiple cores that initiate access can execute the access process in parallel, which improves the processing speed. By completing inter-core communication, it can ensure that the cores understand each other's status. By using messages to complete the inter-core communication, you can Improve the processing efficiency of the kernel.

Fig. 7 is a schematic flowchart of another inter-core communication method provided by an embodiment of the present invention. In this embodiment, a programmable unit is triggered and an access request is an instruction as an example. This embodiment includes:

71: The core that initiates the access sends an access request to the proxy device;

The access request may be an instruction, which includes processor core ID and/or address information of the core that initiates the access.

72: The proxy device judges whether the access request is valid, if so, execute 73, otherwise execute 75;

Wherein, the proxy device can judge whether the access request is valid according to the processor core ID and/or address information included in the access request. For example, the proxy device can pre-configure a list of valid processor core IDs. When the device core ID belongs to the list of processor core IDs, the judgment result is that the access request is valid; or, an effective address information list can be pre-configured in the agent device, and when the address information contained in the access request belongs to the address information list , then the judgment result is that the access request is valid; or, the proxy device can be pre-configured with a valid processor core ID list and address information list, when the processor core ID contained in the access request belongs to the processor core ID list, and When the address information contained in the access request belongs to the address information list, the determination result is that the access request is valid.

73: Trigger a preset programmable unit in the agent device when the access request is valid.

Wherein, a counter may be pre-configured in the programmable unit, and the counter may be a down counter or an up counter. When it is a down-counter, the configured initial value is a preset number of times, and then every time the programmable unit is triggered, the count value is reduced by 1 until it is reduced to 0. When it is an up-counter, the configured initial value is 0, and each time the programmable unit is triggered, the count value increases by 1 until it reaches the preset number of times.

74: When the number of times the programmable unit is triggered reaches a preset number of times, the agent device initiates communication to the corresponding accessed processor core according to the preconfigured correspondence.

For example, when a down counter is used, when the count value decreases to 0, it indicates that the number of times the programmable unit is triggered reaches the preset number of times, or, when an up counter is used, when the count value increases to the preset number of times, it indicates that the programmable unit The unit is triggered a preset number of times.

Initiating communication can also use interrupt mode or message mode.

75: End.

Referring to FIG. 8 a and FIG. 8 b , schematic diagrams of inter-core communication in an interrupt mode and in a message mode are respectively shown. During specific visits, the corresponding relationship can be configured according to the actual situation to complete 1-to-1, 1-to-many, many-to-1 or many-to-pair scenarios. For example, the accessed core corresponding to DMA can be pre-configured as CPU0, then when the core that initiates access is DMA, when the number of valid access requests sent by DMA reaches the preset number of times, the corresponding relationship can be initiated according to the corresponding relationship. For CPU0 access, a 1-to-1 scenario can be implemented at this time. Alternatively, the accessed cores corresponding to DMA can be pre-configured as CPU0 and CPU1. When the cores that initiate access are DMA, and the number of valid access requests sent by DMA reaches the preset number of times, the corresponding relationship can be initiated according to the corresponding relationship. The access of CPU0 and CPU1 can implement a one-to-many scenario at this time. Or, the accessed core corresponding to DMA and HAC can be pre-configured as CPU0, when the core that initiates access is DMA and HAC, and the sum of the number of valid access requests sent by DMA and the number of valid access requests sent by HAC When the preset number of times is reached, an access to CPU0 can be initiated according to the corresponding relationship, and a many-to-one scenario can be realized at this time. Alternatively, the accessed cores corresponding to DMA and HAC can be pre-configured as CPU0 and CPU1. When the cores that initiate access are DMA and HAC, and the number of valid access requests sent by DMA and the number of valid access requests sent by HAC When the sum reaches a preset number of times, an access to CPU0 and CPU1 can be initiated according to the corresponding relationship, and a many-to-many scenario can be realized at this time.

In this embodiment, by triggering the programmable unit, after the core that initiates the access sends the access request, the core to be accessed can be determined according to the corresponding relationship configured in the hardware unit, so as to realize inter-core communication. The overall performance can be improved through the proxy device. Multiple cores that initiate access can execute the access process in parallel, which improves the processing speed. By completing inter-core communication, it can ensure that the cores understand each other's status. By using messages to complete the inter-core communication, you can Improve the processing efficiency of the kernel.

Fig. 9 is a schematic flowchart of another inter-core communication method provided by an embodiment of the present invention. In this embodiment, a programmable unit is triggered and an access request is a message as an example. This embodiment includes:

91: The core that initiates the access sends an access request to the proxy device;

The difference from the embodiment shown in FIG. 7 is that the access request in this embodiment is a message, that is, the access request may include not only processor core ID and/or address information, but also message content. The message content may specifically be a bit string.

92: The proxy device judges whether the access request is valid, if so, execute 93, otherwise execute 95;

Different from the embodiment shown in FIG. 7, this embodiment judges whether it is valid or not according to the content of the message.

In this embodiment, two bit strings may be pre-configured, which are respectively called a first bit string and a second bit string. The first bit string may be represented as a mask, and the second bit string may be represented as a match.

Referring to Figure 10, the process of judging whether the access request is valid may include:

First, all or part of the bits of the message content included in the access request and the first bit string can be bitwise ORed, and bits that do not need to be detected can be shielded through this step. Wherein, all or part of the bits of the content of the message may be pre-configured.

Secondly, compare the bit string after the bitwise OR operation with the second bit string, if the two are the same, that is, every bit of the two is the same, it indicates that the access message is valid, otherwise it is invalid.

93: Trigger a preset programmable unit in the agent device when the access request is valid.

94: When the number of times the programmable unit is triggered reaches a preset number of times, the agent device initiates communication to the corresponding accessed processor core according to the preconfigured correspondence.

For the specific content of 93-94, please refer to 73-74, and will not repeat them here.

95: End.

Referring to FIG. 11 a and FIG. 11 b , schematic diagrams of inter-core communication in an interrupt mode and in a message mode are respectively shown. During specific visits, the corresponding relationship can be configured according to the actual situation to complete 1-to-1, 1-to-many, many-to-1 or many-to-pair scenarios. For example, the accessed core corresponding to DMA can be pre-configured as CPU0, then when the core that initiates access is DMA, when the number of valid access requests sent by DMA reaches the preset number of times, the corresponding relationship can be initiated according to the corresponding relationship. For CPU0 access, a 1-to-1 scenario can be implemented at this time. Alternatively, the accessed cores corresponding to DMA can be pre-configured as CPU0 and CPU1. When the cores that initiate access are DMA, and the number of valid access requests sent by DMA reaches the preset number of times, the corresponding relationship can be initiated according to the corresponding relationship. The access of CPU0 and CPU1 can implement a one-to-many scenario at this time. Or, the accessed core corresponding to DMA and HAC can be pre-configured as CPU0, when the core that initiates access is DMA and HAC, and the sum of the number of valid access requests sent by DMA and the number of valid access requests sent by HAC When the preset number of times is reached, an access to CPU0 can be initiated according to the corresponding relationship, and a many-to-one scenario can be realized at this time. Alternatively, the accessed cores corresponding to DMA and HAC can be pre-configured as CPU0 and CPU1. When the cores that initiate access are DMA and HAC, and the number of valid access requests sent by DMA and the number of valid access requests sent by HAC When the sum reaches a preset number of times, an access to CPU0 and CPU1 can be initiated according to the corresponding relationship, and a many-to-many scenario can be realized at this time.

In this embodiment, by triggering the programmable unit, after the core that initiates the access sends the access request, the core to be accessed can be determined according to the corresponding relationship configured in the hardware unit, so as to realize inter-core communication. The overall performance can be improved through the proxy device. Multiple cores that initiate access can execute the access process in parallel, which improves the processing speed. By completing inter-core communication, it can ensure that the cores understand each other's status. By using messages to complete the inter-core communication, you can Improve the processing efficiency of the kernel.

FIG. 12 is a schematic structural diagram of a proxy device provided by an embodiment of the present invention. The device is located between the core that initiates the access and the core that is accessed. The device 120 includes a receiving module 121, a processing module 122, and a sending module 123; the receiving module 121 is used to receive the access request sent by the core that initiates the access; the processing module 122 is used to determine the accessed core corresponding to the access request received by the receiving module according to the pre-configured correspondence; the sending module 123 is used to initiate the access request The communication of the accessed core determined by the processing module, so as to realize the communication between the access-initiating core and the accessed core.

Optionally, the processing module 122 includes:

A determining unit, configured to determine a hardware unit corresponding to the access request, wherein the hardware unit is pre-configured in the proxy device;

The hardware unit is configured to determine the accessed core corresponding to the access request according to its pre-configured correspondence.

Optionally, the processing module 122 includes:

A programmable unit, which includes a counter and a determination unit;

The counter is used to judge whether the number of times of triggering the programmable unit reaches a preset number of times, wherein each valid access request triggers the programmable unit once;

The determining unit is configured to determine the accessed core corresponding to the access request according to a pre-configured correspondence relationship when the determination result of the counter is that the preset number of times has been reached.

Optionally, the access request is an instruction, the instruction includes the processor core ID and/or address information of the core that initiates the access, and the device further includes:

A first judging module, configured to judge whether the access request is valid according to the processor core ID and/or address information, so as to determine the accessed core corresponding to the access request according to a pre-configured correspondence when valid .

Optionally, the access request is a message, and the device further includes:

The second decision module is used to perform a bitwise OR operation on all or part of the bits contained in the message and a preset first bit string; and perform a bitwise OR operation on the bitwise OR-operated bit string with a preset second bit Strings are compared, and if they are the same, it is determined that the access request is valid.

Referring to FIG. 13 , it is a schematic structural diagram of another proxy device provided by an embodiment of the present invention. The device 130 includes a receiver 131 , a processor 132 and a sender 133 . The receiver 131 is used to receive the access request sent by the core that initiates the access; the processor 132 is used to determine the accessed core corresponding to the access request according to the pre-configured correspondence; the transmitter 133 is used to initiate the access to the accessed core. The communication between the cores, so as to realize the communication between the core that initiates the access and the core that is accessed.

Optionally, the processor 132 is specifically configured to determine the hardware unit corresponding to the access request; the device may further include a hardware unit configured to determine the access request according to a pre-configured correspondence in the hardware unit. The core to be accessed corresponding to the request.

Optionally, the device includes a programmable unit, the programmable unit includes a counter and a processor, and the counter is used to judge whether the number of triggering the programmable unit reaches a preset number of times, wherein each valid access request triggers once The programmable unit; the processor 132 is configured to determine the accessed core corresponding to the access request according to the pre-configured corresponding relationship when the judgment result of the counter reaches the preset number of times.

Optionally, the access request is an instruction, the instruction includes the processor core ID and/or address information of the core that initiates the access, and the processor 132 is further configured to The information judges whether the access request is valid, so as to determine the accessed core corresponding to the access request according to the pre-configured correspondence relationship if valid.

Optionally, the access request is a message, and the processor 132 is further configured to perform a bitwise OR operation on all or part of the bits contained in the message and a preset first bit string; The bit string is compared with the preset second bit string, and if they are the same, it is determined that the access request is valid.

In terms of specific implementation, the above-mentioned receiver and transmitter may specifically be a receiving interface and a sending interface, and the above-mentioned processor may be specifically a central processing unit (CPU), a microprocessor, a single-chip microcomputer, and the like. In addition, the device may also include general modules such as a bus, a memory, and a timer.

In this embodiment, an agent device is set between the core that initiates the access and the core that is accessed, and the corresponding relationship is pre-configured in the agent device. According to the corresponding relationship, the communication between the core that initiates the access and the core that is accessed can be realized. The processing speed is increased and the complexity can be reduced, thereby improving the processing performance of inter-core communication.

Those skilled in the art can clearly understand that for the convenience and brevity of description, only the division of the above-mentioned functional modules is used as an example for illustration. In practical applications, the above-mentioned function allocation can be completed by different functional modules according to needs. The internal structure of the device is divided into different functional modules to complete all or part of the functions described above. For the specific working process of the above-described system, device, and unit, reference may be made to the corresponding process in the foregoing method embodiments, and details are not repeated here.

In the several embodiments provided in this application, it should be understood that the disclosed system, device and method can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of the modules or units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be Incorporation may either be integrated into another system, or some features may be omitted, or not implemented. In another point, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces, and the indirect coupling or communication connection of devices or units may be in electrical, mechanical or other forms.

The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place, or may be distributed to multiple network units. Part or all of the units can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, each unit may exist separately physically, or two or more units may be integrated into one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software functional units.

If the integrated unit is realized in the form of a software function unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium , including several instructions to make a computer device (which may be a personal computer, server, or network device, etc.) or a processor (processor) execute all or part of the steps of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM, Read-OnlyMemory), random access memory (RAM, RandomAccessMemory), magnetic disk or optical disk and other media that can store program codes.

As mentioned above, the above embodiments are only used to illustrate the technical solutions of the present application, and are not intended to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still understand the foregoing The technical solutions described in each embodiment are modified, or some of the technical features are equivalently replaced; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the various embodiments of the application.

Claims (6)

1. A method for inter-core communication, comprising: The proxy device receives the access request sent by the core that initiates the access; The proxy device determines the accessed core corresponding to the access request according to the pre-configured correspondence; The agent device initiates communication with the accessed core, so as to realize the communication between the access-initiating core and the accessed core; Wherein, the proxy device is located between the core that initiates access and the core that is accessed; The proxy device determines the accessed core corresponding to the access request according to the pre-configured correspondence, including: The agent device judges whether the number of times of triggering the programmable unit reaches a preset number of times, wherein the programmable unit is pre-configured in the agent device, and each valid access request triggers the programmable unit once; When the judging result is that the preset number of times is reached, the agent device determines the core to be accessed corresponding to the access request according to a pre-configured correspondence. 2. The method according to claim 1, wherein the access request is an instruction, and the instruction includes the processor core ID and/or address information of the core that initiates the access, and the method further comprises: The proxy device judges whether the access request is valid according to the processor core ID and/or address information, so as to determine the accessed core corresponding to the access request according to a pre-configured correspondence relationship if valid. 3. The method according to claim 1, wherein the access request is a message, and the method further comprises: performing a bitwise OR operation on all or part of the bits contained in the message and a preset first bit string; The bit string after the bitwise OR operation is compared with the preset second bit string, and if they are the same, it is determined that the access request is valid. 4. A proxy device, characterized in that the proxy device is located between the core that initiates the access and the core that is accessed, and the device includes: A receiving module, configured to receive an access request sent by the core that initiates the access; a processing module, configured to determine the accessed core corresponding to the access request received by the receiving module according to a pre-configured correspondence; a sending module, configured to initiate communication with the accessed core determined by the processing module, so as to realize communication between the access-initiating core and the accessed core; The processing modules include: A programmable unit, which includes a counter and a determination unit; The counter is used to judge whether the number of times of triggering the programmable unit reaches a preset number of times, wherein each valid access request triggers the programmable unit once; The determining unit is configured to determine the accessed core corresponding to the access request according to a pre-configured correspondence relationship when the determination result of the counter reaches a preset number of times. 5. The device according to claim 4, wherein the access request is an instruction, the instruction includes the processor core ID and/or address information of the core that initiates the access, and the device further comprises: A first judging module, configured to judge whether the access request is valid according to the processor core ID and/or address information, so as to determine the accessed core corresponding to the access request according to a pre-configured correspondence when valid . 6. The device according to claim 4, wherein the access request is a message, and the device further comprises: The second decision module is used to perform a bitwise OR operation on all or part of the bits contained in the message and a preset first bit string; and perform a bitwise OR operation on the bitwise OR-operated bit string with a preset second bit Strings are compared, and if they are the same, it is determined that the access request is valid.