CN103187388B - The semiconductor device of encapsulation and the method for encapsulated semiconductor device - Google Patents

Abstract

Mechanisms are provided for forming a molding compound on a semiconductor device substrate to enable fan-out structures in wafer-level packaging (WLP). This mechanism includes covering part of the surface of the insulating layer surrounding the contact pad. This mechanism improves package reliability and process control of the packaging process. This mechanism also reduces the risk of interfacial delamination, and excessive outgassing of the insulating layer during subsequent processing. This mechanism also improves the determination of the end point of planarization. By utilizing a protective layer between the contact pad and the insulating layer, copper outdiffusion can be reduced and adhesion between the contact pad and the insulating layer can also be improved. The invention provides a packaged semiconductor device and a method of packaging a semiconductor device.

Description

Packaged semiconductor device and method of packaging semiconductor device

Cross References to Related Applications

This application is related to the following co-pending and commonly assigned patent application: Serial No. 13/228,244, filed September 8, 2011, entitled "Packaging Methods and Structures Using a Die Attach Film," the entirety of which The content is incorporated into this application.

technical field

The present invention relates to semiconductor packaging, and in particular, to a packaged semiconductor device and a method of packaging a semiconductor device.

Background technique

Semiconductor devices are used in various electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are generally fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of materials over a semiconductor substrate, and patterning the various material layers using photolithography to form circuit elements and components thereon.

The semiconductor industry continues to increase the integration density of various electronic components (eg, transistors, diodes, resistors, capacitors, etc.) by continually reducing the minimum feature size, which allows more components to be integrated into a given area. In certain applications, these smaller electronic components also require smaller packages that utilize less area than packages of the past.

Accordingly, new packaging technologies have begun to be developed such as wafer level packaging (WLP), in which an integrated circuit (IC) is placed on a carrier with wiring for establishing connections to the IC and other electrical components. These relatively new packaging technologies for semiconductors face manufacturing challenges.

Contents of the invention

In one aspect, the present invention relates to a packaged semiconductor device comprising: a contact pad on a semiconductor die; an insulating layer surrounding the contact pad; and a molding compound surrounding the insulating layer, wherein the mold Plastic is in contact with two adjacent and non-linear surfaces of the insulating layer.

In the packaged semiconductor device, a wiring layer is disposed on and physically connected to the contact pad, wherein the wiring layer extends beyond a boundary of the semiconductor die.

In the packaged semiconductor device, the insulating layer surrounding the contact pad has a thin portion and a thick portion, and wherein a thickness of the thin portion is in a range of about 1 μm to about 30 μm.

In the packaged semiconductor device, a protective layer is located between the contact pad and the insulating layer.

In the packaged semiconductor device, the protective layer is a copper diffusion barrier.

In the packaged semiconductor device, the protective layer has a thickness in the range of about 50 nm to about 2 μm.

In the packaged semiconductor device, the protective layer is also located between the insulating layer and another underlying insulating layer.

In the packaged semiconductor device, the protective layer is a dielectric material and includes a material selected from the group consisting of SiN, SiC, SiCN, SiCO, TEOS, _SiO2 or a low-k dielectric.

In the packaged semiconductor device, the dielectric material also improves the adhesion between the contact pad and the insulating layer.

In the packaged semiconductor device, the protective layer is a conductive material and is made of a material selected from the group consisting of Ta, TaN, Ti, TiN, Co, and Mn.

In the packaged semiconductor device, the contact pads are copper pillars and have an under bump metallization layer underneath.

In the packaged semiconductor device, the thickness of the contact pad is greater than the thickness of the insulating layer.

In another aspect, the present invention also provides a packaged semiconductor device, comprising: a contact pad located on the semiconductor die; an insulating layer surrounding the contact pad; a protective layer, wherein the protective layer is located on the between a contact pad and the insulating layer; and a molding compound surrounding the insulating layer, wherein the molding compound is in contact with two adjacent and non-linear surfaces of the insulating layer.

In yet another aspect, the present invention provides a method of packaging a semiconductor device, the method comprising: providing a semiconductor device, wherein the semiconductor device has a contact pad; forming an insulating layer over the semiconductor device, wherein the The thickness of the contact pad is greater than the thickness of the insulating layer; a molding compound is formed to cover the semiconductor device and a space between the semiconductor device and an adjacent semiconductor device, wherein the two semiconductor devices are located on the carrier on a wafer; and planarizing the surface of the semiconductor device by removing the molding compound and the insulating layer over the bonding pads.

The method further includes forming a redistribution layer (RDL) over the semiconductor device, wherein the RDL is connected to the contact pad, and wherein the RDL extends beyond a boundary of the semiconductor device outside.

The method further includes: forming a protective layer between the contact pad and the insulating layer.

In the method, the protective layer has a thickness in the range of about 50 nm to about 2 μm.

In the method, planarization of the surface is carried out by grinding.

In the method, the contact pads are copper pillars and have a thickness in the range of about 1 μm to about 35 μm.

In the method, the protection layer not surrounding the contact pad is removed by etching.

Description of drawings

For a fuller understanding of the present invention and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings, in which:

1A-1H are cross-sectional views of a semiconductor device in a fan-out wafer-level package (FO-WLP) at various packaging stages, according to some embodiments.

1I is an enlarged cross-sectional view of the packaged semiconductor device of FIG. 1H in accordance with some embodiments.

2A-2C are enlarged cross-sectional views of a portion of a semiconductor device in a fan-out wafer-level package (FO-WLP) depicted in FIGS. 1B , 1C and 1D , respectively, according to some embodiments.

3A-3B are cross-sectional views of sequential processing of a semiconductor device in a fan-out wafer-level package (FO-WLP) at various packaging stages, according to some embodiments.

3C is an enlarged cross-sectional view of a packaged semiconductor device according to some embodiments.

4A-4B are cross-sectional views of a semiconductor device in a fan-out wafer-level package (FO-WLP) at various packaging stages, according to some embodiments.

4C is an enlarged cross-sectional view of a packaged semiconductor device according to some embodiments.

5A-5B are cross-sectional views of a semiconductor device in a fan-out wafer-level package (FO-WLP) at various packaging stages, according to some embodiments.

Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

detailed description

The making and using of embodiments of the invention are discussed in detail below. It should be appreciated, however, that the present invention provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the invention, and do not limit the scope of the invention.

1A to 1I are cross-sectional views of a semiconductor device at various packaging stages according to an embodiment of the present invention. Referring first to FIG. 1A , a carrier wafer 100 is provided. As examples, carrier wafer 100 may comprise glass, silicon oxide, aluminum oxide, and the like. The thickness of the carrier wafer 100 may range from about a few mils to tens of mils, and may include a diameter of about 300 mm in some embodiments. The carrier wafer 100 functions as a carrier wafer processed during packaging of semiconductor devices or dies 104 (see FIG. 1B ) for fan-out, which means electrical connections beyond the boundary of the semiconductor die.

In some embodiments, a die-bonding film (DAF) 102 is formed over the carrier wafer 100, as shown in FIG. 1A. DAF 102 may comprise polymers, and in some embodiments thermoplastics. DAF 102 can be a liquid, such as a viscous liquid, which is liquid when applied but forms a solid at room temperature, and which can become semi-liquid when heated, and which can become viscous at elevated temperatures to act as an adhesive kick in.

Next, as shown in FIG. 1B , a plurality of dies 104 are bonded to DAF 102 . As an example, depending on the size of the die 104 , the size of the carrier wafer 100 , and the specific application, tens of dies 104 or hundreds of dies 104 or more may be bonded to the DAF 102 . Herein, for purposes of discussion, die 104 has a front side 103a and a back side 103b. The front side 103a of the die 104 is also referred to herein as the first side, and the back side 103b is also referred to herein as the second side. Die 104 includes semiconductor devices or integrated circuits that have been previously fabricated on a semiconductor substrate. Die 104 may include one or more layers of circuitry and/or electronic functional elements formed thereon, and may include, for example (not shown) wires, vias, capacitors, diodes, transistors, resistors, inductors, and / or other electrical components. After fabrication, the dies 104 are separated from each other and ready for packaging. For example, the die 104 may be placed in predetermined locations on the carrier wafer 100 using a pick and place machine. As shown in FIG. 1B , the backside 103b of the die 104 is bonded to the DAF 102 .

Next, a packaging process is performed to package each of the plurality of dies 104 . In some embodiments as depicted in FIGS. 1A-1I , to package dies 104 , first, molding compound 106 is formed over dies 104 and over exposed portions of DAF 102 , as shown in FIG. 1C . As shown, molding compound 106 may be molded onto die 104 and DAF 102 over carrier wafer 100 . The top surface of molding compound 106 may be higher (as shown in FIG. 1C ), flush (as shown in FIG. 1D ), or slightly lower than top surface 104 a of die 104 . As shown, the molding compound 106 is filled into the gaps between the plurality of dies 104 . Further details of the mold forming process are discussed below.

Next, a planarization process, such as a grinding process, may be performed to planarize the top surfaces 104a of the plurality of dies 104 such that any non-uniformity in the top surfaces 104a of the dies 104 may be at least reduced and possibly substantially eliminated. If the molding compound 106 includes portions on the top surface 104 a of the die 104 , these portions of the molding compound 106 are also removed by the grinding process, as shown in FIG. 1D . Accordingly, the top surface 106 a of the remainder of the molding compound 106 is flush with the top surfaces 104 a of the plurality of dies 104 . In addition, the height or thickness of the plurality of dies 104 can also be reduced to a predetermined height through a grinding process.

A wiring layer 108 is formed over the top surfaces 104a of the plurality of dies 104, eg, on the front sides 103a of the dies 104, as shown in FIG. 1E. The wiring layer 108 may include one or more redistribution layers (RDLs), which will be discussed further herein with reference to FIG. 1I . The RDL layer is surrounded by one or more dielectric layers. Part of the RDL may extend beyond the boundaries of die 104 . As a result, better connectivity and design flexibility can be achieved. RDL enables fan-out design for wafer-level packaging (WLP).

The structure shown in FIG. 1E includes, for example, a rebuilt wafer positioned over a carrier wafer 100 including a plurality of dies 104 . A plurality of solder balls 110 are formed over portions of the wiring layer 108, as shown in FIG. 1F. At this stage of the manufacturing and packaging process, the packaged die 104 may optionally be tested, for example, by performing electrical and functional tests.

In some embodiments, packaged die 104 includes molding compound 106 , wiring layer 108 , solder balls 110 , and DAF 102 . In other embodiments, DAF 102 is removed so that the packaged die includes molding compound 106 , wiring layer 108 and solder balls 110 .

Next, according to some embodiments, at least the carrier wafer 100 is removed from the packaged die 104 as shown in FIG. 1G . For example, the molding compound 106 and the wiring layer 108 support the die 104 during the process of debonding the carrier wafer 100 from the packaged die 104 . In the embodiment shown in FIGS. 1A-1I , DAF 102 remains on backside 103b of die 104 as shown. Alternatively, the DAF 102 may be removed when removing the carrier wafer 100 or in a separate processing step, for example using a light (laser) or thermal process.

The packaged dies 104 are then singulated or separated at a singulation line 114 to form individual packaged dies 104, hereinafter also referred to as packaged semiconductor devices 120, as shown in FIG. 1H. Molding compound 106 is disposed within packaged semiconductor device 120 adjacent to the edge of die 104 between wiring layer 108 and DAF 102 , which protects the edge of die 104 . To separate a packaged die 104 from adjacent packaged die 104 , as also shown in FIG. 1G , a tape 112 may be applied to the solder balls 110 on the front side 103 a of the die 104 . Tape 112 includes a dicing tape that supports packaged die 104 during a singulation process. Packaged semiconductor device 120 is then removed from tape 112, as shown in FIG. 1H.

FIG. 1I is an enlarged cross-sectional view of the packaged semiconductor device 120 shown in FIG. 1H in accordance with some embodiments. FIG. 1I also shows optional tape 122 that may be applied over DAF 102 after carrier wafer 100 is removed. In some embodiments, optional tape 122 may include marking tape suitable for marking with laser marking. In other embodiments, DAF 102 may comprise a material suitable for marking, eg, with a laser, and strip 122 may not be included in the structure. After solder balls 110 are formed, testing may be performed on die 104 and, for example, tape 122 or DAF 102 may be marked to indicate the results of the testing. Packaged die 104 may also be marked before or after separation for various other reasons.

FIG. 1I also shows a more detailed view of die 104 and wiring layer 108 , according to some embodiments. The views of die 104 and routing layer 108 are exemplary; alternatively, die 104 and routing layer 108 may include other structures, layouts, and/or designs. In the illustrated embodiment, die 104 includes a substrate 124 comprising silicon or other semiconductor material. The insulating layers 126 a and 126 b may include a passivation layer disposed on the substrate 124 . Contact pads 128 of die 104 may be formed over conductive features of the substrate, such as metal pads 127 , plugs, vias, or wires, to make electrical contact with electrical elements (not shown) of substrate 124 . The contact pads 128 may be formed in an insulating layer 126c, which may include a polymer layer or other insulating material.

The wiring layer 108 may include insulating layers 132a and 132b comprising polymer or other insulating materials. As shown, RDL 130 may be formed within insulating layers 132 a and 132 b , with portions of RDL 130 making electrical contact with contact pads 128 on die 104 . As shown, an optional under bump metallization (UBM) structure (or layer) 134 may be formed on portions of RDL 130 and insulating layer 132b. UBM structure 134 facilitates, for example, connection and formation of solder ball 110 . Further details of methods of packaging semiconductor devices are described in US Patent Application Serial No. 13/228,244, filed September 8, 2011, entitled "Packaging Methods and Structures Using a Die Attach Film."

FIG. 2A is an enlarged view of region 150 of FIG. 1B according to some embodiments. Region 150 is a portion of die 104 and includes substrate 124 as depicted in FIG. 1I . As noted above, there are devices in the substrate 124, which includes silicon and/or other semiconductor materials. Overlying the substrate 124 is an insulating layer 126a that isolates and separates conductive structures (not shown). The insulating layer 126a may include undoped silicon oxide, a low dielectric constant (low-k) dielectric, a doped dielectric film, or a combination thereof. In some embodiments, the low-k dielectric may have a dielectric constant less than 3.5. In other embodiments, the low-k dielectric may have a dielectric constant less than 2.5.

Figure 2A shows that region 150 also includes metal pad 127, which may be made of aluminum or other suitable material. Metal pads 127 are connected to devices on substrate 124 through interconnect structures (not shown). A contact pad 128' is formed on the metal pad 127. Referring to FIG. In some embodiments, metal pad 128' is made of copper and is formed over metal pad 127 and UBM layer 129 (not shown in FIG. 1I for clarity). The UBM layer 129 may include a copper diffusion barrier, which may be a titanium layer, a titanium nitride layer, a tantalum layer, or a tantalum nitride layer. The UBM layer 129 may also include a seed layer, which may include copper or a copper alloy. However, other metals may also be included, such as silver, gold, aluminum, and combinations thereof.

In some embodiments, the contact pads 128' are copper pillars and are formed by electroplating. The insulating layer 126b serves to isolate the contact pad 128' and a portion of the UBM layer 129 from the metal pad 127. The insulating layer 126b may be made of one or more dielectric layers, which may include oxide, nitride, polyimide, insulating polymer, or other suitable materials. The insulating layer 126c' covers the insulating layer 126b and the contact pad 128'. As noted above, the insulating layer 126c' may include a polymer layer or other insulating material. Exemplary polymeric materials that may be used for insulating layer 126c may include epoxy, polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and the like, although other relatively comparable polymer materials may also be used. Soft (usually organic) dielectric material.

In some embodiments, the height D' of the contact pad 128, measured above the insulating layer 126b, is in the range of about 1 μm to about 25 μm. The height H' of the insulating layer 126c' measured above the insulating layer 126b is in the range of about 1 µm to about 30 µm.

Figure 2B is an enlarged view of region 150' of Figure 1C, according to some embodiments. FIG. 2B shows molding compound 106 covering die 104 . Partial fan-out structures, such as RDL 130 , will be built over molding compound 106 as described and illustrated above in FIG. 1I . According to some embodiments, molding compound 106 is initially in liquid form and dries after being dispersed on carrier wafer 100 . For example, molding compound 106 may include epoxy, resin, silica filler, or other additives.

FIG. 2C is an enlarged view of region 150" of FIG. 1D according to some embodiments. FIG. 2C shows that portions of molding compound 106, insulating layer 126c, and possibly a portion of the metal pad have been removed by a planarization process, such as grinding. 128, thereby removing excess material from the surface of the contact pad 128' and planarizing the substrate surface of FIG. 2B. Afterwards, according to some embodiments, as shown in FIG. Wafer 100 having the structure of FIG. 2C ) is sent to the other packaging processes described above in FIGS. 1E-1H to make the packaged substrate. Interface 142' is located between contact pad 128' and dielectric layer 126c'.

The following process operations involving mounting balls 110 performed on an unfinished package (having the structure of FIG. 2C on carrier wafer 100 ) may place significant stress on packaged die 120 . As shown in FIG. 2C, the interface 141' between the insulating layer 126c' and the molding compound 106 is linear, or vertical. In some embodiments, the linear interface 141' is relatively weak and may cause delamination under stress. Furthermore, when performing a planarization operation on the substrate of FIG. 2B to remove portions of the molding compound 106 and insulating layer 126c', and possibly a portion of the contact pads 128', determining the end point of the planarization process can be challenging. The end of the planarization process can be determined by detecting the different torque forces experienced by a planarization tool, such as a grinder, as the removed material changes from the molding compound 106 to the insulating layer 126c' and then to the contact pads 128' . In some embodiments, endpoint is determined by inspection of contact pad 128' by a planarization tool. Determining the end point of the planarization process is challenging when the planarization tool needs to identify the junction of two different types of surfaces (the insulating layer 126c' and the contact pad 128').

In addition to the issues discussed above, the exposed surface 333' of insulating layer 126c' may release chemicals during the formation of insulating layer 132a and RDL 130 in subsequent processing. As described above, the insulating layer 126c' may be made of a polymer that is decomposed by a plasma process, a sputtering process, or ashing of a photoresist. Chemicals released from insulating layer 126c' may redeposit on interface 334' between contact pad 128' and RDL 130 and cause an increase in interface resistance. Because of at least these issues, according to some embodiments, there is a need to improve the mechanisms of forming molded structures shown in FIGS. 2A-2C and their subsequent structures leading to the formation of packaged semiconductor devices.

Figure 3A shows a more detailed cross-sectional view of region 150' of Figure 1C, according to some embodiments. The height D" of the contact pad 128" of FIG. 3A is higher than the height D' of FIG. 2A. In some embodiments, the height D" is in the range of about 1 μm to about 35 μm. The height H' of the insulating layer 126" is in the range of about 1 μm to about 30 μm. The surface 145 of the insulating layer 126c" is lower than the surface 434 of the contact pad 128". If insulating layer 126c" is formed by dispensing (such as by a spin coating process) a liquid containing a polymer or a precursor to a polymer, a thin layer 126c* of insulating layer 126c" is formed over contact pad 128". In some implementations In one example, thin layer 126c* has a thickness in the range of about 0.01 μm to about 3 μm. Exemplary polymeric materials suitable for forming insulating layer 126c″ have been described above. In some embodiments, a curing process is then performed to drive out moisture or solvents in the film. Figure 3A shows molding compound 106 covering die 104 with insulating layer 126c".

3B is an enlarged view of region 150″ of FIG. 1D according to some embodiments. FIG. 3B shows that portions of molding compound 106, dielectric layer 126c″ over contact pads 128″ have been removed and planarized, such as by grinding. and contact pads 128". According to some embodiments, the unfinished substrate package is then sent to undergo an additional packaging process such as that described in FIGS. 1E to 1H to fabricate a packaged semiconductor device. Figure 3C shows a more detailed cross-sectional view of the packaged semiconductor device 120' according to some embodiments.

For the structure shown in FIG. 3B, the interface 141" between the molding compound 106 and the dielectric layer 126c" is not a single linear interface. Instead, according to some embodiments, as shown in FIG. 3C , interface 141 ″ has three segments, linear surfaces 141A ″, 141B ″, and 141C ″ connected to each other. The interface 141" is mechanically stronger than the single linear interface 141' described above, and can withstand more stress without delamination. In addition, the molding compound 106 and the dielectric layer 126c* and possibly a part of the During the planarization process of the contact pads 128", there is only a thin dielectric layer 126c* over the contact pads 128". In contrast to structures that do not have the thin dielectric layer 126c* over the contact pads 128" This makes it easier and more accurate to determine the end point of flattening than . Because, once the torque force changes due to the planarization tool contacting the dielectric layer 126c*, the planarization tool will quickly contact the contact pad 128". The determination of the end point will be more accurate. For example, the fixation after the torque force change can be set time to stop the planarization process. In addition, the risk of higher interfacial resistance on the interface 334" of the contact pad 128" is greatly reduced. This is due to the exposed surface 333" of the dielectric layer 126c" (compared to FIG. 2C The surface 333') described in ) is greatly reduced. Therefore, the amount of chemical species released from the dielectric layer 126c" is also greatly reduced. Thus, the risk of redeposition of chemicals released from the dielectric layer 126c" on the interface 334" is minimized.

For some packages, as shown in Figure 2C, delamination at the interface 142' (see Figure 2C) between the contact pad 128' and the dielectric layer 126c' is involved. Additionally, if the contact pads 128', 128" include copper, for some packages, metal diffusion of the contact pads 128', 128" may also be involved. As a result, according to some embodiments, as shown in FIG. 4A , a protective layer 135 may be deposited to surround the contact pad 128″. The protective layer 135 may be made of a dielectric material including SiN, SiC, SiCN, SiCO , TEOS, SiO ₂ , low-k dielectrics, etc. For example, the low-k dielectric may have a dielectric constant less than about 3.5. The protective layer 135 also improves the adhesion between the dielectric layer 126c" and the contact pad 128" In some embodiments, the thickness of the protective layer 135 is in the range of about 50 nm to about 2 μm. According to some embodiments, the process of forming the dielectric layer 126c "and the molding compound 106 is the same as that described above in FIGS. 3A and 3B The process described is similar. Then, the molding compound 106, the dielectric layer 126c" and the portion of the protective layer 135 over the contact pad 128" are removed.

4B shows a cross-sectional view of the structure after planarization to remove material over contact pad 128″, according to some embodiments. Protective layer 135 covers the sidewalls of contact pad 128″ and reduces the contact pad 128″. Out-diffusion of copper. In addition, the protective layer 135 also improves the adhesion between the contact pad 128" and the dielectric layer 126c". FIG. 4C shows a cross-sectional view of a packaged semiconductor device 120" according to some embodiments.

In some embodiments, the protective layer 135' can be made of a conductive material sufficient to prevent copper diffusion, such as Ta, TaN, Ti, TiN, Co, Mn, or combinations thereof. 5A shows a protective layer 135' covering the sidewalls of contact pads 128" on the substrate 124 according to some embodiments. The protective layer 135' does not cover the surface of the dielectric layer 126b. After forming the dielectric layer 126c" Previously, the protective layer 135' over the surface of the dielectric layer 126b was removed by etching. In some embodiments, the etching process is a dry plasma process. A molding compound 106 is then deposited on the substrate. Portions of molding compound 106, dielectric layer 126c*, capping layer 135' over contact pads 128" are then removed by planarization. Figure 5B shows a cross-sectional view of Figure 5A after a planarization operation, according to some embodiments.

Mechanisms are provided for forming molding compounds on semiconductor device substrates to enable fan-out structures in wafer-level packaging (WLP). This mechanism includes covering part of the surface of the insulating layer surrounding the contact pad. This mechanism improves package reliability and process control of the packaging process. This mechanism also reduces the risk of interfacial delamination and excessive outgassing of the insulating layer during subsequent processing. This mechanism also improves the determination of the end point of planarization. By utilizing a protective layer between the contact pad and the insulating layer, copper outdiffusion can be reduced and adhesion between the contact pad and the insulating layer can also be improved.

In some embodiments, a packaged semiconductor device is provided. The packaged semiconductor device includes a contact pad on a semiconductor die; and an insulating layer surrounding the contact pad. The packaged semiconductor device also includes a molding compound surrounding the insulating layer, and the molding compound is in contact with two adjacent and non-linear surfaces of the insulating layer.

In some other embodiments, a packaged semiconductor device is provided. The packaged semiconductor device includes a contact pad on a semiconductor die; and an insulating layer surrounding the contact pad. The packaged semiconductor device also includes a protective layer; and the protective layer is located between the contact pad and the insulating layer. The packaged semiconductor device also includes a molding compound surrounding the insulating layer, and the molding compound is in contact with two adjacent and non-linear surfaces of the insulating layer.

In yet other embodiments, a method of packaging a semiconductor device is provided. The method includes providing a semiconductor device, and the semiconductor device has contact pads. The method also includes forming an insulating layer over the semiconductor device, and the thickness of the contact pad is greater than the thickness of the insulating layer. The method also includes forming a molding compound to cover the semiconductor device and a space between the semiconductor device and adjacent semiconductor devices. Both semiconductor devices are located on a carrier wafer. Additionally, the method includes planarizing the surface of the semiconductor device by removing the molding compound and the insulating layer over the contact pads.

Although the embodiments of the present invention and its advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made therein without departing from the spirit and scope of the invention as defined by the appended claims. For example, it will be readily understood by those skilled in the art that changes may be made in the components, functions, processes, and materials described herein and remain within the scope of the invention. Moreover, the scope of the present application is not limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. Those of ordinary skill in the art will readily understand from the present invention that existing or later developed processes for performing substantially the same functions or obtaining substantially the same results as the corresponding embodiments described herein can be utilized in accordance with the present invention , machine, manufacture, composition of material, device, method or step. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps.

Claims (20)

1. A packaged semiconductor device comprising: contact pads on the semiconductor die; an insulating layer surrounding the contact pad, wherein the insulating layer surrounding the contact pad has a thin portion and a thick portion; and a molding compound surrounding the insulating layer, wherein the molding compound is in contact with two adjacent and non-linear surfaces of the insulating layer, and the top surface of the molding compound is in contact with the thick The top surfaces of the parts are coplanar. 2. The packaged semiconductor device of claim 1 , wherein a wiring layer is disposed over and physically connected to the contact pad, wherein the wiring layer extends to an edge of the semiconductor die. outside the borders. 3. The packaged semiconductor device according to claim 1, wherein a thickness of the thin portion is in a range of 1 μm to 30 μm. 4. The packaged semiconductor device of claim 1, wherein a protective layer is located between the contact pad and the insulating layer. 5. The packaged semiconductor device of claim 4, wherein the protective layer is a copper diffusion barrier. 6. The packaged semiconductor device according to claim 4, wherein the protective layer has a thickness in the range of 50 nm to 2 μm. 7. The packaged semiconductor device of claim 4, wherein the protective layer is also located between the insulating layer and an underlying another insulating layer. 8. The packaged semiconductor device of claim 4, wherein the protective layer is a dielectric material and comprises a material selected from the group consisting of SiN, SiC, SiCN, SiCO, TEOS, SiO, or a low- _k dielectric . 9. The packaged semiconductor device of claim 8, wherein the dielectric material also improves adhesion between the contact pad and the insulating layer. 10. The packaged semiconductor device of claim 4, wherein the protective layer is a conductive material and is made of a material selected from the group consisting of Ta, TaN, Ti, TiN, Co, and Mn. 11. The packaged semiconductor device of claim 1, wherein the contact pad is a copper pillar and has an under bump metallization layer underneath. 12. The packaged semiconductor device of claim 1, wherein a thickness of the contact pad is greater than a thickness of the insulating layer. 13. A packaged semiconductor device comprising: contact pads on the semiconductor die; an insulating layer surrounding the contact pad; a protective layer, wherein the protective layer is located between the contact pad and the insulating layer; and A molding compound surrounds the insulating layer, wherein the molding compound is in contact with two adjacent and non-linear surfaces of the insulating layer. 14. A method of packaging a semiconductor device, the method comprising: providing a semiconductor device, wherein the semiconductor device has contact pads; forming an insulating layer over the semiconductor device, wherein a thickness of the contact pad is greater than a thickness of the insulating layer; forming a molding compound to cover the semiconductor device and a space between the semiconductor device and an adjacent semiconductor device, wherein both semiconductor devices are on the carrier wafer; and planarizing the surface of the semiconductor device by removing the molding compound and the insulating layer over the contact pads, Wherein, the insulating layer surrounds the contact pad, and the insulating layer surrounding the contact pad has a thin portion and a thick portion, and the top surface of the molding compound is in contact with the thick portion of the insulating layer. The top faces are coplanar. 15. The method of claim 14, further comprising: forming a redistribution layer (RDL) over the semiconductor device, wherein the redistribution layer (RDL) is connected to the contact pad, and wherein the redistribution layer (RDL) extends to the semiconductor device outside the boundaries of . 16. The method of claim 14, further comprising: A protective layer is formed between the contact pad and the insulating layer. 17. The method according to claim 16, wherein the protective layer has a thickness in the range of 50 nm to 2 μm. 18. The method of claim 14, wherein planarizing the surface is performed by grinding. 19. The method of claim 14, wherein the contact pads are copper pillars and have a thickness in the range of 1 μm to 35 μm. 20. The method of claim 16, wherein the protective layer not surrounding the contact pad is removed by etching.